CN110380720B - Universal pin multiplexing circuit - Google Patents
Universal pin multiplexing circuit Download PDFInfo
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- CN110380720B CN110380720B CN201910578489.3A CN201910578489A CN110380720B CN 110380720 B CN110380720 B CN 110380720B CN 201910578489 A CN201910578489 A CN 201910578489A CN 110380720 B CN110380720 B CN 110380720B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
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Abstract
The invention provides a universal pin multiplexing circuit which is suitable for the technical field of electronization in the automobile industry. The multiplexing circuit comprises a driving circuit, a power output circuit, a resistance voltage division network, a first control pin, a detection input pin and a general pin, wherein the first control pin is used for connecting a first output port of a processor, and the detection input pin is used for connecting an input port of the processor; the first control pin is connected with an enabling port of the power output circuit through a first driving branch of the driving circuit, and a power output port of the power output circuit is connected with the general pin; the detection input pin is connected with an input port of the resistance voltage division network, and an output port of the resistance voltage division network is connected with the general pin. The universal pin of the multiplexing circuit can be used as an output pin and an input pin, and the utilization rate of the universal pin is effectively improved as the universal pin integrates input and output functions.
Description
Technical Field
The invention relates to a universal pin multiplexing circuit which is suitable for the technical field of electronization in the automobile industry.
Background
At present, more and more electronic devices are mounted on automobiles, and various types of power input and output interfaces of the devices need to be connected to a vehicle body control module or an instrument, but external interfaces of the vehicle body control module or the instrument are limited; moreover, when the vehicle configurations are different, the number of power output pins and the number of input pins of different types required by the vehicle body control module or the instrument are different, and the common practice of the traditional vehicle body control module or the instrument manufacturer is to configure a single pin into a single input or output function, so that the pin resource is consumed greatly, and the cost of the vehicle body control module or the instrument is increased indirectly.
In the prior art, a plurality of universal pin multiplexing circuits exist, for example, the universal pin multiplexing circuit disclosed in the invention patent document with an authorization publication number of CN104993815B and the invention patent application document with an application publication number of CN108566191a can provide a plurality of input options on a single input port, and although the pin utilization rate is improved to a certain extent, the universal pin can only be used as an input pin, the function is still single, and the universal pin utilization rate still needs to be further improved.
Disclosure of Invention
The invention aims to provide a universal pin multiplexing circuit, which is used for solving the problem that the universal pin in the existing universal pin multiplexing circuit can only be used as an input pin, has single function and causes low utilization rate of the universal pin.
In order to achieve the above object, the present invention provides a general-purpose pin multiplexing circuit, which includes a driving circuit, a power output circuit, a resistor voltage-dividing network, a first control pin, a detection input pin and a general-purpose pin, wherein the first control pin is used for connecting to a first output port of a processor, and the detection input pin is used for connecting to an input port of the processor; the first control pin is connected with an enabling port of the power output circuit through a first driving branch of the driving circuit, and a power output port of the power output circuit is connected with the general pin; the detection input pin is connected with an input port of the resistance voltage division network, and an output port of the resistance voltage division network is connected with the universal pin.
The invention has the beneficial effects that: configuring a first control pin of the multiplexing circuit to be at a low level or a high level by using a processor to control a first driving branch of a driving circuit to be switched on or switched off so as to control whether a power output circuit is enabled or not, wherein when the power output circuit is enabled, a general pin of the multiplexing circuit is used as the power output pin; when the power output circuit is not enabled, the universal pin of the multiplexing circuit is used as an analog voltage input pin; that is to say, the general pin of the multiplexing circuit can be used as an output pin and an input pin, and the general pin integrates the input function and the output function, so that the utilization rate of the general pin is effectively improved.
In order to enable the general pin to be used as a switching value input pin, so that the general pin can provide multiple types of input selection when being used as an input pin, further, the multiplexing circuit further comprises a second control pin and a source current or leakage current generating circuit, and the driving circuit further comprises a second driving branch, wherein the second control pin is used for connecting with a second output port of the processor; the second control pin is connected with an enabling port of the source current or leakage current generating circuit through a second driving branch of the driving circuit, and an output port of the source current or leakage current generating circuit is connected with the general pin.
In order to realize the power output function of the universal pin, further, the power output circuit is an HSD power output circuit.
In order to enable the universal pin to be used as an analog voltage input pin, further, the resistance voltage division network comprises a first capacitor, a first resistor and a second resistor, and an input port of the resistance voltage division network is sequentially connected with the first resistor and the first capacitor in series and then grounded; one end of the second resistor is connected with the input port of the resistor voltage-dividing network, and the other end of the second resistor is grounded; and the series point of the first capacitor and the first resistor is used as an output port of the resistor voltage division network.
In order to control whether the power output circuit is enabled or not, and further control whether the general pin is used as an output pin or an input pin, the first driving branch of the driving circuit further comprises: the first triode is a PNP type triode, the base of the first triode is connected with the first control pin, the emitting electrode of the first triode is connected with the driving power supply, and the collector electrode of the first triode is connected with the enabling port of the power output circuit.
In order to control whether the pull-up current or leakage current generating circuit is enabled or not and further control the input type when the general-purpose pin is used as the input pin, the second driving branch of the driving circuit further comprises: the second triode is an NPN type triode, the MOS tube is a P communication MOS tube, the second control pin is connected with the base electrode of the second triode, the emitting electrode of the second triode is grounded, the collecting electrode of the second triode is connected with the grid electrode of the MOS tube, the drain electrode of the MOS tube is connected with the input power supply of the multiplexing circuit, and the source electrode of the MOS tube is connected with the enabling port of the source current or leakage current generating circuit.
In order to implement a source current or leakage current generating function, the source current or leakage current generating circuit further includes: the circuit comprises a third triode, a fourth triode, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a first diode and a second diode, wherein the third triode is a PNP type triode, and the fourth triode is an NPN type triode; an enabling port of the source current or leakage current generating circuit is connected with an emitting electrode of a third triode, a collector electrode of the third triode is connected with a collector electrode of a fourth triode after being connected with an eighth resistor and a ninth resistor in series, and the emitting electrode of the fourth triode is grounded; one end of the tenth resistor is connected to the series point of the eighth resistor and the ninth resistor, and the other end of the tenth resistor is used as an output port of the source current or leakage current generating circuit; the enabling port of the source current or leakage current generating circuit is further connected with the base electrode of a third triode through an eleventh resistor, the base electrode of the third triode is connected with the anode of a first diode, the cathode of the first diode is connected with the anode of a second diode, the cathode of the second diode is connected with the base electrode of a fourth triode, and the base electrode of the fourth triode is grounded through a twelfth resistor.
In order to realize that the general pin of the multiplexing circuit can only be used as the input pin or only can be used as the output pin at the same time, the multiplexing circuit further comprises a third diode, the second control pin is connected with the anode of the third diode, and the cathode of the third diode is connected with the base of the first triode.
Drawings
Fig. 1 is a circuit schematic diagram of a general pin multiplexing circuit of embodiment 1 of the present invention;
fig. 2 is a circuit schematic diagram of a general pin multiplexing circuit according to embodiment 2 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Example 1:
as shown in fig. 1, the universal pin multiplexing circuit (hereinafter referred to as a multiplexing circuit) of this embodiment includes a power output circuit (i.e., part a in fig. 1), a resistor voltage divider network (i.e., part B in fig. 1), a driving circuit (i.e., part D in fig. 1), a first control pin MCU _ GPIO1, a detection input pin MCU _ AD, and a universal pin Interface _ IO, where the first control pin MCU _ GPIO1 is used to connect to a first output port of a processor, and the detection input pin MCU _ AD is used to connect to an input port of the processor. In this embodiment, a microcontroller (MCU for short) is used as the processor, and as other embodiments, an AP application processor, an ARM processor, a DSP microprocessor, a CPLD complex programmable logic device, and the like may also be used as the processor.
In this embodiment, the power output circuit is an HSD power output circuit, and the HSD power output circuit includes an HSD chip (i.e., a high side driver chip), where two power ports of the HSD chip (i.e., the port 4 and the port 8 of the HSD chip in fig. 1) are power ports of the HSD power output circuit; the four power output ports of the HSD chip (i.e., ports 1, 2, 6, and 7 of the HSD chip in fig. 1) are power output ports of the HSD power output circuit; the enable port of the HSD chip (i.e. port 3 of the HSD chip in fig. 1) is an enable port HSD _ CTR of the HSD power output circuit. As other embodiments, the type of the power output circuit may also be changed according to actual needs, for example, to an LSD power output circuit including an LSD chip (i.e., a low-side driver chip).
In this embodiment, the resistance voltage-dividing network includes a first capacitor C1, a first resistor R1, and a second resistor R2, and an input port of the resistance voltage-dividing network is sequentially connected in series with the first resistor R1 and the first capacitor C1 and then grounded to GND; one end of the second resistor R2 is connected with an input port of the resistor voltage division network, and the other end of the second resistor R2 is grounded GND; the series point of the first capacitor C1 and the first resistor R1 is used as an output port of the resistor voltage division network. As another embodiment, the resistor voltage divider network may have another circuit structure, for example, a resistor voltage divider network obtained by connecting the second resistor R2 in parallel with the first capacitor C1.
In this embodiment, the driving circuit includes a first driving branch, the first driving branch is composed of a first triode Q1, a third resistor R3 and a fourth resistor R4, wherein the first triode Q1 is a PNP-type triode, the input end of the first driving branch is connected with the base of the first triode Q1 through the fourth resistor R4, the emitter of the first triode Q1 is connected with the driving power VCC, and the collector of the first triode Q1 is connected with the output end of the first driving branch through the third resistor R3. The resistance value and the number of the resistors in the first driving branch circuit can be adjusted according to actual needs.
The circuit connection relationship of the multiplexing circuit of this embodiment is shown in fig. 1, a first control pin MCU _ GPIO1 of the multiplexing circuit is connected to an input end of a first driving branch, an output end of the first driving branch is connected to an enable port HSD _ CTR of an HSD power output circuit, a power port of the HSD power output circuit is connected to a +24V power supply (i.e., an input power supply of the multiplexing circuit), and a power output port of the HSD power output circuit is connected to a general pin Interface _ IO of the multiplexing circuit; the detection input pin MCU _ AD of the multiplexing circuit is connected with the input port of the resistance voltage division network, and the output port of the resistance voltage division network is connected with the universal pin Interface _ IO of the multiplexing circuit.
The multiplexing circuit of the present embodiment has two operating modes, which are explained in detail below:
working condition 1: when the first control pin MCU _ GPIO1 of the multiplexing circuit is at a high level, the first triode Q1 is cut off, the HSD power output circuit is invalid (namely not enabled), and the resistance voltage division network is single and effective.
Working condition 2: when the first control pin MCU _ GPIO1 of the multiplexing circuit is at a low level, the first triode Q1 is turned on, and the enable port HSD _ CTR of the HSD power output circuit is at a high level, then under this condition, the HSD power output circuit is effective (even if it is possible), the multiplexing circuit can implement a power output function with the help of the HSD power output circuit, and at this time, the general pin Interface _ IO of the multiplexing circuit is used as a power output pin.
In summary, the general pin of the multiplexing circuit of this embodiment can be used as both the output pin and the input pin, and the general pin integrates the input and output functions, so that the utilization rate of the general pin is effectively improved.
Example 2:
as shown in fig. 2, the general pin multiplexing circuit (hereinafter referred to as a multiplexing circuit) of this embodiment is added with a second control pin MCU _ GPIO2 and a source current or leakage current generating circuit (i.e., part C in fig. 2) on the basis of the multiplexing circuit of embodiment 1, and at the same time, a second driving branch is added to the driving circuit of the multiplexing circuit. And the second control pin MCU _ GPIO2 is used for connecting a second output port of the processor.
In this embodiment, the second driving branch is composed of a second triode Q2, an MOS transistor M1, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and a voltage regulator tube Z1, where the second triode Q2 is an NPN-type triode, the MOS transistor M1 is a P-type communication MOS transistor, an input end of the second driving branch is connected to a base of the second triode Q2 through the fifth resistor R5, an emitter of the second triode Q2 is grounded GND, one end of the sixth resistor R6 is connected to the base of the second triode Q2, and the other end of the sixth resistor R6 is grounded GND, a collector of the second triode Q2 is connected to a gate of the MOS transistor M1 through the seventh resistor R7, a drain of the MOS transistor M1 is connected to a +24V power supply (i.e., an input power supply of the multiplexing circuit), a source of the MOS transistor M1 is connected to an output end of the second driving branch, an anode of the voltage regulator tube Z1 is connected to the gate of the voltage regulator tube M1, and a cathode of the voltage regulator tube Z1 is connected to a drain of the MOS transistor M1. The resistance value and the number of the resistors in the second driving branch circuit and the voltage stabilizing value and the number of the voltage stabilizing tubes can be adjusted according to actual needs.
In this embodiment, the source current or drain current generating circuit includes: the circuit comprises a third triode Q3, a fourth triode Q4, an eighth resistor R8 (10 omega), a ninth resistor R9 (10 omega), a tenth resistor R10 (1.5K omega), an eleventh resistor R11 (4.7K omega), a twelfth resistor R12 (4.7K omega), a first diode D1 and a second diode D2, wherein the third triode Q3 is a PNP type triode, and the fourth triode Q4 is an NPN type triode; an enabling port of the source current or leakage current generating circuit is connected with an emitting electrode of a third triode Q3, a collector electrode of the third triode Q3 is connected with a collector electrode of a fourth triode Q4 after being connected with an eighth resistor R8 and a ninth resistor R9 in series, and an emitting electrode of the fourth triode Q4 is grounded GND; one end of the tenth resistor R10 is connected to the series point of the eighth resistor R8 and the ninth resistor R9, and the other end is used as an output port of the source current or leakage current generating circuit; the enabling port of the source current or leakage current generating circuit is further connected with the base of a third triode Q3 through an eleventh resistor R11, the base of the third triode Q3 is connected with the anode of a first diode D1, the cathode of the first diode D1 is connected with the anode of a second diode D2, the cathode of the second diode D2 is connected with the base of a fourth triode Q4, and the base of the fourth triode Q4 is grounded GND through a twelfth resistor R12. The source current or leakage current generating circuit of this embodiment can provide 8mA source current or 8mA leakage current, and as another embodiment, the resistance value and the number of resistors in the source current or leakage current generating circuit may be adjusted according to actual needs to adjust the magnitude of the source current or leakage current output by the source current or leakage current generating circuit.
The circuit connection relationship of the multiplexing circuit of this embodiment is shown in fig. 2, a first control pin MCU _ GPIO1 of the multiplexing circuit is connected to an input end of a first driving branch, an output end of the first driving branch is connected to an enable port HSD _ CTR of the HSD power output circuit, a power port of the HSD power output circuit is connected to a +24V power supply (i.e., an input power supply of the multiplexing circuit), and a power output port of the HSD power output circuit is connected to a general pin Interface _ IO of the multiplexing circuit; the detection input pin MCU _ AD of the multiplexing circuit is connected with the input port of the resistance voltage division network, and the output port of the resistance voltage division network is connected with the universal pin Interface _ IO of the multiplexing circuit; a second control pin MCU _ GPIO2 of the multiplexing circuit is connected with the input end of a second driving branch circuit, the output end of the second driving branch circuit is connected with an enabling port of a source current or leakage current generating circuit, and the output port of the source current or leakage current generating circuit is connected with a general pin Interface _ IO of the multiplexing circuit; the multiplexing circuit of this embodiment further includes a third diode D3, a second control pin MCU _ GPIO2 of the multiplexing circuit is connected to an anode of the third diode D3, and a cathode of the third diode D3 is connected to a base of the first transistor Q1.
The multiplexing circuit of the present embodiment has three operating modes, which are described in detail below:
working condition 1: when the second control pin MCU _ GPIO2 of the multiplexing circuit is at a high level, the base electrode of the first triode Q1 is at the high level due to the conduction of the third diode D3, at this time, no matter what the state of the first control pin MCU _ GPIO1 of the multiplexing circuit is, the first triode Q1 is cut off, and the HSD power output circuit is invalid; meanwhile, as the second triode Q2 is conducted and the MOS tube M1 is conducted, the enabling port of the source current or leakage current generating circuit is in a high level, the third triode Q3 and the fourth triode Q4 are conducted, and the source current or leakage current generating circuit is effective; under the working condition, the source current or leakage current generating circuit is matched with the resistance voltage division network by providing the source current or leakage current, so that the multiplexing circuit can realize the switching value low level input detection function or the switching value high level input detection function, and at the moment, the universal pin Interface _ IO of the multiplexing circuit is used as the switching value input pin.
In summary, the third diode D3 prevents the general pin Interface _ IO of the multiplexing circuit from being used as both the input pin and the output pin when the second control pin MCU _ GPIO2 is at a high level and the first control pin MCU _ GPIO1 is at a low level, that is, the third diode D3 ensures that the general pin Interface _ IO of the multiplexing circuit can only be used as the input pin or only as the output pin at the same time.
Working condition 2: when the second control pin MCU _ GPIO2 of the multiplexing circuit is in a low level and the first control pin MCU _ GPIO1 of the multiplexing circuit is in a high level, the second triode Q2 is cut off, the MOS tube M1 is not conducted, and the source current or leakage current generating circuit is ineffective; meanwhile, the first triode Q1 is cut off, and the HSD power output circuit is invalid; under the working condition, the resistance voltage division network is single and effective, the multiplexing circuit can realize the input function of the analog voltage quantity by the resistance voltage division network, and at the moment, the universal pin Interface _ IO of the multiplexing circuit is used as the input pin of the analog voltage quantity.
Working condition 3: when the first control pin MCU _ GPIO1 and the second control pin MCU _ GPIO2 of the multiplexing circuit are both at a low level, the first triode Q1 is conducted, the enable port HSD _ CTR of the HSD power output circuit is at a high level, and the HSD power output circuit is effective; meanwhile, the second triode Q2 is cut off, the MOS tube M1 is not conducted, and the source current or leakage current generating circuit is ineffective; under the working condition, the multiplexing circuit can realize the power output function by virtue of the HSD power output circuit, and at the moment, a universal pin Interface _ IO of the multiplexing circuit is used as a power output pin.
In summary, the universal pin of the multiplexing circuit of the present embodiment can be used as both the output pin and the input pin, and the universal pin integrates the input and output functions, so that the utilization rate of the universal pin is effectively improved; in addition, when the universal pin of the multiplexing circuit of the embodiment is used as an input pin, two types of input selections can be provided, and the utilization rate of the universal pin is further improved.
Claims (7)
1. A universal pin multiplexing circuit, characterized by: the multiplexing circuit comprises a driving circuit, a power output circuit, a resistance voltage division network, a first control pin, a detection input pin and a general pin, wherein the first control pin is used for connecting a first output port of a processor, and the detection input pin is used for connecting an input port of the processor; the first control pin is connected with an enabling port of the power output circuit through a first driving branch of the driving circuit, and a power output port of the power output circuit is connected with the general pin; the detection input pin is connected with an input port of the resistance voltage division network, and an output port of the resistance voltage division network is connected with the general pin; the multiplexing circuit further comprises a second control pin and a source current or leakage current generating circuit, the driving circuit further comprises a second driving branch, and the second control pin is used for being connected with a second output port of the processor; the second control pin is connected with an enabling port of the source current or leakage current generating circuit through a second driving branch of the driving circuit, and an output port of the source current or leakage current generating circuit is connected with the universal pin.
2. The universal pin multiplexing circuit according to claim 1, wherein: the power output circuit is an HSD power output circuit.
3. The universal pin multiplexing circuit according to claim 1, wherein: the input port of the resistance voltage division network is sequentially connected with the first resistor and the first capacitor in series and then grounded; one end of the second resistor is connected with the input port of the resistor voltage division network, and the other end of the second resistor is grounded; and the series point of the first capacitor and the first resistor is used as an output port of the resistor voltage division network.
4. The universal pin multiplexing circuit according to claim 1, wherein: the first drive branch of the drive circuit comprises: the first triode is a PNP type triode, the base of the first triode is connected with the first control pin, the emitting electrode of the first triode is connected with the driving power supply, and the collector electrode of the first triode is connected with the enabling port of the power output circuit.
5. The universal pin multiplexing circuit according to claim 1, wherein: the second drive branch of the drive circuit comprises: the second triode is an NPN type triode, the MOS tube is a P communication MOS tube, the second control pin is connected with the base electrode of the second triode, the emitting electrode of the second triode is grounded, the collecting electrode of the second triode is connected with the grid electrode of the MOS tube, the drain electrode of the MOS tube is connected with the input power supply of the multiplexing circuit, and the source electrode of the MOS tube is connected with the enabling port of the source current or leakage current generating circuit.
6. The universal pin multiplexing circuit according to claim 1, wherein: the source current or leakage current generating circuit includes: the circuit comprises a third triode, a fourth triode, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a first diode and a second diode, wherein the third triode is a PNP type triode, and the fourth triode is an NPN type triode; an enabling port of the source current or leakage current generating circuit is connected with an emitting electrode of a third triode, a collector electrode of the third triode is connected with a collector electrode of a fourth triode after being connected with an eighth resistor and a ninth resistor in series, and the emitting electrode of the fourth triode is grounded; one end of the tenth resistor is connected to the series point of the eighth resistor and the ninth resistor, and the other end of the tenth resistor is used as an output port of the source current or leakage current generating circuit; the enabling port of the source current or leakage current generating circuit is further connected with the base electrode of a third triode through an eleventh resistor, the base electrode of the third triode is connected with the anode of a first diode, the cathode of the first diode is connected with the anode of a second diode, the cathode of the second diode is connected with the base electrode of a fourth triode, and the base electrode of the fourth triode is grounded through a twelfth resistor.
7. The universal pin multiplexing circuit according to claim 1, wherein: the multiplexing circuit further comprises a third diode, the second control pin is connected with the anode of the third diode, and the cathode of the third diode is connected with the base electrode of the first triode.
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| CN114175506B (en) * | 2020-07-10 | 2023-05-16 | 深圳欣锐科技股份有限公司 | Pulse width modulation port multiplexing circuit and device based on digital signal processing |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004247389A (en) * | 2003-02-12 | 2004-09-02 | Renesas Technology Corp | Semiconductor integrated circuit |
| CN101452433A (en) * | 2007-11-30 | 2009-06-10 | 中兴通讯股份有限公司 | Diplex interface recognition device and method |
| CN101807176A (en) * | 2010-02-04 | 2010-08-18 | 杭州矽力杰半导体技术有限公司 | Chip pin multiplexing circuit and multiplexing method thereof |
| CN202135109U (en) * | 2011-06-10 | 2012-02-01 | 深圳市博亚时代科技有限公司 | Voltage input and cell output multiplexing circuit of connector |
| CN104639147A (en) * | 2015-02-06 | 2015-05-20 | 深圳桑菲消费通信有限公司 | Interface multiplexing circuit and device |
| CN104993815A (en) * | 2015-07-22 | 2015-10-21 | 欧科佳（上海）汽车电子设备有限公司 | General pin multiplex circuit |
| CN108566191A (en) * | 2018-04-03 | 2018-09-21 | 擎先电子科技（苏州）有限公司 | A kind of general pin multiplexing circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6509758B2 (en) * | 2001-04-18 | 2003-01-21 | Cygnal Integrated Products, Inc. | IC with digital and analog circuits and mixed signal I/O pins |
| US8957700B2 (en) * | 2012-09-28 | 2015-02-17 | Analog Devices, Inc. | Apparatus and methods for digital configuration of integrated circuits |
-
2019
- 2019-06-28 CN CN201910578489.3A patent/CN110380720B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004247389A (en) * | 2003-02-12 | 2004-09-02 | Renesas Technology Corp | Semiconductor integrated circuit |
| CN101452433A (en) * | 2007-11-30 | 2009-06-10 | 中兴通讯股份有限公司 | Diplex interface recognition device and method |
| CN101807176A (en) * | 2010-02-04 | 2010-08-18 | 杭州矽力杰半导体技术有限公司 | Chip pin multiplexing circuit and multiplexing method thereof |
| CN202135109U (en) * | 2011-06-10 | 2012-02-01 | 深圳市博亚时代科技有限公司 | Voltage input and cell output multiplexing circuit of connector |
| CN104639147A (en) * | 2015-02-06 | 2015-05-20 | 深圳桑菲消费通信有限公司 | Interface multiplexing circuit and device |
| CN104993815A (en) * | 2015-07-22 | 2015-10-21 | 欧科佳（上海）汽车电子设备有限公司 | General pin multiplex circuit |
| CN108566191A (en) * | 2018-04-03 | 2018-09-21 | 擎先电子科技（苏州）有限公司 | A kind of general pin multiplexing circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110380720A (en) | 2019-10-25 |
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Address after: 450001 building 15, No.16, Jinzhan street, high tech Industrial Development Zone, Zhengzhou City, Henan Province Applicant after: Zhengzhou senpeng Electronic Technology Co.,Ltd. Address before: 450001 F3, unit 3, building 9, No. 338, Lianhua street, high tech Development Zone, Zhengzhou City, Henan Province Applicant before: ZHENGZHOU SENPENG ELECTRONIC TECHNOLOGY Co.,Ltd. |
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Denomination of invention: A Universal Pin Multiplexing Circuit Effective date of registration: 20230911 Granted publication date: 20221220 Pledgee: Bank of Zhengzhou Co.,Ltd. Zhongyuan Science and Technology City Sub branch Pledgor: Zhengzhou senpeng Electronic Technology Co.,Ltd. Registration number: Y2023980055919 |