CN110380697B

CN110380697B - Chopper preamplifier and integrated circuit

Info

Publication number: CN110380697B
Application number: CN201910691213.6A
Authority: CN
Inventors: 苗书立; 许建超; 夏书香
Original assignee: SHENZHEN RENERGY TECHNOLOGY CO LTD
Current assignee: SHENZHEN RENERGY TECHNOLOGY CO LTD
Priority date: 2019-07-29
Filing date: 2019-07-29
Publication date: 2024-07-16
Anticipated expiration: 2039-07-29
Also published as: CN110380697A

Abstract

A chopper preamplifier and an integrated circuit comprise a pair of chopper switches, and an input buffer stage, a gain amplification stage and an output filter stage which are sequentially connected, wherein one chopper switch is arranged before the input buffer stage, the other chopper switch is arranged after the input buffer stage, and a chopper operational amplifier is adopted in the gain amplification circuit, so that chops are scattered, the chops only process small differential signals, and large differential signals are prevented from being exchanged back and forth, so that large state changes are avoided. This greatly simplifies the recovery difficulty and recovery time after the signal is disturbed, with very little loss of signal integrity.

Description

Chopper preamplifier and integrated circuit

Technical Field

The application belongs to the technical field of CMOS integrated devices, and particularly relates to a chopper preamplifier and an integrated circuit.

Background

The simple description of the chopping technique is: a differential circuit is placed between a pair of chopper switches using the pair of chopper switches. The pair of chopper switches enables the constant switching back and forth of the differential signals in phase and in antiphase. Functionally, the input side switch performs a modulation function (modulator) for the input signal, and the output side switch performs a demodulation function (de-modulator) for the output signal. The final effect is: for the signal spectrum, there is no effect (two spectral shifts occur back and forth, but eventually return to the origin), but for the noise of the differential circuit between the two chopper switches, only one spectral shift occurs, and the low frequency 1/f noise and offset is shifted to the high frequency, and finally filtered by the subsequent low pass filter, since only one demodulation process is performed. Although the chopping technology can eliminate the mismatch and 1/f noise, because of introducing a chopping clock, the periodic inversion and disturbance to a precise analog circuit exist, so that the introduction of non-ideal factors such as clock feedthrough, charge injection, disturbance of a signal, resumption and the like is unavoidable. These problems, if not handled well, can severely deteriorate linearity and gain accuracy.

The pre-amplifier structure with chopper function commonly used at present comprises: the chopper switch is generally arranged at two ends of the gain amplifying stage, or the input side switch is arranged at the front end of the input buffer stage, and the output side switch is arranged at the rear end of the gain amplifying stage. The chopper switch of the output side switch has a large signal, the chopper process causes a large state change, the signal integrity problem is caused, and the linearity and the gain precision are affected. In addition, the performance of the whole pre-amplifier is also affected due to the problems of input impedance, process requirements, gain accuracy and linearity of the structure of the current input buffer stage

Disclosure of Invention

The application aims to provide a chopping preamplifier and an integrated circuit, and aims to solve the problems that the existing common chopping preamplifier has a large signal at a chopping switch of an output side switch, and the signal integrity, linearity and gain precision are affected due to the large state change of the signal caused by the chopping process.

A first aspect of an embodiment of the present application provides a chopper preamplifier, comprising:

The first chopper switch is used for modulating the two input signals and then outputting the two input signals;

the input buffer circuit is connected with two output ends of the first chopping switch, adopts a source follower structure and provides impedance isolation for the input signal and then outputs the signal;

The two input ends of the second chopper switch are respectively connected with the two output ends of the input buffer circuit, and the second chopper switch is used for mediating and outputting an output signal of the input buffer circuit;

The gain amplifying circuit is connected with two input ends of the second chopping switch, adopts a chopping operational amplifier capable of eliminating offset and noise, and is used for amplifying the regulated output signal gain, eliminating offset and noise and outputting an amplified signal;

And the two input ends of the output filter circuit are connected with the output end of the gain amplifying circuit, and the output filter circuit is used for outputting the amplified signal after filtering.

In one embodiment, the input buffer circuit comprises two input buffer units, each input buffer unit comprises a first current source, a first main source follower and a first auxiliary source follower, wherein the first current source is connected in parallel or in reverse series between a power supply and a common potential, the first main source follower is formed by a first transistor, the first auxiliary source follower is formed by at least one second transistor, the gates of the first transistor and the second transistor are commonly connected as an input end of the input buffer circuit, a common joint between the first current source and the first main source follower is used as an output end of the input buffer circuit, and the first auxiliary source follower is used for eliminating channel length modulation effect of the first main source follower.

In one embodiment, the input buffer unit further includes a level shift module for increasing output level shift, wherein:

The level shift module is connected between the first current source and the first main source follower, and a common point between the level shift module and the first current source is used as an output of the input buffer unit.

In one embodiment, the level shifting module is connected between the first primary source follower and the first secondary source follower.

In one embodiment, the first transistor and the second transistor are PMOS transistors, and a source of the first transistor is connected to a power supply through the first current source, and at least one of the second transistors is connected in parallel and then connected between a drain of the first transistor and a common potential; or (b)

The first transistor and the second transistor are NMOS transistors, the source electrode of the first transistor is connected with a common potential through the first current source, and at least one second transistor is connected between the drain electrode of the first transistor and a power supply after being connected in series in the same direction.

In one embodiment, the first transistor and the second transistor each operate in a saturation region; the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor.

In one embodiment, the threshold voltage relationship that the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor is: the |Vt1| -Vt0| is not less than |Vod0|+margin;

Wherein Vth1 is a threshold voltage of the first transistor, vth0 is a threshold voltage of the second transistor, vod0 is an overdrive voltage of the second transistor, and margin is a voltage margin.

In one embodiment, the gain amplifying circuit includes a first chopper operational amplifier, a second chopper operational amplifier, a first voltage dividing element, a second voltage dividing element, and a third voltage dividing element, wherein a positive phase input end of the first chopper operational amplifier is used as a first input end of the gain amplifying circuit, one end of the first voltage dividing element is connected with an output end of the first chopper operational amplifier, the other end of the first voltage dividing element is connected with an inverting input end of the first chopper operational amplifier and one end of the second voltage dividing element, the other end of the second voltage dividing element is connected with an inverting input end of the second chopper operational amplifier and one end of the third voltage dividing element, a positive phase input end of the second chopper operational amplifier is used as a second input end of the gain amplifying circuit, the other end of the third voltage dividing element is connected with an output end of the second chopper operational amplifier, an output end of the first chopper operational amplifier is used as a first output end of the gain amplifying circuit, and an output end of the second chopper operational amplifier is used as a second output end of the gain amplifying circuit.

In one embodiment, the output filter circuit includes a first resistor, a second resistor, and a filter capacitor, wherein one end of the first resistor and one end of the second resistor are respectively used as two input ends of the output filter circuit, the filter capacitor is connected in series between the other end of the first resistor and the other end of the second resistor, and the other end of the first resistor and the other end of the second resistor are respectively used as two output ends of the output filter circuit.

A second aspect of an embodiment of the application provides an integrated circuit comprising a chopper preamplifier as described above.

The input buffer stage in the chopper preamplifier adopts a source follower structure, so that the linearity performance and the gain precision performance can be greatly improved, and the bottleneck that the input buffer stage becomes the performance is avoided; the chopper is respectively acted on the first-stage input buffer and the operational amplifier of the second-stage gain amplification stage, so that the chopper is dispersed, only small differential signals are processed by the chopper, and large differential signals are prevented from being exchanged back and forth, so that large state changes are avoided, the recovery difficulty and recovery time of the disturbed signals are greatly simplified, and the loss of the integrity of the signals is very small.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a chopper preamplifier according to an embodiment of the application;

FIG. 2 is a schematic diagram of a typical chopper switch and schematic circuit diagram;

FIGS. 3A and 3B are schematic diagrams of two input buffer circuits in the chopper preamplifier of FIG. 1, respectively;

FIG. 4 is a schematic diagram of an exemplary circuit of a first embodiment of the input buffer circuit shown in FIG. 3A;

FIG. 5 is a schematic diagram of an exemplary circuit of a second embodiment of the input buffer circuit shown in FIG. 3A;

FIG. 6 is a schematic diagram of an exemplary circuit of a third embodiment of the input buffer circuit shown in FIG. 3B;

FIG. 7 is a schematic diagram of an exemplary circuit of a fourth embodiment of the input buffer circuit shown in FIG. 3B;

FIG. 8 is a schematic diagram of an exemplary circuit of a fifth embodiment of the input buffer circuit shown in FIG. 3A;

FIG. 9 is a schematic diagram of an exemplary circuit of a sixth embodiment of the input buffer circuit shown in FIG. 3A;

FIG. 10 is a schematic circuit diagram of a conventional source follower structure input buffer circuit composed of a single PMOS tube and an input/output signal waveform diagram thereof;

FIG. 11 is a schematic circuit diagram of the input buffer circuit shown in FIG. 4 and an input/output signal waveform thereof;

FIG. 12 is an exemplary schematic circuit diagram of a first chopper preamplifier provided by an embodiment of the application;

FIG. 13 is an exemplary schematic circuit diagram of a second chopper preamplifier according to an embodiment of the application;

fig. 14 is an exemplary circuit schematic of a typical chopper operational amplifier.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

Referring to fig. 1, a chopper preamplifier according to an embodiment of the application can be used in an integrated circuit. Comprises a first chopper switch 01, an input buffer circuit 02, a second chopper switch 03, a gain amplifying circuit 04 and an output filter circuit 05.

Two input ends of the first chopper switch 01 are used as two input ends vin and vip of a chopper preamplifier to be respectively connected with two input signals, and the first chopper switch 01 is used for modulating the two input signals and then outputting the modulated signals; two input ends of the input buffer circuit 02 are connected with two output ends of the first chopper switch 01, the input buffer circuit 02 adopts a source follower structure, and impedance isolation is provided for input signals and then output; two input ends of the second chopper switch 03 are respectively connected with two output ends vbf _n and vbf_p of the input buffer circuit 02, and the second chopper switch 03 is used for modulating and outputting an output signal of the input buffer circuit 02; the two input ends of the gain amplifying circuit 04 are connected with the two output ends of the second chopping switch 03, and the gain amplifying circuit 04 adopts a chopping operational amplifier capable of eliminating offset and noise and is used for gain amplifying the regulated output signal and outputting an amplified signal after eliminating offset and noise; the two input ends of the output filter circuit 05 are connected with the output ends vop_f and von_f of the gain amplifying circuit 04, and the output filter circuit 05 is used for filtering the amplified signal and outputting the filtered signal.

The chopping scheme of the chopping preamplifier is as follows: chopping separately for the input buffer stage; and putting chopping waves into the operational amplifier aiming at the gain amplification stage, and chopping the operational amplifier only. This localizes and minimizes the chopping. The whole chopping schemes are distributed through the traditional arrangement at the front end of the input buffer stage and the rear end of the gain amplification stage, and the chopping is enabled to only process small differential signals through a plurality of local chopping schemes, so that large differential signals are prevented from being exchanged back and forth, large state changes are avoided, recovery difficulty and recovery time after the signals are disturbed are greatly simplified, and loss of integrity of the signals is very small.

Fig. 2 is a typical circuit diagram of a chopper switch, the first chopper switch 01 and the second chopper switch 03 are identical, and each has 4 ports, which are sequentially denoted as a pair of an input terminal in+ and an output terminal out+, and the other pair of an input terminal in-and an output terminal out-, and the two pairs of ports are completely symmetrical without any distinction.

The input buffer circuit 02 comprises two input buffer units 10, each input buffer unit 10 comprises a first current source Iss connected in series (see fig. 3A) or in series (see fig. 3B) in opposite directions between a power supply Vcc and a common potential Vss, a first main source follower 100 formed by a first transistor, and a first auxiliary source follower 200 formed by at least one second transistor, gates of the first transistor and the second transistor are commonly connected as an input terminal of the input buffer circuit 02, a common junction between the first current source Iss and the first main source follower 100 is used as an input terminal of the input buffer circuit 02, and the first auxiliary source follower 200 is used for eliminating a channel length modulation effect of the first main source follower 100.

The scheme is an improvement on the basis of the input buffer unit 10 formed by single MOS transistors, the first main source follower 100 is also a single transistor, and the first auxiliary source follower 200 is a single transistor or a plurality of transistors connected in series. And the first current source Iss, the first main source follower 100 and the first auxiliary source follower 200 are sequentially connected in series between the power supply Vcc and the common potential Vss (e.g., ground) in forward or reverse direction, depending on whether the transistor is P-type or N-type. The input buffer unit 10 uses different transistors to form two source followers, one of which is a main source follower and the other of which is an auxiliary source follower, and the auxiliary source follower functions to eliminate the channel length modulation effect of the main source follower, thereby greatly improving the linearity and gain accuracy of the preamplifier.

Regarding the embodiment of the input buffer unit 10, since two input buffer units 10 are required to be identical, one of the input buffer units 10 is taken as an example without losing generality:

embodiment one:

Referring to fig. 4, the first transistor and the second transistor in the input buffer unit 10 are PMOS transistors, and then the first current source Iss, the first main source follower 100 and the first auxiliary source follower 200 are sequentially connected in series between the power supply Vcc and the common potential Vss, the source of the first transistor is connected to the power supply Vcc through the first current source Iss, and at least one second transistor is connected in parallel between the drain of the first transistor and the common potential Vss. Specifically, the first transistor is a PMOS tube PM1, the second transistor is a PMOS tube PM0, the substrate of the PMOS tube PM0 is connected with the source electrode of the PMOS tube PM0, and the drain electrode of the PMOS tube PM0 is grounded; the substrate of the PMOS tube PM1 is connected with the source electrode thereof, and the drain electrode of the PMOS tube PM1 is connected with the source electrode of the PMOS tube PM 0. The first current source Iss provides a bias current, which is placed between the power supply Vcc and the source of the PMOS tube PM1, and the bias current is directed from the power supply Vcc to the PMOS tube PM1. The input signal vin is applied to the input gates of the PMOS transistor PM0 and the PMOS transistor PM1 at the same time, and the output signal vbf _n is taken from the source of the PMOS transistor PM1.

Embodiment two:

referring to fig. 5, the input buffer unit 10 of the present embodiment extends to a series structure of a plurality of PMOS source followers based on the first embodiment, wherein the first transistor PMOS transistor PM1 forms a "main" source follower, the remaining second transistors PMOS transistors pm_a0 to pm_an form the first auxiliary source follower 200 together, the gates of the PMOS transistors PM1 and pm_a0 to pm_an are commonly connected as the input of the preamplifier, and the output signal vbf _n is taken from the source of the PMOS transistor PM1 as the output of the preamplifier.

Embodiment III:

Referring to fig. 6, the first transistor and the second transistor of the input buffer unit 10 are NMOS transistors, and then the first auxiliary source follower 200, the first main source follower 100 and the first current source Iss are sequentially connected in series between the power source Vcc and the common potential Vss, the source of the first transistor is connected to the common potential Vss through the first current source Iss, and at least one second transistor is connected in parallel between the drain of the first transistor and the power source Vcc. Specifically, the first transistor is an NMOS transistor NM1, the second transistor is an NMOS transistor NM0, the substrate of the NMOS transistor NM0 is connected to the source thereof, and the drain of the NMOS transistor NM0 is connected to the power supply Vcc; the substrate of the NMOS tube NM1 is connected with the source electrode thereof, and the drain electrode of the NMOS tube NM1 is connected with the source electrode of the NMOS tube NM 0. The first current source Iss supplies a bias current which is placed between the common potential Vss and the source of the NMOS transistor NM1 in a direction from the power supply Vcc to the NMOS transistor NM1 to the common potential Vss. The input signal vin is applied to the input gates of both the NMOS transistor NM0 and the NMOS transistor NM1, and the output signal vbf _n is taken from the source of the NMOS transistor NM 1. In this embodiment, a serial structure composed of 2 NMOS source followers is adopted, and is completely dual with the 2 PMOS structures of the first embodiment. The common mode level of the input signal vin may be high at this time, for example, by taking the supply voltage directly.

Embodiment four:

Referring to fig. 7, the input buffer unit 10 of the present embodiment is a serial structure of multiple NMOS source followers based on the third embodiment, wherein the first transistor NMOS transistor NM1 forms a "main" source follower, the remaining second transistors NMOS transistors nm_a0 to nm_an together form the first auxiliary source follower 200, the gates of the NMOS transistors NM1 and nm_a0 to nm_an are commonly connected as the input of the preamplifier, and the output signal vbf _n is taken from the source of the NMOS transistor NM1 as the output of the preamplifier. The series structure of the plurality of NMOS source followers of the present embodiment is fully dual with the series structure of the plurality of PMOS source followers of the second embodiment.

Fifth embodiment:

Referring to fig. 8, the input buffer unit 10 of the present embodiment is extended to a structure in which a dc level shifting module 300 is added on the basis of any one of the first to fourth embodiments. In this embodiment, the level shift module 300 is connected between the first current source Iss and the first main source follower 100, and a common junction between the level shift module 300 and the first current source Iss is used as an output of the preamplifier, and the level shift module 300 is used to increase the output level shift. The main source follower 200 and the first auxiliary source follower 200 are not limited to PMOS transistors or NMOS transistors, and the number of MOS transistors of the first auxiliary source follower 200 is not limited.

In the example shown in fig. 8, the dc level shift module 300 is a resistor R0, and is connected in series between the output and the PMOS tube PM1 of the first main source follower, so that the problem that the output level shift is insufficient due to the single PMOS tube PM1 can be solved, and at this time, the dc level shift can be further increased by adding the level shift module 300, and meanwhile, the signal quality is not affected. Sometimes, in order for the gain amplification circuit 04 of the second stage to operate at a comfortable bias voltage vbias, this level shifting block 300 is necessary. In other embodiments, the resistor R0 may be replaced by a circuit module, and it is within the scope of the present disclosure, regardless of the specific implementation of the circuit module, as long as its function is to increase the dc level shift, while not affecting the signal quality.

Example six:

Referring to fig. 9, the input buffer unit 10 of the present embodiment is extended to a structure in which a dc level shifting module 400 is added on the basis of any one of the first to fourth embodiments. In this embodiment, the level shift module 400 is connected between the first primary source follower 100 and the first secondary source follower 200, and the level shift module 400 is used to increase the output level shift. The main source follower 200 and the first auxiliary source follower 200 are not limited to PMOS transistors or NMOS transistors, and the number of MOS transistors of the first auxiliary source follower 200 is not limited. In addition, the scheme in this embodiment may be used in combination with the scheme of embodiment five.

In the example shown in fig. 9, the dc level shift module 400 is a resistor R1 connected in series between the PMOS tube PM1 of the first main source follower 100 and the PMOS tube PM0 of the first auxiliary source follower 200. The problem that the output level shift is insufficient due to the fact that the PMOS tube PM1 tube is singly used can be solved, the direct current level shift can be further increased by the level shift module 400, and meanwhile the signal quality is not affected. In other embodiments, the resistor may be replaced by a circuit module, and the circuit module belongs to the protection scope of the scheme as long as the function of the circuit module is to increase the dc level shift without affecting the signal quality.

It should be noted that, as described above, although fig. 8 and 9 are described by taking a 2-stage MOS source follower series structure as an example, the present invention is applicable to a multi-stage MOS source follower series structure, and it is within the scope of protection to insert a level shift module into these structures.

With continued reference to fig. 4, the related principles will be described below by taking the first transistor and the second transistor in the input buffer unit 10 as PMOS transistors, and the first auxiliary source follower 200 as a PMOS transistor. Specifically, the core of the preamplifier employs 2 PMOS transistors PM0 and PM1 and a first current source Iss. Therefore, from the structural point of view, the two PMOS transistors PM0 and PM1 both constitute a source follower, but their inputs are connected in parallel and their outputs are "in series". The PMOS tube PM1 forms a main source follower, and the PMOS tube PM0 forms an auxiliary source follower; the presence of the PMOS transistor PM0 performs linearization processing on the PMOS transistor PM1, so that the linearity of the PMOS transistor PM1 is greatly improved, and the output signal vbuffer is generated by the PMOS transistor PM 1. The linearity is greatly improved due to the ingenious connection relation, the gain accuracy is greatly improved, and performances (such as output impedance, noise, power consumption and voltage margin consumption) of the device in other aspects are equivalent to those of a common single PMOS tube source follower. This is a very rare phenomenon in the field of analog circuit design, which is filled with various tradeoffs (tradeoff), often at the expense of other aspects of performance when one circuit architecture is better than another.

In the structure of fig. 4, the PMOS transistors PM0 and PM1 need to be carefully designed and selected to ensure that all 2 MOS devices operate in the saturation region, which is a basic requirement for the structure to function as desired. Let PMOS pipe PM0 work very light in saturation region, the difficult point lies in letting PMOS pipe PM1 work in saturation region, it must satisfy:

Vds1, vgs1, vth1 and margin are drain-source voltage, gate-source voltage, threshold voltage and voltage margin of the PMOS tube PM1 respectively, and margin is generally about 100 to 200 mv. Assuming that the common mode level of the input signal vin is 0, the above equation is further written as:

the method further comprises the following steps:

Due to Vt is the voltage of the common junction of the drain of the PMOS tube PM1 and the source of the PMOS tube PM0, vgs0, vth0, vod0 is the gate-source voltage, threshold voltage, overdrive voltage of the PMOS tube PM0,. Thus, the above formula is further written as:

This means that the threshold voltage of the PMOS transistor PM1 must be greater than the threshold voltage of the PMOS transistor PM0 by vod0+margin, i.e., at least 100 mV. To achieve this goal, there are at least 2 possible solutions:

First kind: the process typically provides multiple threshold MOS transistor options. PM1 can be selected as a high threshold MOS tube, PM0 is selected as a low threshold MOS tube, and the aim can be easily achieved.

Second kind: through fine and smart sizing. Let W/L (W is the width of the conduction channel and L is the length of the conduction channel) of the PMOS tube PM0 be large enough to operate in the subthreshold region, where Vod0 is very small (e.g., 50 mV). Let L of the PMOS PM0 be the minimum length under the current process (e.g., l=0.35 um for a 0.35um CMOS process), and the L minimum typically has a smaller threshold voltage. In addition, the W/L of the PMOS tube PM1 is as small as possible, and the L is as large as possible in the current process (for example, L=4um is adopted for a 0.35um CMOS process), so that the Vod1 of the PMOS tube PM1 is large enough, the self channel length modulation effect is small enough, and the linearity is as good as possible. The larger L of the PMOS tube PM1 generally brings about a larger threshold voltage. In this way, by lettingAs large as possible, letAs small as possible, letAs small as possible for the above formula is satisfied, so the effect that this scheme structure brought has been played, further makes the linearity better.

Further analysis follows why the proposed structure can greatly improve linearity and gain accuracy, and this problem needs to be examined by comparative analysis.

Fig. 10 shows an input buffer unit 10 of a source follower structure formed by a conventional single PMOS transistor, and the substrate is connected to the source. The gain of its input to output is:

wherein gm is the transconductance of the PMOS tube PM1, and gds is the output intrinsic admittance of the PMOS tube PM 1. The intrinsic gain, called MOS transistor, is usually around 100, that isGm is typically negligible compared to gm, and therefore Av is approximately equal to 1. The effect of gds cannot be neglected if used in high precision and high linearity applications. The gds effect characterizes the channel length modulation effect, in this configuration, gds completely determines the accuracy and linearity of the gain. Note the definition of gds:

Thus gds is a function of vds (drain-source voltage of MOS transistor). For the source follower of fig. 8, due to The gain Av is actually still a weak function of the input signal due to the influence of gds:

This is non-linearity and harmonic distortion is generated. The design and simulation results on a typical CMOS process show that the components of the 2 nd harmonic and the 3 rd harmonic of the input buffer unit 10 of the source follower structure formed by the conventional single PMOS transistor are very difficult to be lower than < -80dBc, which means that the effective bit number (precision index, defined as enob= (SNDR-1.76)/6.02) of the measurement system based on the input buffer unit 10 of the single PMOS transistor is at most about 13bits, which is far from sufficient for high-precision application.

From the analysis of FIG. 10, we know that the bottleneck is the gds. Our proposed patent approach is just to almost completely eliminate the effect of gds.

As shown in fig. 11, the input signal vin passes through 2 source followers, producing vbf _n and vt, respectively. We call PMOS pipe PM1 the first main source follower 100, and PMOS pipe PM0 the first auxiliary source follower 200.vbf _n and vt are almost exactly equal to the input signal vin, the magnitude of the error being the harmonic component (around-80 dBc, i.e. around one ten thousandth of the signal itself).

In addition, note the PMOS tube PM1, which

Mathematical notations are used herein, with a small o representing "much less" e.g., o (vin) representing an amount much less than vin. Therefore, the source and drain of the PMOS PM1 swing synchronously with the input signal, but with respect to their difference, are almost 0 (the ripple is around ten thousandth of the input signal), so that no change in vds is felt. Since no change in vds is felt, gds for the PM1 tube of the PMOS tube is nearly equal to 0. Thus, for the circuit configuration of the present application:

The nonlinear component is greatly reduced, thus greatly reducing harmonic distortion. The design and simulation results on the same CMOS process show that the components of the input buffer unit 10, the 2 nd harmonic and the 3 rd harmonic of the new source follower structure provided by the application can reach < -120dBc, which means that the effective bit number of the measurement system of the input buffer unit 10 based on the source follower can reach the level close to 20bits at the highest, and the system is sufficient for high-precision application occasions (usually about 16bits are more common).

On the other hand, the gain accuracy is an indicator to be considered, which is also critical for high-accuracy measurement systems. In practice, each stage (buffer isolation, amplification, filtering, analog-to-digital conversion …) in the signal processing link introduces gain, and the gain of each stage is affected by PVT (process bias, power supply ripple, temperature), which tends to be very complex and even difficult to accurately characterize. In the influence of PVT:

typically the effect of supply ripple V can be addressed by design, e.g. placing V under LDO (Low Dropout Regulator, low dropout linear regulator) to keep V constant.

The influence of the process deviation P is usually solved by a calibration link before the chip/whole machine leaves the factory. The calibration is to record the gain value Av0 before leaving the factory of the chip/whole machine and store it in the nonvolatile memory of the chip, and is called calibration. In normal use, the actual gain Av is calibrated with Av 0. In this way, sheet-to-sheet process variations are eliminated;

the effect of temperature T is to make the gain of the circuit insensitive to temperature by an excellent design level and a smart circuit structure.

For the source follower structure input buffer unit 10 composed of the conventional single PMOS transistor shown in fig. 8, the gain is:

And Are all amounts that vary drastically with temperature, ranging from-40 c to +85 c,The variation is often up to more than 2 times. As before, the typical value for gds/gm is approximately 1%, and the typical value for Av is approximately 0.99; however, if the temperature variation of gds/gm is taken into consideration, the temperature variation of Av is as high as 1% or more, which brings about a large measurement error, so that the high-precision measurement system becomes no longer accurate. Due toNot only with T, but also with P, which means that for each chip,The temperature profiles of (a) may all be different so that the idea of taking into account temperature compensation becomes impractical (temperature compensation for each is required, which is extremely expensive).

However, for the patent proposal proposed by the application, the gain is as follows:

Assuming that the value of x itself is about 1%, the variation over the full temperature range is also about 1%. As before, o (x) is a quantity about 40dB smaller (about 100 times) than x, so that the value of o (x) itself is about 0.01%, and the variation in the whole temperature range is about 0.01% in magnitude, which is converted into a temperature coefficient of about 8ppm/°c, which is the top level from the literature currently available, and satisfies most of the applications of high-precision measurement systems.

The application connects the source follower composed of 2 MOS tubes in parallel, and the output ends are connected in series. One of the MOS transistors serves as a first main source follower 100, and the other one or more MOS transistors serve as a first auxiliary source follower 200, and the output is taken from the first main source follower 100. The first subsidiary source follower 200 functions to eliminate the channel length modulation effect of the first main source follower 100, thereby greatly improving the linearity and gain accuracy of the input buffer unit 10.

In order to make the MOS transistors of the main source follower 200 and the first auxiliary source follower 200 all work in the saturation region, the design method is adopted: firstly, a design method of a multi-threshold tube is adopted; and secondly, a more skillful tube size selection method is adopted. Both of these methods are described in detail above.

The input buffer unit 10 and the integrated circuit of the application have excellent linearity and extremely accurate gain; the input signal does not need to provide an additional bias voltage vbias (the sensor can directly take ground as a common mode signal); the circuit is extremely simple, is completely compatible with the CMOS process, and does not need special devices; impedance isolation (high impedance input and low impedance output); other aspects of performance (such as noise, power consumption and voltage margin consumption) are equivalent to that of a common single MOS tube source follower structure. This is a very rare phenomenon in the field of circuit design. In the field of circuit design, various tradeoffs (tradeoff) are filled, and one circuit architecture performs better than another in one aspect, often at the expense of other aspects.

Referring to fig. 12 and 13, in one embodiment, the gain amplifying circuit 04 includes a first chopper operational amplifier A0, a second chopper operational amplifier a0_, a first voltage dividing element R21, a second voltage dividing element R22 and a third voltage dividing element R23, wherein a non-inverting input terminal of the first chopper operational amplifier A0 is used as a first input terminal of the gain amplifying circuit 04, one end of the first voltage dividing element R21 is connected to an output terminal of the first chopper operational amplifier A0, the other end of the first voltage dividing element R21 is connected to an inverting input terminal of the first chopper operational amplifier A0, one end of the second voltage dividing element R22, the other end of the second voltage dividing element R22 is connected to an inverting input terminal of the second chopper operational amplifier a0_, one end of the third voltage dividing element R23 is used as a second input terminal of the gain amplifying circuit 04, the other end of the third voltage dividing element R23 is connected to an output terminal of the second chopper operational amplifier a0_, and the output terminal of the first chopper operational amplifier a 04 is used as an output terminal of the gain amplifying circuit von_.

Referring to fig. 12 and 13, in one embodiment, the output filter circuit 05 includes a first resistor Rf, a second resistor rf_and a filter capacitor, one end of the first resistor Rf and one end of the second resistor rf_are respectively used as two input ends of the output filter circuit 05, the filter capacitor Cf is connected in series between the other end of the first resistor Rf and the other end of the second resistor rf_and the other end of the first resistor Rf and the other end of the second resistor rf_are respectively used as two output ends of the output filter circuit 05, namely as two output vop_f and von_f of the chopper preamplifier.

In this embodiment, the front-chopper differential amplifier is a differential structure formed on the basis of the related embodiment of fig. 4, and the differential circuit has symmetry and naturally has suppression capability for even harmonics, so that the front-chopper differential amplifier has wider application, and most of the amplifier circuits in practical application are in differential (or pseudo-differential) form.

It should be noted that, although the two input buffer units 10 of the chopper pre-differential amplifier are illustrated by taking a 2-stage PMOS series structure as an example, in practice, for all structures including but not limited to the first to sixth embodiments, a differential circuit may be formed, which falls within the protection scope of the present application. The voltage dividing element may be a passive circuit including at least one of a resistor, a capacitor, an inductor, and a transistor.

Functionally, the first chopper switch 01 performs a modulation function for the input signals vip, vin, while the second chopper switch 03 performs a demodulation function for the output signals vbf _p, vbf_n of the input buffer circuit 02. The final effect is that there is no effect on the signal (from vip, vin→ vbf _p, vbf_n), but the noise of the differential input buffer circuit 02 between the first chopper switch 01 and the second chopper switch 03 undergoes only one demodulation process, so that the spectrum shift occurs, the low frequency 1/f noise is shifted to the high frequency, and finally filtered by the filter of the subsequent stage.

The gain amplifying circuit 04 is composed of two operational amplifiers (A0 and a0_) and 3 voltage dividing elements (R21, R22 and R23), wherein A0 and a0_ are identical operational amplifiers, and the gain amplifying circuit 04 is also an exactly symmetrical differential structure. The op-amps A0 and a0_are internally self-contained with chopping functionality, and a typical chopping implementation of a differential input single ended output op-amp is shown in fig. 14. The output filter circuit 05 is mainly for filtering out high frequency noise of the circuit, and its cut-off frequency is far higher than the signal frequency, so it is all-pass (gain is 1 in the signal band) for the signal.

One improvement of the present application is related to the input buffer stage and another improvement is related to the improvement of the chopping scheme.

The input buffer stage adopts a very special structure, and is a source follower structure with high input impedance, enhanced linearity and accurate gain. While other aspects of performance (e.g., output impedance, noise, power consumption, consumption of voltage margin) are comparable to a common single MOS transistor source follower.

The gain of the whole chopper preamplifier is as follows:

By varying the ratio of R21, R22 and R23, the desired gain can be achieved.

The second-stage gain stage adopts the form of operational amplifier closed-loop feedback, so that the linearity and gain precision of the gain stage can be very good as long as the open-loop gain of the operational amplifier is high enough.

The input buffer circuit structure adopted by the application greatly improves the linearity and the gain precision. The design and simulation results on a typical CMOS process show that the components of 2 nd harmonic and 3 rd harmonic of a source follower structure input buffer formed by a traditional single MOS tube are difficult to be minus 80dBc, and the gain changes with temperature by +/-1%, which is far from sufficient for high-precision application. By adopting the input buffer structure, the components of the 2 nd harmonic and the 3 rd harmonic can be < -120dBc, the gain variation along with the temperature is as low as +/-0.01%, and the input buffer structure is enough for most high-precision systems. Most importantly, this is achieved on a pure CMOS process without any special devices and without the support of an expensive BiCMOS process.

For the input buffer stage, chops are placed at its input and output. Since the gain of the input buffer stage is 1 and the signal is not amplified, the first chopper switch 01 and the second chopper switch 03 both process small differential signals, the disturbance and recovery time caused by the small differential signals are very small, and the loss of the integrity of the signals is very small.

For the gain amplifier stage, the chopper is placed inside the op-amp. Chopping is located on the differential path of the input and current signals of the op-amp. It is well known that when an op-amp operates in a closed loop state, the differential signal processed by the op-amp is a very small error signal, so that the chopper switch operating within the op-amp causes very little disturbance and loss of signal integrity.

For the gain amplifying stage, the chopper is arranged in the 2 operational amplifiers, which is equivalent to chopping the operational amplifiers only and not chopping the voltage dividing element. If there is a mismatch or 1/f noise in the voltage dividing element, it will be presented directly at the output. If the voltage dividing element is a passive device, 1/f noise is not generated; through reasonable design, the matching precision can be extremely high.

The actual design test result shows that the 1/f noise inflection point frequency of the whole chopper preamplifier can be as low as <1Hz and the offset is less than 10uV by adopting the proposal provided by the application. If high-level system-level chopping is re-matched, the offset can be further reduced to <1uV. The signal integrity loss caused by chopping is greatly reduced, and the components of the 2 nd harmonic and the 3 rd harmonic of the whole chopper preamplifier can be < -120dBc by matching with the use of a high-linearity input buffer, so that the gain is reduced to +/-0.01% along with the change of temperature, and the chopper preamplifier has high-precision property.

The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the application.

Claims

1. A chopper preamplifier, comprising:

The two input ends of the second chopper switch are respectively connected with the two output ends of the input buffer circuit, the second chopper switch is used for mediating output signals of the input buffer circuit and then outputting the mediated output signals, and the first chopper switch is identical with the second chopper switch;

2. The chopper pre-amplifier of claim 1, wherein the input buffer circuit comprises two input buffer units, each of the input buffer units comprises a first current source connected in parallel or in anti-series between a power supply and a common potential, a first main source follower formed by a first transistor, and a first auxiliary source follower formed by at least one second transistor, gates of the first transistor and the second transistor are commonly connected as an input terminal of the input buffer circuit, a common junction between the first current source and the first main source follower is used as an output terminal of the input buffer circuit, and the first auxiliary source follower is used for eliminating channel length modulation effect of the first main source follower.

3. The chopper preamplifier of claim 2, wherein the input buffer unit further comprises a level shift module for increasing output level shift, wherein:

4. The chopper preamplifier of claim 3, wherein the level shifting module is connected between the first primary source follower and the first secondary source follower.

5. The chopper preamplifier according to claim 2, wherein the first transistor and the second transistor are PMOS transistors, a source of the first transistor is connected to a power supply through the first current source, and at least one of the second transistors is connected between a drain of the first transistor and a common potential after being connected in series in the same direction; or (b)

6. A chopper preamplifier according to any of claims 2 to 5, wherein the first transistor and the second transistor both operate in a saturation region; the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor.

7. The chopper preamplifier of claim 6, wherein the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor by the relationship: the |Vt1| -Vt0| is not less than |Vod0|+margin;

8. The chopper preamplifier according to claim 1, wherein the gain amplification circuit includes a first chopper operational amplifier, a second chopper operational amplifier, a first voltage dividing element, a second voltage dividing element, and a third voltage dividing element, a positive phase input terminal of the first chopper operational amplifier is used as a first input terminal of the gain amplification circuit, one end of the first voltage dividing element is connected to an output terminal of the first chopper operational amplifier, the other end of the first voltage dividing element is connected to an inverting input terminal of the first chopper operational amplifier, one end of the second voltage dividing element is connected to an inverting input terminal of the second chopper operational amplifier, one end of the third voltage dividing element is connected to a positive phase input terminal of the second chopper operational amplifier as a second input terminal of the gain amplification circuit, the other end of the third voltage dividing element is connected to an output terminal of the second chopper operational amplifier, and an output terminal of the first chopper operational amplifier is used as an output terminal of the second gain amplification circuit.

9. The chopper preamplifier according to claim 1, wherein the output filter circuit includes a first resistor, a second resistor, and a filter capacitor, one end of the first resistor and one end of the second resistor are respectively used as two input ends of the output filter circuit, the filter capacitor is connected in series between the other end of the first resistor and the other end of the second resistor, and the other end of the first resistor and the other end of the second resistor are respectively used as two output ends of the output filter circuit.

10. An integrated circuit comprising a chopper preamplifier according to any of claims 1 to 9.