CN110379847A - Improve the structure of super-junction device breakdown voltage - Google Patents
Improve the structure of super-junction device breakdown voltage Download PDFInfo
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- CN110379847A CN110379847A CN201910772833.2A CN201910772833A CN110379847A CN 110379847 A CN110379847 A CN 110379847A CN 201910772833 A CN201910772833 A CN 201910772833A CN 110379847 A CN110379847 A CN 110379847A
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- breakdown voltage
- groove
- junction device
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- 230000015556 catabolic process Effects 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000000407 epitaxy Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 5
- 230000005684 electric field Effects 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- 230000001737 promoting effect Effects 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
Abstract
The invention discloses a kind of structures for improving super-junction device breakdown voltage, by increasing a gate trench between the groove of super-junction device, super junction by drawing partially respective selection optimal match point condition again, do not increase conducting resistance, is not required to the upper breakdown voltage for promoting super-junction device on the basis of newly-increased mask plate and technique.
Description
Technical field
The present invention relates to semiconductor device design and manufacturing field, in particular to a kind of super junction deep groove fill methods.
Background technique
Super junction power device be one kind quickly grow, widely used novel power semiconductor.It is in double expansions
On the basis of dispersed metallic oxide semiconductor (DMOS), by introducing super junction (Super Junction) structure, in addition to having
DMOS input impedance is high, switching speed is fast, working frequency is high, thermostabilization is good, driving circuit is simple, outside the features such as being easily integrated,
Also overcome the shortcomings that conducting resistance of DMOS increases with breakdown voltage at 2.5 power relationships.Super junction DMOS is wide at present
It is general to be applied to towards PC, laptop, net book, mobile phone, illumination (high-voltage gas discharging light) product and TV
The power supply or adapter of the consumption electronic products such as machine (liquid crystal or plasma TV) and game machine.
Super-junction device uses new structure of voltage-sustaining layer, i.e., thin using a series of alternately arranged p-type and N-type semiconductor
Layer in the off state, at the lower voltage just exhausts the p-type, the N-type region that are made of p-type and N-type semiconductor thin layer, realization
Charge mutually compensates, to make p-type, N-type region be able to achieve high breakdown voltage under high-dopant concentration, to obtain low lead simultaneously
Be powered resistance and high-breakdown-voltage, breaks conventional power devices theoretical limit.Therefore, super-junction device is a kind of utilization PN charge
The internal Resurf technology of balance keeps lesser conducting resistance again while promoting device reverse breakdown voltage BV
MOSFET structure.
Super-junction device replaces the drift region N in traditional VDMOS using the structure of N/P alternating assortment, it is combined in the industry
Well known VDMOS technique, so that it may which production obtains the MOSFET of super-junction structures, it can be in breakdown reverse voltage and traditional
In the case where VDMOS-cause, by using the epitaxial layer of low-resistivity, the conducting resistance of device is greatly reduced.P in the thin layer
The characteristic that the Carrier Profile of type impurity and the Carrier Profile of N-type impurity and their matching will affect device includes that it is anti-
To breakdown voltage and current handling capability.All using in general device design keeps alternate P/N thin layer i.e. p-type thin layer and N-type thin
Reach optimal charge balance in layer to obtain the maximum breakdown reverse voltage of device.The preparation of super junction power device at present
Technique is largely divided into two major classes: one is epitaxy technique, being formed in N-type epitaxial substrate in the way of multiple extension and injection
P column；Another is formed in the mode of deep plough groove etched plus P column filling, be etched in N-type epitaxy layer it is a plurality of
Then parallel groove is filled p-type epitaxy material in parallel groove and is formed, forms the structure for being alternately repeated P, N, P, N of arrangement.
As shown in Figure 1, being a kind of schematic diagram of traditional super-junction device, right side is the part in figure at the dashed circle in left side in figure
Method figure, the gate trench for including in figure, silica layer in groove, the oxide layer is attached on trench wall and bottom, more
Crystal silicon fills full groove, and oxide layer keeps apart the silicon substrate of polysilicon and groove in groove or extension as dielectric layer
Come, substrate surface also has heavily doped N-type layer and the silicon oxide layer on heavily doped N-type layer.Traditional is groove-shaped super
Junction device is because groove cannot accomplish 90 degree completely therefore breakdown voltage is difficult to maximize, highly dependent upon the pattern of groove.
Summary of the invention
Technical problem to be solved by the present invention lies in providing in a kind of super-junction device technique, improves super-junction device and hit
Wear the structure of voltage.
To solve the above problems, the structure of the present invention for improving super-junction device breakdown voltage, super-junction device exist
There is super-junction structure in semiconductor substrate, the super-junction structure is made of multiple alternately arranged N-type columns and p-type column, p-type column by
The P-type material composition being filled in superjunction groove, superjunction groove are formed in N-type substrate, and N-type column is by between the p-type column
The N-type substrate composition.
There are double grooves in N-type extension or substrate, double trench walls all have oxide layer, filling in groove
Full polysilicon；Be N-type substrate between double grooves, and wherein a groove is located in p-well, extension between double grooves or
Also there is substrate surface a heavily doped N-type layer to be covered in the section substrate surface between double grooves, the heavily doped N-type layer it is upper
Side is also covered with oxide layer, and the oxide layer is connected with the oxide layer in the groove positioned in epitaxial layer.
Further, the semiconductor substrate is silicon substrate.
Further, the silicon substrate or be silicon epitaxy.
Further, the superjunction groove and double grooves are formed by etching.
Further, the p-type column is filled by p-type extension forms.
Further, double grooves at work, draw partially respective selection optimal match point condition again, improve breakdown
Voltage.
Further, 0 potential depth is continued lower pushing and presses p-type region area, so that top by double groove structures
Electric field region deformation, improves breakdown voltage.
The structure of the present invention for improving super-junction device breakdown voltage, is drawn partially each free again by double groove structures
Optimal match point condition is selected, breakdown voltage is improved.
Detailed description of the invention
Fig. 1 is traditional super junction device structure schematic diagram.
Fig. 2 is the structural schematic diagram of super-junction device of the present invention.
Fig. 3 is the breakdown voltage simulation curve figure of the present invention with traditional devices.
Description of symbols
1 is extension, and 2 be polysilicon, and 3 be silica, and 4 be p-well, and 5 be heavily doped N-type layer.
Specific embodiment
The structure of the present invention for improving super-junction device breakdown voltage, super-junction device have in the semiconductor substrate
Super-junction structure, the super-junction structure are made of multiple alternately arranged N-type columns and p-type column, and p-type column is by being filled in superjunction groove
P-type material composition, superjunction groove is formed in N-type substrate, and N-type column is made of the N-type substrate between the p-type column.
For example, on the bulk silicon substrate of N-type or in silicon epitaxy, multiple parallel grooves are formed by dry etching,
What is be spaced between multiple parallel grooves is exactly the silicon substrate either silicon epitaxy of N-type, between the transverse width and groove of groove
Interval it is roughly the same.Then by fill process, the epitaxial layer thin layer of full p-type is filled in this multiple parallel groove, this
Sample, the silicon substrate layer or epitaxial layer of the N-type between p-type epitaxial layer and groove in groove are formed the interval P, N, P, N row
The form of column, spaced N-type and p-type form super-junction structures.The p-type of composition, N-type region can assisted depletion, realize
Charge mutually compensates, so that p-type, N-type region be made to be able to achieve high breakdown voltage under high-dopant concentration, utilizes PN charge balance
Internal Resurf technology keeps lesser conducting resistance again while promoting device reverse breakdown voltage BV.
Region other than the super-junction structure in N-type extension or substrate has double grooves, as shown in Fig. 2, described is double
Trench wall all has oxide layer, and full polysilicon is filled in groove；It is N-type semiconductor silicon substrate between double grooves, or
Person is silicon epitaxy layer, and wherein a groove is located in p-well, and the extension or substrate surface between double grooves also have a heavy doping
N-type layer is covered in the section substrate surface between double grooves, is also covered with oxide layer above the heavily doped N-type layer, described
Oxide layer is connected with the oxide layer in the groove positioned in epitaxial layer.
The structure of above-mentioned super-junction device is inserted into a gate trench group groove in pairs, as shown in Figure 2, left and right
Respectively there is a gate trench, double grooves at work, draw partially respective selection optimal match point condition again, improve breakdown
Voltage.
Above-mentioned double grooves are formed by etching, and compared with traditional handicraft, the present invention has increased a groove newly, in manufacture craft
It is upper identical as traditional handicraft holding, original layout design only need to be modified, is increased again in original trench etching mask version
Add the design of a groove, can be synchronous with the holding of original technique, when etching, once forms two grooves.No longer need to production volume
Outer mask plate, it is completely compatible with traditional technique without the new processing step of increase.
After having used the device architecture, super junction by drawing partially respective selection optimal match point condition again, such as Fig. 3 institute
Show, be the drain terminal voltage curve simulation comparison of existing structure and structure of the invention, traditional device architecture shows that drain terminal voltage is
Puncture after 668 volts, and the new device architecture breakdown voltage BV of the present invention is up to 731V, there is the promotion of obvious amplitude.
Design theory of the invention is to be re-introduced into a gate trench in top device, and 0 potential depth is continued to push down on
P-type region area is squeezed, i.e. the area of p-well 4 in Fig. 2 makes the electric field region deformation at top, reaches the mesh for increasing breakdown voltage BV
's.
The above is only a preferred embodiment of the present invention, is not intended to limit the present invention.Come for those skilled in the art
It says, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any modification, equivalent
Replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (8)
1. a kind of structure for improving super-junction device breakdown voltage, it is characterised in that: super-junction device has in the semiconductor substrate
There is super-junction structure, the super-junction structure is made of multiple alternately arranged N-type columns and p-type column, and p-type column is by being filled in superjunction groove
In P-type material composition, superjunction groove is formed in N-type substrate, and N-type column is by the N-type substrate group between the p-type column
At；
There are double grooves in N-type extension or substrate, double trench walls all have oxide layer, and filling is full more in groove
Crystal silicon；It is N-type substrate between double grooves, and wherein a groove is located in p-well, extension or substrate between double grooves
Also there is a heavily doped N-type layer to be covered in the section substrate surface between double grooves on surface, and the top of the heavily doped N-type layer is also
It is covered with oxide layer, the oxide layer is connected with the oxide layer in the groove positioned in epitaxial layer.
2. improving the structure of super-junction device breakdown voltage as described in claim 1, it is characterised in that: the semiconductor lining
Bottom is silicon substrate.
3. improving the structure of super-junction device breakdown voltage as claimed in claim 1 or 2, it is characterised in that: the silicon lining
Bottom is silicon epitaxy.
4. improving the structure of super-junction device breakdown voltage as described in claim 1, it is characterised in that: the superjunction groove
And double grooves are formed by etching, are formed multiple parallel grooves by dry etching in the semiconductor substrate of N-type, are then existed
P-type semiconductor material is filled in groove forms p-type column.
5. improving the structure of super-junction device breakdown voltage as claimed in claim 4, it is characterised in that: the p-type column is by p-type
Extension fills to be formed.
6. improving the structure of super-junction device breakdown voltage as described in claim 1, it is characterised in that: double grooves exist
When work, partially respective selection optimal match point condition is drawn again, improves breakdown voltage.
7. improving the structure of super-junction device breakdown voltage as claimed in claim 6, it is characterised in that: double groove knots
0 potential depth is continued lower pushing and presses p-type region area by structure, so that top electric field region deforms, improves breakdown voltage.
8. improving the structure of super-junction device breakdown voltage as described in claim 1, it is characterised in that: double grooves are carved
In etching technique, the groove etched mask plate of primitive groove only need to be modified, without making new mask plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201910772833.2A CN110379847A (en) | 2019-08-21 | 2019-08-21 | Improve the structure of super-junction device breakdown voltage |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910772833.2A CN110379847A (en) | 2019-08-21 | 2019-08-21 | Improve the structure of super-junction device breakdown voltage |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010109033A (en) * | 2008-10-29 | 2010-05-13 | Renesas Technology Corp | Semiconductor device and method of manufacturing the same |
| CN103828058A (en) * | 2011-09-27 | 2014-05-28 | 株式会社电装 | Semiconductor device provided with vertical semiconductor element |
| CN203659877U (en) * | 2013-10-30 | 2014-06-18 | 英飞凌科技奥地利有限公司 | Super junction device and semiconductor structure comprising same |
-
2019
- 2019-08-21 CN CN201910772833.2A patent/CN110379847A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010109033A (en) * | 2008-10-29 | 2010-05-13 | Renesas Technology Corp | Semiconductor device and method of manufacturing the same |
| CN103828058A (en) * | 2011-09-27 | 2014-05-28 | 株式会社电装 | Semiconductor device provided with vertical semiconductor element |
| CN203659877U (en) * | 2013-10-30 | 2014-06-18 | 英飞凌科技奥地利有限公司 | Super junction device and semiconductor structure comprising same |
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Application publication date: 20191025 |
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