CN110365244B - Frequency error modulation method for reducing THD of single-phase photovoltaic grid-connected inverter - Google Patents

Frequency error modulation method for reducing THD of single-phase photovoltaic grid-connected inverter Download PDF

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CN110365244B
CN110365244B CN201910692542.2A CN201910692542A CN110365244B CN 110365244 B CN110365244 B CN 110365244B CN 201910692542 A CN201910692542 A CN 201910692542A CN 110365244 B CN110365244 B CN 110365244B
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frequency
switching
inverter
tube
switching tube
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CN110365244A (en
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潘健
陈庆东
刘松林
吕磊
陈凤娇
张慧
梁佳成
尤润川
许章茁
马浩
成玉爽
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Hubei University of Technology
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/01—Arrangements for reducing harmonics or ripples
    • H02J3/383—
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/40—Arrangements for reducing harmonics

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Abstract

The invention provides a frequency error modulation method for reducing THD (total harmonic distortion) of a single-phase photovoltaic grid-connected inverter, wherein a topological main circuit of the single-phase photovoltaic grid-connected inverter comprises a Direct Current (DC) source and a first switching tube Q1A second switch tube Q2And a third switching tube Q3And a fourth switching tube Q4An output filter inductor L, an output filter capacitor C and a load R, U0For outputting an effective value of the AC voltage, UdFor inputting direct current voltage, its characterized in that: provided with a first switch tube Q1And a second switching tube Q2Form a front arm S1 and a third switch tube Q3And a fourth switching tube Q4The rear arm S2 is composed by controlling the front arm S1 and the rear arm S2 respectively with SPWM pulses of different carrier frequenciessFor the switching frequency, carrier frequency f, of the forearm S1 switchmIs the switching frequency of the rear arm S2, and fm＝nfsAnd limiting the value range of n to be
Figure DDA0002148318620000011
And preferably setting the value of n in the value range, so that the ratio of the low frequency to the high frequency of the switching frequencies of the two bridge arms is as close to 1 as possible.

Description

Frequency error modulation method for reducing THD of single-phase photovoltaic grid-connected inverter
Technical Field
The invention relates to the technical field of single-phase photovoltaic grid connection, in particular to a frequency error method for reducing Total Harmonic Distortion (THD) of an inverter by a single-phase inverter.
Background
The photovoltaic grid connection is one of important applications of photovoltaic power generation, however, harmonic waves generated by a photovoltaic grid connection inverter can pollute a power grid, THD generated by a photovoltaic grid connection device can be reduced, the pollution to the power grid can be effectively reduced, and the grid connection electric energy quality is improved.
The large-scale photovoltaic power supply is connected to the grid, so that a large number of power electronic converters are introduced into a power system, a large number of nonlinear loads are also added into a power supply system, the power system is seriously polluted, and the more serious power quality problem is generated. The Total Harmonic Distortion (THD) is an important index for measuring the quality of the photovoltaic grid-connected electric energy.
In recent years, a great deal of research is being conducted on reducing the value of the grid-connected photovoltaic THD. At present, three technologies are mainly used for reducing the photovoltaic grid-connected THD: 1) the topological structure of the inverter is changed, and through corresponding switch control, multiple levels are generated to reduce THD; 2) an additional decoupling circuit is adopted for providing the required pulse power to reduce THD; 3) the THD is reduced by optimizing the control strategy and controlling and changing the switching algorithm of the switch.
The first approach employs multi-level inverters (MLIs) which have higher output voltage levels than the two-level or three-level conventional inverters, which makes the output waveforms of the MLIs stepped, more sinusoidal than the conventional inverters. Thus, MLIs cause THD to decrease. A commonly used multilevel inverter, a cascaded H-bridge (CHB) inverter, lacks energy storage elements and the ability to isolate faults. Through the optimization of the topological structure, the Maximum Power Point Tracking (MPPT) capability is better, the THD is reduced, and the THD is increased due to the fact that the MPPT has a large number of semiconductor switches. Thereafter, topological optimization is performed in order to reduce the number of semiconductor switches. The topological structure improvement scheme provided later reduces the number of semiconductor switches as much as possible on the basis of keeping THD and MPPT performances. However, the problem of the large number of switches still remains.
The second method adopts an additional decoupling circuit to generate double-line-frequency power ripple (double-line-frequency) on the direct current side of the single-phase grid connection. This pulsation is detrimental to THD performance. The dc-link side of a common passive decoupling circuit needs an electrolytic capacitor with a large volume to absorb power pulsation, so that the service life is limited. While the active decoupling approach can reduce the capacitance of the power decoupling, it adds an auxiliary circuit and causes efficiency loss. Recently, an auxiliary circuit for active decoupling is added in a single-phase photovoltaic grid-connected inverter with common LC filtering, so that the efficiency and the THD performance are improved compared with a single-phase grid-connected active decoupling circuit based on the LC filtering. However, adding auxiliary circuitry still results in a loss of efficiency.
The third method is to optimize the control part of the grid-connected inverter, and generally, the optimization is performed on an algorithm for controlling the on and off of the inverter switch. Furthermore, in recent years, it has been proposed to introduce a neural network into the inverter control. When the double improvement of the structure and the control is carried out, the switch of the inverter is increased, and the exclusive control is used. Although this method can reduce THD, the cost is increased due to the addition of switches, and when the system parameters do not match, the control algorithm may fail or the performance may be reduced.
Currently, a scholars proposes to modulate two bridge arms of a full-bridge inverter by using a modulation technology and using two frequencies of low frequency and high frequency respectively. See also: the method comprises the following steps of A, tree Huai, Wangming, Dengwei, Li\32704Adouble-frequency inverter control strategy [ J ] for photovoltaic grid connection, 2011,31(01):84-88.
This method requires that one switching cycle of the low frequency switch must include a plurality of switching cycles of the high frequency switch so that within one low frequency switching cycle, there are four operating modes. Although the inverter switching frequency dual-frequency control method can make the current ripple on the inverter output inductor smaller than the current ripple of the inverter switching frequency which only uses single low-frequency control, the current ripple is still far higher than the current ripple of the inverter switching frequency which only uses high-low frequency control. The direct result is that the output performance (total harmonic distortion rate) of the method is between the full low frequency and the full high frequency used by the two legs of the inverter in terms of the output performance (total harmonic distortion rate) of the inverter. This dual frequency modulation method is not practically used because it does not improve the inverter output performance.
Disclosure of Invention
In order to solve the problem that the dual-frequency modulation of two bridge arms of an inverter is poorer in output performance (total harmonic distortion rate) than the full-high-frequency modulation of the two bridge arms of the inverter, the invention provides a novel inverter cross-frequency modulation method for limiting the ratio of low frequency to high frequency, and the ratio of the low frequency to the high frequency of the switching frequency of the two bridge arms is close to 1 as much as possible.
The technical scheme of the invention provides a frequency error modulation method for reducing THD (total harmonic distortion) of a single-phase photovoltaic grid-connected inverter, wherein a topological main circuit of the single-phase photovoltaic grid-connected inverter comprises a Direct Current (DC) source and a first switching tube Q1A second switch tube Q2And a third switching tube Q3And a fourth switching tube Q4An output filter inductor L, an output filter capacitor C and a load R, a direct current source DC provides direct current, a first switch tube Q1A second switch tube Q2And a third switching tube Q3And a fourth switching tube Q4A bridge circuit is formed, an output filter inductor L and an output filter capacitor C form an LC filter circuit for filtering the high-frequency carrier part, a load R is an output resistor, and is recorded as U0For outputting AC voltageEffective value, UdFor inputting direct current voltage, its characterized in that: provided with a first switch tube Q1And a second switching tube Q2Form a front arm S1 and a third switch tube Q3And a fourth switching tube Q4The rear arm S2 is composed by controlling the front arm S1 and the rear arm S2 respectively with SPWM pulses of different carrier frequenciessFor the switching frequency, carrier frequency f, of the forearm S1 switchmIs the switching frequency of the rear arm S2, and
fm＝nfs
and limiting the value range of n to
Figure BDA0002148318600000031
And preferably setting the value of n in the value range, so that the ratio of the low frequency to the high frequency of the switching frequencies of the two bridge arms is as close to 1 as possible.
And the value of n is preferably set in the value range, and the trial and error method is adopted to realize the method.
Moreover, two SPWM pulse generation modules are adopted to respectively provide carrier frequencies fsSPWM pulse and carrier frequency fmSPWM pulse.
The technical method for reducing the frequency error of the single-phase photovoltaic grid-connected inverter THD provided by the invention can effectively reduce the pollution of a photovoltaic grid-connected device to a power grid and improve the power quality. The frequency-staggered modulation used by the invention can ensure that the current ripple on the output inductor of the inverter is smaller than the current ripple on the output inductor of which the switching frequency of the inverter uses full high-frequency modulation. The modulation method of the invention can make the output performance of the inverter superior to the condition that two bridge arms of the inverter use full high frequency.
Drawings
Fig. 1 shows an LC-configuration inverter using a cross-frequency technique according to an embodiment of the present invention.
FIG. 2 shows Q according to an embodiment of the present invention2And Q3The switch tube triggers a pulse sequence.
Fig. 3 is a simplified diagram of an SPWM control unit with different carrier frequencies according to an embodiment of the present invention.
FIG. 4 shows current ripple on inductor, voltage on inductor, and Q in common LC filter inverter circuit in the prior art2And Q3A timing diagram.
Fig. 5 shows the current ripple in a switching cycle of a conventional LC filter inverter circuit in the prior art.
FIG. 6 shows an improved LC filter inverter circuit according to an embodiment of the present inventionm＝0.97fsCurrent ripple on the middle inductor L, voltage on the inductor, Q2And Q3A timing diagram.
Fig. 7 shows the THD value of a conventional LC filter inverter circuit in the prior art.
Fig. 8 shows the THD value of the LC filter inverter circuit according to the embodiment of the present invention.
Detailed Description
For better understanding of the technical solutions of the present invention, the following detailed description of the present invention is made with reference to the accompanying drawings and examples.
The method for reducing THD by the frequency-staggered technology provided by the embodiment of the invention is realized by aiming at the existing single-phase inverter topology main circuit. The single-phase inverter topology main circuit comprises a direct current source, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, an output filter inductor, an output filter capacitor and a load.
As shown in FIG. 1, the interleaved topology circuit includes a DC source DC, a first switch tube Q1A second switch tube Q2And a third switching tube Q3And a fourth switching tube Q4The circuit comprises an output filter inductor L, an output filter capacitor C and a load R. The four switch tubes adopt Metal Oxide Semiconductor Field Effect Transistors (MOSFET).
The direct current source DC provides direct current. First switch tube Q1A second switch tube Q2And a third switching tube Q3And a fourth switching tube Q4Forming a bridge circuit. And the output filter inductor L and the output filter capacitor C form an LC filter circuit for filtering the high-frequency carrier part. The load R is an output resistor U0For outputting an effective value of the AC voltage, UdIs an input dc voltage.
The direct current sourceA positive electrode and a first switch tube Q of the circuit1The upper end is connected, the negative pole of the direct current source is connected with the second switch tube Q2The lower ends are connected.
The specific circuit connection mode is as follows:
the first switch tube Q1The lower end of the second switch tube Q2The upper end is electrically connected.
The second switch tube Q2The lower end of the fourth switch tube Q4The lower ends are connected.
The third switch tube Q3Upper end of the first switch tube Q1The upper ends are connected, and the third switching tube Q3The lower end of the fourth switch tube Q4The upper ends are connected.
The left side of the output filter inductor L and the third switch tube Q3The lower end is connected, and the right side of the output filter inductor L is connected with the upper end of the output filter capacitor C.
The lower end of the output filter capacitor C and the first switch tube Q1The lower ends are connected.
The upper end of the output resistor is connected with the upper end of the output filter capacitor C, and the lower end of the output resistor is connected with the lower end of the output filter capacitor C.
It is to be noted that Q1And Q2、Q3And Q4Two groups of switches, two switches of the same group cannot be in a conducting state at the same time. Will Q1And Q2Set as forearm S1, Q3And Q4Set as the rear arm S2.
For the control aspect, the embodiment of the invention also provides that the high-frequency error frequency carrier frequency is fsSPWM pulse generation module and low-frequency error frequency carrier frequency of fmSPWM pulse generation module. SPWM denotes sinusoidal pulse width modulation.
The two SPWM pulse generation modules have different carrier frequencies, respectively fsAnd fmBesides, the logic relation inside the SPWM pulse generation module is completely consistent. It is worth noting that the fundamental frequency inside both modules is the power frequency (50 Hz). The carrier frequency is the switching frequency of four switching tubes, and is filtered by the LC at the later stageAfter the wave, the carrier wave of high frequency is filtered out, and the low-frequency fundamental wave is kept to flow through the load.
In the examples, f is setsSwitching frequency, f, of forearm S1 switchmThe switching frequency of the rear arm S2, and
fm＝nfs
in order to ensure that the current ripple on the output inductor of the inverter is smaller than the current ripple on the output inductor of which the switching frequency of the inverter is modulated by full high frequency. The invention proposes to limit the value of n. The value range of n is as follows:
Figure BDA0002148318600000051
within this range, it is ensured that each of the four states has a smaller current ripple than that of a conventional high frequency inverter. In practice, however, each consists of two of the four states of the cross-frequency inverter due to the up-current ripple and the down-current ripple of the cross-frequency. The current ripple on the actual output inductor of the cross-frequency inverter is the superposition of two switching states, so if the value of n is too small, the average current ripple on the inductance of the cross-frequency inverter can be caused to be larger than the switching frequency fsSo that the fault frequency inverter THD (total harmonic distortion) is between the switching frequency and the use high frequency fsAnd a low frequency fmBetween two general inverters THD. Therefore, the frequency f is higher than the switching frequency in order to make the frequency-staggered inverter THD usesThe common inverter THD is smaller, and the output characteristic of the error frequency inverter can be ensured to be more superior to that of the common high frequency inverter only by enabling the n value to be closer to 1. Generally, n is 0.9 or more. Considering that the relation between the n value and the actual output performance is in a parabola form, the invention further provides that the n value can be determined by adopting a trial and error method in the value range in order to obtain the optimal vertex value.
In specific practice, fsThe preset design parameters of the circuit, such as 10, 15, 20 or 40kHz, can be directly used. F can be determined according to the value of nm＝nfs。
The modulation method of the invention can make the output performance of the inverter superior to the condition that two bridge arms of the inverter use full high frequency. In order to facilitate understanding of the technical scheme principle of the invention, the value range derivation of n provided by the invention is specifically realized as follows:
when the switch Q2And Q3Derived from kirchhoff's voltage law KVL at the same time as switching on
Figure BDA0002148318600000052
When the switch Q1And Q4Obtained by KVL at opening
Figure BDA0002148318600000053
When the switch Q1、Q3(OR switch Q)2、Q4) Obtained from kirchhoff's voltage law KVL at switch-on
Figure BDA0002148318600000054
Wherein,
Figure BDA0002148318600000055
to output a sinusoidal voltage); u shape0Is an effective value of the output voltage; ω ω 2 pi f Fundamental frequency2 pi × 50Hz to 100 pi, ω t ω t is the phase of the output sinusoidal ac voltage, fFundamental frequencyThe fundamental frequency is 50Hz, P is the instantaneous value of the output voltage, and P is approximately regarded as a constant in a section of any switching period; u shapedIs an input direct current voltage; u shapeLIs the voltage on the inductor.
Let duty cycle of Q2 be D2(t)，Q3Duty ratio of D3(t) of (d). Due to control of Q2、Q3The switches all use SPWM modulation, with only a difference in carrier frequency. Thus Q2、Q3Are equal. Taking one segment of the minimum common period of any one switch, Q in figure 22And Q3Trigger pulseThe impulse sequence is analyzed, and the duty ratio D is approximately considered to be unchanged in the switching sequence.
D2＝D3＝D
To facilitate the calculation of Q1、Q2、Q3、Q4In the switching situation of (1), take Q2、Q3While opening as a starting point for the analysis, the following relationships can be listed
Figure BDA0002148318600000061
In the formula y1Is Q2The trigger pulse amplitude of the switch; k1Is a coefficient, K1∈ N, N is natural number, TsIs the switching period of the forearm S1, and has
Figure BDA0002148318600000062
fsSwitching frequency of the forearm; t represents a time variable.
Figure BDA0002148318600000063
Due to fm＝nfsTherefore, T iss＝nTmTherefore, it is
Figure BDA0002148318600000064
In the formula y2Is Q3The trigger pulse amplitude of the switch; k2Is a coefficient, K2∈N；TmIs the rear arm S2The switching period of (2).
By
Figure BDA0002148318600000065
To obtain
Figure BDA0002148318600000066
Wherein L is an inductance value, iLTo output the current value on the inductor; diLIs the current ripple.
The magnitude of the increase in time is as follows: at Q2、Q3Are simultaneously on (y)1＝1，y2＝1)、Q1、Q4Are simultaneously on (y)1＝0，y2＝0)、Q2、Q3Opposite conduction state (y)1＝1，y2＝0；y1＝0，y21) three cases, iLThe amplitude h increasing during the time at is as follows:
Figure BDA0002148318600000071
during a period of time in any one common switching cycle, as long as Q is available2、Q3Satisfies any one of the following conditions, namely, Q is enabled to be obtained2、Q3Are simultaneously on (y)1＝1，y2＝1)。
K1Ts≤t≤K1Ts+DT s①
Or
Figure BDA0002148318600000072
Or
Figure BDA0002148318600000073
Satisfying condition ① is:
Figure BDA0002148318600000074
then Q is2、Q3Time of simultaneous conduction Δ t1＝DTsWhere Δ t is1Is Q2、Q3Time of simultaneous conduction at condition ①.
Meet the condition that
Figure BDA0002148318600000075
Then Q is2、Q3Time of simultaneous conduction
Figure BDA0002148318600000076
Where Δ t2Is Q2、Q3Time of simultaneous conduction at condition ②.
Satisfaction (sometimes)
Figure BDA0002148318600000077
Then Q is2、Q3Time of simultaneous conduction
Figure BDA0002148318600000078
Where Δ t3Is Q2、Q3Time of simultaneous conduction at condition ③.
From above satisfy Q2、Q3Are simultaneously on (y)1＝1，y21), Δ t is maximum when condition ① is satisfied, where Δ t represents a time increment.
Figure BDA0002148318600000081
In the formula,. DELTA.tAIndicates persistence at y1＝1，y2Time in the case of 1; max Δ tAIndicates persistence at y1＝1，y2Maximum time in case 1; h isAIs shown at y1＝1，y2Current ripple on the inductor, maxh, in the case of 1ARepresents hAIs measured.
Will make a deformation
Figure BDA0002148318600000082
K2≤nK1≤nK1+nD≤K2+D
From the above formula, if and only if K1＝0，K2When equal to 0, K1＝K2Otherwise K2＜K1。K1＝0，K2The condition is satisfied when 0, and the next condition is ①
0K2＜nK1+nD＜K2+D
Figure BDA0002148318600000083
Since each segment of D values taken is approximately considered to be constant, K1∈N,K2∈N。
When n is smaller, K2The smaller, the two occurrences then Q2、Q3Are simultaneously on (y)1＝1，y21) time max Δ tA＝DTsThe shorter the time interval of (a), the shorter the interval at which the maximum current ripple occurs. To avoid this, the value of n must be maintained at a large value.
In contrast, Q1、Q4Condition of simultaneous conduction (y)1＝0，y20) case with Q2、Q3Condition of simultaneous conduction (y)1＝1，y21) similarly. In the same way, Q1、Q4Are simultaneously on (y)1＝0，y20) time max Δ tB＝(1D)Ts。
Figure BDA0002148318600000084
In the formula,. DELTA.tBIndicates persistence at y1＝0，y2Time in the case of 0; in the formula max Δ tBIndicates persistence at y1＝0，y2Maximum time in the case of 0; h isBIs shown at y1＝0，y2Current ripple on the inductor, maxh, at 0BRepresents hBIs measured.
Also satisfies that when n is smaller, Q is obtained by two occurrences1、Q4Are simultaneously on (y)1＝0，y20) time max Δ T ═ 1-D) TsThe shorter the time interval of (a). To avoid this, the value of n must be maintained at a large value.
Q1、Q3Are simultaneously on (y)1＝0，y21) time Δ tC(ii) a In the formula max Δ tCIndicates persistence at y1＝0，y2Maximum time in case 1; h isCIs shown at y1＝0，y2Current ripple on the inductor in case 1; maxhCRepresents hCIs measured.
Figure BDA0002148318600000085
If it is
Figure BDA0002148318600000091
Then
Figure BDA0002148318600000092
Figure BDA0002148318600000093
When P > 0
Figure BDA0002148318600000094
Figure BDA0002148318600000095
When P < 0
Satisfy the requirement of
Figure BDA0002148318600000096
Under the condition that
Figure BDA0002148318600000097
Figure BDA0002148318600000098
Figure BDA0002148318600000099
If it is
Figure BDA00021483186000000910
Figure BDA00021483186000000911
Then
Figure BDA00021483186000000912
Figure BDA00021483186000000913
When P > 0
Figure BDA00021483186000000914
Figure BDA00021483186000000915
When P < 0
Satisfy the requirement of
Figure BDA00021483186000000916
Under the condition that
Figure BDA0002148318600000101
Figure BDA0002148318600000102
Therefore, when P < 0 is satisfied
Figure BDA0002148318600000103
Can make
ha＝maxhA＞maxhC＞0
hb＝maxhB＜maxhC＜0
Wherein h isAIndicating a switching frequency of fsAt t of the ordinary high-frequency inverterk-1～tkPeriod of time, Q2And Q3When the power is switched on, the current ripple height of the inductive current rises; h isbIndicating a switching frequency of fsAt t of the ordinary high-frequency inverterk～tk+1Period of time, Q1And Q4The current ripple height of the inductor current rises when it is switched on.
Q2、Q4Are simultaneously on (y)1＝1，y20) time Δ tDIn the formula, max Δ tDIndicates persistence at y1＝1，y2Maximum time in the case of 0; h isDIs shown at y1＝1，y2Current ripple on the inductor in the case of 0; maxhDRepresents hDIs measured.
Figure BDA0002148318600000104
Can be pushed out in the same way
When P > 0 is satisfied
Figure BDA0002148318600000105
Can make
ha＝maxhA＞maxhD＞0
hb＝maxhB＜maxhD＜0
In summary, in order to ensure the frequency-staggered modulation used in the present invention, the current ripple on the output inductor of the inverter can be smaller than the current ripple on the output inductor using full high-frequency modulation for the switching frequency of the inverter.
When P is less than 0
Figure BDA0002148318600000106
When P > 0 is satisfied
Figure BDA0002148318600000107
Therefore, the value range of n is:
Figure BDA0002148318600000111
the maximum current ripple and the switching frequency on the cross-frequency LC filter inductor can be made to be fsThe current ripples on the output inductors of the common high-frequency inverter are equal.
FIG. 2 shows an embodiment of the invention Q2And Q3The switch tube triggers a pulse sequence. Any period of one minimum common switching cycle is taken during this time,
Figure BDA0002148318600000112
to output a sinusoidal voltage) is approximately constant at a constant P over a period of any switching cycle.
Fig. 3 is a simplified diagram of a control circuit according to an embodiment of the present invention. The control circuit in the embodiment comprises two SPWM pulse trigger circuits, the fundamental wave is power frequency (50Hz), and the carrier frequencies are respectively fmAnd fs。
Figure BDA0002148318600000113
A controls Q separately1And Q2The on-off of the switch is carried out,
Figure BDA0002148318600000114
b controls Q separately4And Q3And (5) switching on and off of the switch.
Figure BDA0002148318600000115
A、
Figure BDA0002148318600000116
B are respectively connected with the grids of the four switching tubes, and when a trigger signal is generated, the corresponding switching tube is switched on.
FIG. 4 shows a switching frequency fsThe common high-frequency inverter circuit comprises current ripple on the inductor, voltage on the inductor and Q2And Q3A timing diagram. The main circuit of the common LC filter inverter circuit is consistent with the main circuit of the cross-frequency LC filter inverter circuit, except that the carrier frequencies of the front arm and the rear arm of the common LC filter inverter circuit are high frequencies fs。
FIG. 5 shows the front and rear arms both at high frequency fsThe current ripple in one switching cycle of the conventional inverter. At any switching frequency of high frequency fsOne switching period t of the ordinary inverterk-1～tk+1。
Wherein t isk-1～tkRepresents Q2And Q3In the on period, the inductive current rises, and the rising current ripple is ha；tk～tk+1Represents Q1And Q4Turning on, the inductor current is reduced, and the reduced current ripple is hb(ii) a Setting switch Q2D, which is approximately considered to be a constant value in any one switching period.
From the characteristic formula of the inductance
Figure BDA0002148318600000117
To obtain
Figure BDA0002148318600000118
Wherein,
Figure BDA0002148318600000119
to output a sinusoidal voltage); u shape0Is an effective value of the output voltage; u shapeLTo output the voltage across the filter inductor; ω 2 pi f Fundamental frequency2 pi 50Hz 100 pi, ω t is the phase of the output sinusoidal ac voltage, fFundamental frequencyRepresenting a fundamental frequency of 50 Hz.
When t isk-1≤t＜tkCurrent ripple h of the current rise in the inductoraIs composed of
Figure BDA0002148318600000121
Wherein, TsIs the switching period of a common high-frequency inverter and has
Figure BDA0002148318600000122
fsThe switching frequency of a common high-frequency inverter.
When t isk-1≤t＜tkCurrent ripple h of current drop on inductorbIs composed of
Figure BDA0002148318600000123
FIG. 6 shows an improved LC filter inverter circuit f according to the present inventionm＝0.97fsPartial current ripple on the middle inductor L, voltage on the inductor and Q2And Q3A timing diagram.
In the error frequency inverter of the invention, within a section of the minimum common period, the output filter inductance current ripple height can be divided into Q2And Q3Inductive current ripple h when simultaneously onA、Q1And Q4Inductive current ripple h when simultaneously onB、Q1And Q3Inductive current ripple h when simultaneously onC、Q2And Q4Inductive current ripple h when simultaneously onDThese four types of regions. And h of each type of area is different due to different deltat, so that the ripple height of each type of area is different. In appendix 1 deduces max hA、max hB、max hCAnd max hDRespectively, they are represented in hA、hB、hC、hDThe maximum value of these four types of area current ripples (peak-to-peak value of inductor current ripple).
Figure BDA0002148318600000124
It can be seen from the foregoing derivation that when n satisfies the above relationship, it can ensure that the current ripple on the inductor in any one of the four switching states of the present invention is larger than that in fsThe normal high frequency inverter current ripple at the switching frequency is small. In order to facilitate understanding of the technical scheme of the invention, the case that n is 0.97 is taken in the embodiment to verify the effectiveness and superiority of the invention. Using high frequencies f for the switching frequency as shown in fig. 7 and 8, respectivelysThe common LC filter circuit and the embodiment of the invention improve the THD value of the LC filter inverter circuit. When L is 0.65mH C is 15 muF, the THD value of the common LC filter circuit is 3.09%, while the THD value of the improved LC filter inverter circuit of the embodiment of the invention is reduced to 2.24%, thus verifying the effectiveness of the invention.
The specific embodiments described herein are merely illustrative of the spirit of the invention. Various modifications or additions may be made to the described embodiments or alternatives in a similar manner to those skilled in the art to which the present invention pertains.

Claims (3)

1. A modulation method for reducing the error frequency of a single-phase photovoltaic grid-connected inverter THD is characterized in that a topological main circuit of the single-phase photovoltaic grid-connected inverter comprises a direct current source DC and a first switching tube Q1A second switch tube Q2And a third switching tube Q3And a fourth switching tube Q4An output filter inductor L, an output filter capacitor C and a load R, a direct current source DC provides direct current, a first switch tube Q1A second switch tube Q2And a third switching tube Q3And a fourth switching tube Q4A bridge circuit is formed, an output filter inductor L and an output filter capacitor C form an LC filter circuit for filtering the high-frequency carrier part, a load R is an output resistor, and is recorded as U0For outputting an effective value of the AC voltage, UdFor inputting direct current voltage, its characterized in that: provided with a first switch tube Q1And a second switching tube Q2Form a front arm S1 and a third switch tube Q3And a fourth switching tube Q4The rear arm S2 is composed by controlling the front arm S1 and the rear arm S2 respectively with SPWM pulses of different carrier frequenciessSwitched by the front arm S1Switching frequency, carrier frequency fmIs the switching frequency of the rear arm S2, and
fm＝nfs
and limiting the value range of n to
Figure FDA0002148318590000011
And preferably setting the value of n in the value range, so that the ratio of the low frequency to the high frequency of the switching frequencies of the two bridge arms is as close to 1 as possible.
2. The method for reducing the error frequency modulation of the single-phase photovoltaic grid-connected inverter THD according to claim 1, characterized in that: and preferably setting the value of n in the value range, and realizing by adopting a trial and error method.
3. The method for reducing the error frequency modulation of the single-phase photovoltaic grid-connected inverter THD according to claim 1 or 2, characterized in that: two SPWM pulse generation modules are adopted to respectively provide carrier frequencies fsSPWM pulse and carrier frequency fmSPWM pulse.
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