CN110335814B - Preparation method for preparing selective doping structure on silicon wafer and solar cell - Google Patents
Preparation method for preparing selective doping structure on silicon wafer and solar cell Download PDFInfo
- Publication number
- CN110335814B CN110335814B CN201910604535.2A CN201910604535A CN110335814B CN 110335814 B CN110335814 B CN 110335814B CN 201910604535 A CN201910604535 A CN 201910604535A CN 110335814 B CN110335814 B CN 110335814B
- Authority
- CN
- China
- Prior art keywords
- impurity source
- silicon wafer
- source layer
- doping
- doped region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 85
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 85
- 239000010703 silicon Substances 0.000 title claims abstract description 85
- 238000002360 preparation method Methods 0.000 title abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 151
- 238000000034 method Methods 0.000 claims abstract description 40
- 230000004888 barrier function Effects 0.000 claims abstract description 23
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- 229910004205 SiNX Inorganic materials 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910004012 SiCx Inorganic materials 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 229910021478 group 5 element Inorganic materials 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 239000013590 bulk material Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 230000008021 deposition Effects 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 238000005215 recombination Methods 0.000 description 5
- 230000006798 recombination Effects 0.000 description 5
- 230000004044 response Effects 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000004083 survival effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
- H01L21/2256—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides through the applied layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- High Energy & Nuclear Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Sustainable Development (AREA)
- Life Sciences & Earth Sciences (AREA)
- Optics & Photonics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Photovoltaic Devices (AREA)
Abstract
The invention relates to a preparation method for preparing a selective doping structure on a silicon wafer and a solar cell, wherein the selective doping structure comprises a light doping area and a heavy doping area, and the preparation method comprises the following steps: the method comprises the following steps that a first impurity source layer, a barrier layer and a second impurity source layer are sequentially arranged on a light receiving side or a backlight side of a silicon wafer from inside to outside, the doping properties of an impurity source in the second impurity source layer and the impurity source in the first impurity source layer relative to the silicon wafer are the same, and the concentration of the impurity source in the second impurity source layer is higher; doping the impurity source in the first impurity source layer into the silicon wafer in a high-temperature propulsion mode and forming a planar lightly doped region on the surface of the silicon wafer; and driving the impurity sources in the first impurity source layer and the second impurity source layer into the silicon wafer in the designated area in a laser driving mode to form a heavily doped area. The preparation method provided by the embodiment of the invention has the advantages that the surface doping concentration of the prepared lightly doped region is lower, the surface doping concentration of the heavily doped region is higher, and the preparation method is clean and pollution-free.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a preparation method for preparing a selective doping structure on a silicon wafer and a solar cell.
Background
Human survival and development are not energy-efficient. Solar energy is one of the most advantageous renewable, high volume, clean energy sources. Crystalline silicon solar cells are a type of semiconductor device that directly converts light energy into electrical energy. At present, in the preparation process of the crystalline silicon solar cell, the preparation process of the selective doping structure is a mainstream technology, because the selective doping structure comprises a light doping region and a heavy doping region, the light doping region has more excellent short-wave photoresponse, the contact minority carrier recombination between the heavy doping region and metal is reduced, and the contact resistance is lower.
However, the existing preparation method of the selective doping structure has obvious disadvantages, wherein, the laser doping diffusion method for forming a phosphosilicate glass (PSG) layer has a small concentration difference between a lightly doped region and a heavily doped region of the selective doping structure due to the limitation of the diffusion process; and a mask cleaning mode is adopted to clean part of the heavily doped region of the selective doping structure into a lightly doped region, so that a large amount of chemical solution is consumed, and chemical pollution is brought to the environment.
Disclosure of Invention
In order to solve the above technical problems, an object of the present invention is to provide a method for manufacturing a selective doping structure on a silicon wafer, wherein the method can independently control the doping concentrations of a lightly doped region and a heavily doped region of the selective doping structure, so that the surface doping concentration of the lightly doped region is lower and the surface doping concentration of the heavily doped region is higher, and thus the short-wave response of the lightly doped region is better, the metal contact recombination of the heavily doped region is lower, the contact resistance is lower, and the method is clean and pollution-free.
Another object of the present invention is to provide a solar cell using a silicon wafer prepared with the selectively doped structure prepared by the above preparation method, which has higher open circuit voltage and cell conversion efficiency.
In order to achieve the purpose, the invention adopts the following technical scheme:
according to the embodiment of the first aspect of the invention, the preparation method for preparing the selective doping structure on the silicon wafer, wherein the selective doping structure comprises a light doping area and a heavy doping area, comprises the following steps:
step S1, sequentially arranging a first impurity source layer, a barrier layer and a second impurity source layer from inside to outside on the light receiving side or the backlight side of the silicon wafer, wherein the doping properties of the impurity source in the second impurity source layer and the impurity source in the first impurity source layer relative to the silicon wafer are the same, and the concentration of the impurity source in the second impurity source layer is higher;
step S2, doping the impurity source in the first impurity source layer into the silicon wafer by a high-temperature advancing mode and forming a planar lightly doped region on the surface of the silicon wafer;
step 3, driving the impurity source in the first impurity source layer and the second impurity source layer into the silicon wafer in a designated area by laser driving, and forming the heavily doped region.
Preferably, the type of the silicon wafer is n-type or p-type.
Preferably, the first impurity source layer and the second impurity source layer are made of SiNx, SiON, SiOx, SiCx or amorphous silicon as a host material, and the impurity source is selected from group V elements or group III elements.
Preferably, the first impurity source layer and the second impurity source layer have thicknesses independent of each other of 1 to 1000 nm.
Preferably, the first impurity source layer and/or the second impurity source layer is/are prepared by a chemical vapor deposition method or a physical vapor deposition method, and the chemical vapor deposition method is any one of a low-pressure chemical vapor deposition method, a plasma-enhanced chemical vapor deposition method, and an atmospheric pressure chemical vapor deposition method.
Preferably, the main material of the barrier layer is SiNx, SiON, SiOx, SiCx or amorphous silicon, and the thickness of the barrier layer is 1 to 1000 nm.
Preferably, in the step S2, the high temperature propulsion manner is tubular high temperature propulsion, and the propulsion temperature is 500-.
Preferably, the doping concentration of the lightly doped region is 1 × 1017cm-3-1×1022cm-3。
Preferably, the doping concentration of the heavily doped region is 1 × 1019cm-3-1×1023cm-3。
Preferably, the preparation method for preparing the selective doping structure on the silicon wafer further comprises the following steps:
step S4, after the heavily doped region is formed, removing the first impurity source layer, the blocking layer, and the second impurity source layer.
The solar cell piece according to the embodiment of the second aspect of the invention comprises a silicon wafer, wherein the selective doping structure prepared by the preparation method according to any one of the above embodiments is prepared on the silicon wafer, and the selective doping structure is a selective emitter or a selective surface field.
The invention has the beneficial effects that:
according to the preparation method for preparing the selective doping structure on the silicon wafer, the first impurity source layer, the barrier layer and the second impurity source layer are sequentially arranged on the light receiving side or the backlight side of the silicon wafer from inside to outside, when the light doping region is formed in a high-temperature advancing mode, the barrier layer can effectively prevent impurities of the second impurity source layer from entering, and then the heavy doping region is formed in a laser advancing mode, so that the doping concentrations of the light doping region and the heavy doping region of the selective doping structure can be independently regulated and controlled as long as the impurity source concentrations of the first impurity source layer and the second impurity source layer are respectively controlled, the surface doping concentration of the light doping region of the prepared selective doping structure is lower, the surface doping concentration of the heavy doping region is higher, and as shown in fig. 8 and 9, the surface doping concentration of the light doping region can reach 1 x 1020cm-3Hereinafter, the surface doping concentration of the heavily doped region may reach 1 × 1021cm-3And further, the short-wave response of the lightly doped region is better, the metal contact recombination and the contact resistance of the heavily doped region are lower, and the preparation method is clean and pollution-free. And furthermore, a solar cell with higher open-circuit voltage and cell conversion efficiency can be obtained.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Drawings
FIG. 1 is a flow chart of a method for fabricating a selectively doped structure on a silicon wafer according to an embodiment of the present invention;
FIG. 2 is a silicon wafer after surface texturing according to an embodiment of the present invention;
FIG. 3 is a silicon wafer provided with a first impurity source layer, a barrier layer and a second impurity source layer according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a silicon wafer with selectively doped structures according to an embodiment of the present invention;
FIG. 5 is a silicon wafer with the first impurity source layer, the second impurity source layer and the barrier layer removed according to an embodiment of the present invention;
FIG. 6 shows a silicon wafer with an alumina passivation film and a SiNx film deposited thereon according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a solar cell according to an embodiment of the invention;
FIG. 8 is a graph illustrating doping profiles of lightly doped regions of selectively doped structures fabricated on a silicon wafer in accordance with an embodiment of the present invention;
fig. 9 is a doping profile of a heavily doped region of a selectively doped structure fabricated on a silicon wafer in accordance with an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention, but are not intended to limit the scope of the invention.
As shown in fig. 1 to 4, a method for manufacturing a selectively doped structure (including a lightly doped region 11 and a heavily doped region 12) on a silicon wafer 10 according to an embodiment of the present invention includes the following steps:
step S1, sequentially disposing a first impurity source layer 20, a blocking layer 30 and a second impurity source layer 40 on the light receiving side or the backlight side of the silicon wafer 10 from inside to outside, wherein the impurity source in the second impurity source layer 40 has the same doping property with respect to the silicon wafer 10 as the impurity source in the first impurity source layer 20, and the concentration of the impurity source in the second impurity source layer 20 is higher.
According to some embodiments of the present invention, the silicon wafer 10 may be either n-type or p-type in type. It should be noted that the doping property of the selective doping structure is opposite to the doping property of the silicon wafer 10, for example, when the type of the silicon wafer 10 is n-type, the doping property of the selective doping structure is p-type.
The doping property of the impurity source in the second impurity source layer 40 and the doping property of the impurity source in the first impurity source layer 20 with respect to the silicon wafer 10 are the same, that is, the doping property of the second impurity source layer 40 and the doping property of the impurity source in the first impurity source layer 20 with respect to the silicon wafer 10 are both p-type doping or n-type doping.
According to some embodiments of the present invention, the body material of the first and second impurity source layers 20 and 40 is SiNx, SiON, SiOx, SiCx, or amorphous silicon, and the impurity source in the first and second impurity source layers 20 and 40 is selected from a group V element or a group III element, wherein the impurity source is p-type doped when the impurity source is selected from a group III element, and n-type doped when the impurity source is selected from a group V element. That is, when the silicon wafer 10 is of an n-type, the impurity sources in the first and second impurity source layers 20 and 40 are selected from group III elements, and are p-type doped; when the silicon wafer 10 is p-type, the impurity sources in the first and second impurity source layers 20 and 40 are selected from group V elements and are doped n-type.
According to some embodiments of the present invention, the thicknesses of the first impurity source layer 20 and the second impurity source layer 40 are independent of each other and are 1 to 1000 nm. The first impurity source layer 20 and the second impurity source layer 40 may have the same thickness or different thicknesses, and the first impurity source layer 20 may be thicker than the second impurity source layer 40 or the first impurity source layer 20 may be thinner than the second impurity source layer 40.
Wherein the first impurity source layer 20 and/or the second impurity source layer 40 are/is prepared by a chemical vapor deposition method or a physical vapor deposition method, and the chemical vapor deposition method is any one of a low-pressure chemical vapor deposition method, a plasma-enhanced chemical vapor deposition method, and an atmospheric pressure chemical vapor deposition method.
In addition, there is no particular limitation regarding the impurity source concentration of the first impurity source layer 20, and the impurity source concentration of the second impurity source layer 40, and may be determined according to design requirements. Note that the impurity source concentration of the second impurity source layer 40 is higher than that of the first impurity source layer 20.
According to some embodiments of the present invention, the bulk material of the barrier layer 30 may be selected from SiNx, SiON, SiOx, SiCx or amorphous silicon, and the thickness of the barrier layer 30 may be 1-1000 nm.
Step S2, doping the impurity source in the first impurity source layer 20 into the silicon wafer 10 by high temperature drive, and forming a planar lightly doped region 11 on the surface of the silicon wafer 10.
According to some embodiments of the present invention, in step S2 of the above method for preparing a selective doping structure on a silicon wafer 10, the high temperature driving manner is a tubular high temperature driving, and the driving temperature is 500-.
Step S3, driving the impurity source of the first and second impurity source layers 20 and 40 into the silicon wafer 10 by laser driving in a designated area, and forming the heavily doped region 12.
That is, as shown in fig. 3, a first impurity source layer 20, a barrier layer 30 and a second impurity source layer 40 are sequentially deposited from inside to outside on the light receiving side or the backlight side of a silicon wafer 10, wherein the impurity source in the second impurity source layer 40 and the impurity source in the first impurity source layer 20 have the same doping property with respect to the silicon wafer 10, i.e., the doping property is p-type doping or n-type doping, and the concentration of the impurity source in the second impurity source layer 40 is higher than that of the impurity source in the first impurity source layer 20, as shown in fig. 4, the impurity source in the first impurity source layer 20 is doped into the silicon wafer 10 by a high temperature drive method, and a planar lightly doped region 11 is formed on the surface of the silicon wafer 10, and then the impurity sources in the first impurity source layer 20 and the second impurity source layer 40 are driven into the silicon wafer 10 by a laser drive method, and a heavily doped region 12 is formed.
Through the arrangement of the barrier layer 30, the impurity source in the second impurity source layer 40 is prevented from being pushed into the light doped region 11 in the selective doping structure, so that the doping concentrations of the light doped region 11 and the heavy doped region 12 of the selective doping structure can be independently regulated, the surface doping concentration of the light doped region 11 of the prepared selective doping structure is lower, the surface doping concentration of the heavy doped region 12 is higher, the short-wave response of the light doped region 11 is better, the metal contact recombination and the contact resistance of the heavy doped region 12 are lower, and further, a solar cell with higher open-circuit voltage and cell conversion efficiency can be obtained. And the preparation method is clean and pollution-free.
The above-described fabrication method for fabricating selectively doped structures on a silicon wafer 10 according to some embodiments of the present invention selectively dopes the doped structures fabricated on the silicon wafer 10In the structure, the doping concentration of the lightly doped region 11 is 1 × 1017cm-3-1×1022cm-3The heavily doped region 12 has a doping concentration of 1 × 1019cm-3-1×1023cm-3。
According to some embodiments of the present invention, in the above-described method for fabricating a selectively doped structure on a silicon wafer 10, after forming the heavily doped region 12, the first impurity source layer 20, the barrier layer 30, and the second impurity source layer 40 are removed.
The silicon wafer 10 with the selective doping structure prepared according to the preparation method for preparing the selective doping structure on the silicon wafer 10 can be used for forming a solar cell, wherein the selective doping structure can be a selective emitter or a selective surface field in the solar cell, and the solar cell has higher open-circuit voltage and cell conversion efficiency.
The invention is described below by means of specific examples.
As shown in fig. 2 to 7, a method for manufacturing a solar cell in which a silicon wafer 10 is manufactured with a selectively doped structure manufactured according to the above manufacturing method for manufacturing a selectively doped structure on a silicon wafer 10 includes the steps of:
A. texturing: selecting a P-type silicon wafer 10, wherein the volume resistivity of the P-type silicon wafer is 2.0 omega cm, performing surface texturing on the light receiving surface of the silicon wafer 10, and the light receiving surface reflectivity of the obtained silicon wafer 10 with the textured surface reaches 12%;
B. deposition of the first impurity source layer 20: a first impurity source layer 20 with the thickness of 100nm is formed on the light receiving surface of the silicon wafer 10 through atmospheric pressure vapor deposition, wherein the first impurity source layer 20 is a phosphorosilicate glass layer containing a small amount of impurity source phosphorus doping at the bottom;
C. deposition of the barrier layer 30: a barrier layer 30 with a thickness of 100nm is vapor-deposited on the first impurity source layer 20 at normal pressure, and the barrier layer 30 is a silicon oxide layer;
D. deposition of the second impurity source layer 40: a second impurity source layer 40 with the thickness of 100nm is deposited on the barrier layer 30 in a normal pressure vapor phase mode, and the second impurity source layer 40 is a phosphorus-silicon glass layer which is rich in impurity source phosphorus and doped;
E. formation of the lightly doped region 11 of the selective doping structure: doping impurity source phosphorus in a first impurity source layer 20 into a silicon wafer 10 in a tubular device in a tubular high-temperature propelling mode, and forming a planar lightly doped region 11 on the surface of the silicon wafer 10, wherein the temperature of the tubular high-temperature propelling is 830 ℃, and the time is 30 min;
F. formation of the heavily doped region 12 of the selectively doped structure: scanning a metal grid line pattern in a designated area by using laser to push impurity sources in the first impurity source layer 20 and the second impurity source layer 40 into the silicon wafer 10 to form a heavily doped region 12, wherein the process parameters of the laser are as follows: the wavelength is 532nm, the pulse width is 10ns, the frequency is 200KHz, and the power is 30W;
G. removing the first impurity source layer 20, the second impurity source layer 40, and the barrier layer 30: cleaning and removing the first impurity source layer 20, the second impurity source layer 40 and the barrier layer 30 with a hydrofluoric acid solution;
H. growing an oxide layer: introducing oxygen in a tubular device at 800 deg.C for 30min to generate a silicon oxide layer with a thickness of 10nm on the surface of the light receiving surface of the silicon wafer 10;
I. deposition of the alumina passivation film 50: depositing an aluminum oxide passivation film 50 on the backlight surface of the silicon wafer 10 by using atomic energy deposition equipment, wherein the thickness of the aluminum oxide passivation film 50 is 10 nm;
J. deposition of SiNx film 60: depositing SiNx films 60 with passivation and antireflection effects on a light receiving surface and a backlight surface of the silicon wafer 10 by adopting a plasma enhanced chemical vapor deposition method, wherein the thickness of the SiNx film 60 deposited on the light receiving surface is 80nm, and the thickness of the SiNx film 60 deposited on the backlight surface is 90 nm;
K. grooving: grooving the SiNx film 60 on the backlight surface of the silicon wafer 10 by using laser with the wavelength of 532 nm;
l, manufacturing the metal electrode 70: the conductive paste is printed on the light receiving surface and the backlight surface of the silicon wafer 10, respectively, to form the metal electrode 70.
The silicon wafer 10 with selectively doped structure obtained according to the above embodiment has the doping concentration of the lightly doped region 11 and the doping concentration of the heavily doped region 12 with respect to the depth as shown in fig. 8 and 9, respectively, wherein the surface doping concentration of the lightly doped region can be foundUp to 1 × 1020cm-3Hereinafter, the surface doping concentration of the heavily doped region may reach 1 × 1021cm-3And further, the short-wave response of the lightly doped region is better, the metal contact recombination and the contact resistance of the heavily doped region are lower, and the obtained solar cell has higher open-circuit voltage and cell conversion efficiency.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for producing a selectively doped structure on a silicon wafer (10), said selectively doped structure comprising a lightly doped region (11) and a heavily doped region (12), characterized in that it comprises the following steps:
step S1, arranging a first impurity source layer (20), a barrier layer (30) and a second impurity source layer (40) in sequence from inside to outside on the light receiving side or the backlight side of a silicon wafer (10), wherein the impurity source in the second impurity source layer (40) and the impurity source in the first impurity source layer (20) have the same doping property relative to the silicon wafer (10), and the concentration of the impurity source in the second impurity source layer (40) is higher;
step S2, doping the impurity source in the first impurity source layer (20) into the silicon wafer (10) by a high-temperature advancing mode and forming a planar lightly doped region (11) on the surface of the silicon wafer (10);
step S3, driving the impurity source in the first impurity source layer (20) and the second impurity source layer (40) into the silicon wafer (10) in a designated area by laser driving, and forming the heavily doped region (12).
2. The method for preparing a selectively doped structure on a silicon wafer (10) according to claim 1, characterized in that the type of the silicon wafer (10) is n-type or p-type.
3. The method of claim 1, wherein the first impurity source layer (20) and the second impurity source layer (40) are made of SiNx, SiON, SiOx, SiCx or amorphous silicon as a host material, and the impurity source is selected from group V elements and group III elements.
4. The method for preparing a selectively doped structure on a silicon wafer (10) according to claim 1, wherein the thickness of the first impurity source layer (20) and the second impurity source layer (40) are independent of each other and are 1-1000nm,
the first impurity source layer (20) and/or the second impurity source layer (40) are/is prepared by a chemical vapor deposition method or a physical vapor deposition method, wherein the chemical vapor deposition method is any one of a low-pressure chemical vapor deposition method, a plasma-enhanced chemical vapor deposition method and an atmospheric pressure chemical vapor deposition method.
5. The method of claim 1, wherein the bulk material of the barrier layer (30) is SiNx, SiON, SiOx, SiCx, or amorphous silicon, and the thickness of the barrier layer (30) is 1-1000 nm.
6. The method as claimed in claim 1, wherein the step S2 is carried out by a tubular high temperature propulsion method at a propulsion temperature of 500-1000 ℃.
7. Method for producing a selectively doped structure on a silicon wafer (10) according to claim 1, characterized in that the doping concentration of the lightly doped region (11) is 1 x 1017cm-3-1×1022cm-3。
8. Method for preparing a selectively doped structure on a silicon wafer (10) according to claim 1, characterized in that the doping concentration of the heavily doped region (12) is 1 x 1019cm-3-1×1023cm-3。
9. The method of claim 1, further comprising the steps of:
step S4, after the heavily doped region (12) is formed, removing the first impurity source layer (20), the barrier layer (30), and the second impurity source layer (40).
10. A solar cell, characterized in that it comprises a silicon wafer (10), said silicon wafer (10) being provided with a selectively doped structure produced according to the production method of producing a selectively doped structure on a silicon wafer (10) according to any one of claims 1 to 9, said selectively doped structure being a selective emitter or a selective surface field.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910604535.2A CN110335814B (en) | 2019-07-05 | 2019-07-05 | Preparation method for preparing selective doping structure on silicon wafer and solar cell |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910604535.2A CN110335814B (en) | 2019-07-05 | 2019-07-05 | Preparation method for preparing selective doping structure on silicon wafer and solar cell |
Publications (2)
Publication Number | Publication Date |
---|---|
CN110335814A CN110335814A (en) | 2019-10-15 |
CN110335814B true CN110335814B (en) | 2021-10-22 |
Family
ID=68144263
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910604535.2A Active CN110335814B (en) | 2019-07-05 | 2019-07-05 | Preparation method for preparing selective doping structure on silicon wafer and solar cell |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN110335814B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN116053353A (en) * | 2022-12-01 | 2023-05-02 | 江苏杰太光电技术有限公司 | Preparation method of boron doped selective emitter and N-type crystalline silicon solar cell |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103050568A (en) * | 2011-10-13 | 2013-04-17 | 三星Sdi株式会社 | Method of manufacturing a photoelectric device |
CN103155178A (en) * | 2010-06-18 | 2013-06-12 | 弗劳恩霍弗实用研究促进协会 | Method for producing a selective doping structure in a semiconductor substrate in order to produce a photovoltaic solar cell |
CN109616528A (en) * | 2018-10-29 | 2019-04-12 | 晶澳太阳能有限公司 | A kind of preparation method of selective emitter of solar battery |
-
2019
- 2019-07-05 CN CN201910604535.2A patent/CN110335814B/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103155178A (en) * | 2010-06-18 | 2013-06-12 | 弗劳恩霍弗实用研究促进协会 | Method for producing a selective doping structure in a semiconductor substrate in order to produce a photovoltaic solar cell |
CN103050568A (en) * | 2011-10-13 | 2013-04-17 | 三星Sdi株式会社 | Method of manufacturing a photoelectric device |
CN109616528A (en) * | 2018-10-29 | 2019-04-12 | 晶澳太阳能有限公司 | A kind of preparation method of selective emitter of solar battery |
Also Published As
Publication number | Publication date |
---|---|
CN110335814A (en) | 2019-10-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN109713065B (en) | Passivation solar cell with printed metal electrode and preparation method thereof | |
EP3457448A1 (en) | Stacked photoelectric conversion device and method for producing same | |
EP2128904A2 (en) | Tandem thin-film silicon solar cell and method for manufacturing the same | |
CN114678446A (en) | Low-cost contact passivation full-back electrode solar cell and preparation method thereof | |
RU2456709C2 (en) | Solar cell and method and apparatus for making said solar cell | |
CN112490304A (en) | Preparation method of high-efficiency solar cell | |
EP2782146A1 (en) | Solar cell with reduced potential induced degradation and manufacturing method thereof | |
JP6125594B2 (en) | Method for manufacturing photoelectric conversion device | |
WO2013003828A2 (en) | A tandem solar cell using a silicon microwire array and amorphous silicon photovoltaic layer | |
CN218788382U (en) | High-efficiency heterojunction solar cell | |
CN114864729A (en) | Silicon-based heterojunction solar cell and preparation method thereof | |
JP7109833B2 (en) | SEMI-LAYER FLEXIBLE SILICON-BASED THIN-FILM SOLAR CELL AND MANUFACTURING METHOD THEREOF | |
CN110931603A (en) | Solar cell and preparation method thereof | |
CN110335814B (en) | Preparation method for preparing selective doping structure on silicon wafer and solar cell | |
CN114050105A (en) | TopCon battery preparation method | |
JP6330108B1 (en) | High photoelectric conversion efficiency solar cell and method for producing high photoelectric conversion efficiency solar cell | |
CN116130558B (en) | Preparation method of novel all-back electrode passivation contact battery and product thereof | |
CN103107240B (en) | Multi-crystal silicon film solar battery and preparation method thereof | |
JP2013214672A (en) | Photoelectric conversion element | |
CN113594295B (en) | Preparation method of solar cell with double-sided passivation structure | |
CN111886706A (en) | Method for manufacturing series solar cell | |
JP2675754B2 (en) | Solar cell | |
CN114744077A (en) | Manufacturing method of N-type TBC crystalline silicon solar cell | |
CN113471322B (en) | Laminated photovoltaic device and production method | |
KR20140110911A (en) | Method for the low-temperature production of radial-junction semiconductor nanostructures, radial junction device, and solar cell including radial-junction nanostructures |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |