CN110299975A - A kind of the verifying system and equipment of fpga chip interconnection parallel interface - Google Patents
A kind of the verifying system and equipment of fpga chip interconnection parallel interface Download PDFInfo
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- CN110299975A CN110299975A CN201910577770.5A CN201910577770A CN110299975A CN 110299975 A CN110299975 A CN 110299975A CN 201910577770 A CN201910577770 A CN 201910577770A CN 110299975 A CN110299975 A CN 110299975A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/24—Testing correct operation
- H04L1/242—Testing correct operation by comparing a transmitted test signal with a locally generated replica
Abstract
This application discloses a kind of verifying systems of fpga chip interconnection parallel interface, it include: transmitting terminal, for generating echo signal according to default bit wide and default overturning rate, and echo signal and the corresponding clock signal of echo signal are sent to receiving end by parallel interface；Receiving end, for the echo signal received to be converted to first object data；Signal is generated according to default bit wide and default overturning rate, and the signal of generation is converted into the second target data；Judge whether first object data are consistent with the second target data；If so, parallel interface is normal；If it is not, then parallel interface is abnormal.Transmitting terminal and receiving end in the system are communicated by parallel interface, functional good if parallel interface is normal；If parallel interface is abnormal, functionality is impaired, and the electric general character may also have problem.Correspondingly, the verifying equipment of a kind of fpga chip interconnection parallel interface disclosed in the present application, similarly has above-mentioned technique effect.
Description
Technical field
This application involves the field of test technology, in particular to a kind of fpga chip interconnects the verifying system of parallel interface and sets
It is standby.
Background technique
It is that the interface standard of data is transmitted using parallel transmission mode that fpga chip, which interconnects parallel interface, parallel interface packet
Include clock line and data circuit, data circuit has multiple data bit, this multiple data bit can simultaneous transmission data, therefore
Have the characteristics that efficiency of transmission is high, fireballing.
Currently, interconnecting connectivity of the verifying primarily directed to circuit of parallel interface to fpga chip.Such as: by adjusting
The devices such as capacitor or resistance on FPGA, to control the voltage of parallel interface one end, while it is another to detect parallel interface
Whether the voltage of one end can accordingly change, if can be with, then it is assumed that the connectivity of parallel interface is good.Existing verification mode
It is able to validate only the Circuit Connectivity of parallel interface, and Circuit Connectivity can not well determine whether the functionality of parallel interface is good
It is good.
Therefore, the functionality for how verifying parallel interface is those skilled in the art's problem to be solved.
Summary of the invention
In view of this, the verifying system for being designed to provide a kind of fpga chip interconnection parallel interface of the application and setting
It is standby, to verify the functionality of parallel interface.Its concrete scheme is as follows:
In a first aspect, this application provides a kind of verifying systems of fpga chip interconnection parallel interface, comprising:
Transmitting terminal for generating echo signal according to default bit wide and default overturning rate, and sends mesh by parallel interface
Signal and the corresponding clock signal of echo signal are marked to receiving end；
Receiving end, for the echo signal received to be converted to first object data；It is turned over according to default bit wide with default
Rate of rotation generates signal, and the signal of generation is converted to the second target data；Judge first object data and the second target data
It is whether consistent；If so, parallel interface is normal；If it is not, then parallel interface is abnormal.
Preferably, further includes:
Oscillograph detects the clock of transmitting terminal transmission if inconsistent for first object data and the second target data
Whether signal and the received clock signal in receiving end are consistent；If；Clock line then in parallel interface is normal；If it is not, then simultaneously
Clock line in line interface is abnormal.
Preferably, transmitting terminal is also used to: if clock line is normal, the target data position controlled in default bit wide is closed,
And detection signal is generated according to default bit wide and default overturning rate, and detection signal, and detection letter are sent by parallel interface
Number corresponding clock signal is to receiving end；
Receiving end is also used to: the detection signal received is converted to detection data；Judge detection data and the second target
Whether data are consistent；If so, target data position is abnormal.
Preferably, transmitting terminal is also used to:
Clock signal is adjusted by frequency multiplication mode or frequency dividing mode.
Preferably, transmitting terminal is also used to:
Using homologous clock corresponding with the clock signal that transmitting terminal is sent, the echo signal that transmitting terminal is sent and exhibition are acquired
Show.
Preferably, receiving end is also used to:
Using homologous clock corresponding with the clock signal that receiving end receives, the echo signal that receiving end receives is acquired
And it shows.
Preferably, further includes:
Host computer, the echo signal that echo signal and receiving end for sending transmitting terminal receive compare, and
Comparing result is shown.
Preferably, transmitting terminal is also used to:
Default bit wide is adjusted, and echo signal is generated according to bit wide adjusted and default overturning rate.
Preferably, transmitting terminal is also used to:
Default overturning rate is adjusted, and echo signal is generated according to overturning rate adjusted and default bit wide.
Second aspect, this application provides a kind of verifying equipment of fpga chip interconnection parallel interface, comprising:
Bit wide selecting module, the bit wide for goal-selling signal；
Overturning rate control module, the overturning rate for goal-selling signal；
Clock control module, for generating clock signal corresponding with echo signal；
Sending module, for sending echo signal and clock signal by parallel interface；
Receiving module, for receiving echo signal and clock signal；
Acquisition module, for the echo signal received to be converted to first object data；
The signal of generation for generating signal using bit wide and overturning rate, and is converted to the second number of targets by correction verification module
According to；Judge whether first object data are consistent with the second target data；If so, parallel interface is normal；If it is not, then parallel interface
It is abnormal.
By above scheme it is found that this application provides a kind of verifying systems of fpga chip interconnection parallel interface, comprising:
Transmitting terminal for generating echo signal according to default bit wide and default overturning rate, and sends echo signal by parallel interface, with
And the corresponding clock signal of echo signal is to receiving end；Receiving end, for the echo signal received to be converted to first object
Data；Signal is generated according to default bit wide and default overturning rate, and the signal of generation is converted into the second target data；Judge
Whether one target data is consistent with the second target data；If so, parallel interface is normal；If it is not, then parallel interface is abnormal.
As it can be seen that the transmitting terminal and receiving end in the system are communicated by parallel interface.Wherein, receiving end can and be sent out
Sending end generates signal according to identical rule, therefore the signal that the receiving end signal and the transmitting terminal that generate are sent is identical；And it connects
Receiving end can compare the signal that the signal and transmitting terminal that itself is received are sent, if the two is consistent, show to receive
Signal it is correct, i.e., parallel interface is normal；If the two is inconsistent, show the signal error received, it may be assumed that parallel interface is different
Often.If the signal that receiving end receives is correct, show that parallel interface can work normally, it is functional good.If receiving end
The signal error received then shows that parallel interface can not work normally, and functionality is impaired, and the electric general character, which may exist, asks
Topic.If the functionality for verifying parallel interface is good, then its electric general character is also certain, there is no problem.
Correspondingly, the verifying equipment of a kind of fpga chip interconnection parallel interface provided by the present application, similarly has above-mentioned
Technical effect.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of application for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the verifying system schematic that a kind of fpga chip disclosed in the present application interconnects parallel interface；
Fig. 2 is the verifying equipment schematic diagram that a kind of fpga chip disclosed in the present application interconnects parallel interface；
Fig. 3 is another verifying equipment schematic diagram realized by FPGA disclosed in the present application.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of embodiments of the present application, instead of all the embodiments.It is based on
Embodiment in the application, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall in the protection scope of this application.
Currently, existing verification mode is able to validate only the Circuit Connectivity of parallel interface, and Circuit Connectivity well can not be true
Whether the functionality for determining parallel interface is good.For this purpose, this application provides a kind of authentications of fpga chip interconnection parallel interface
Case is able to verify that the functionality of parallel interface.
Shown in Figure 1, the embodiment of the present application discloses the verifying system of the first fpga chip interconnection parallel interface, packet
It includes:
Transmitting terminal 101 for generating echo signal according to default bit wide and default overturning rate, and passes through parallel interface and sends
Echo signal and the corresponding clock signal of echo signal are to receiving end.
Receiving end 102, for the echo signal received to be converted to first object data；According to default bit wide and preset
Overturning rate generates signal, and the signal of generation is converted to the second target data；Judge first object data and the second number of targets
According to whether consistent；If so, parallel interface is normal；If it is not, then parallel interface is abnormal.
In the present embodiment, transmitting terminal is also used to: if clock line is normal, controlling the target data position in default bit wide
It closes, and detection signal is generated according to default bit wide and default overturning rate, and detection signal, Yi Jijian are sent by parallel interface
The corresponding clock signal of signal is surveyed to receiving end；Receiving end is also used to: the detection signal received is converted to detection data；Sentence
Whether disconnected detection data is consistent with the second target data；If so, target data position is abnormal.In order to further determine target data
Whether position is normal, can detect according to aforesaid way provided in this embodiment to target data position.
Wherein, transmitting terminal is also used to: adjusting clock signal by frequency multiplication mode or frequency dividing mode.It is sent using with transmitting terminal
The corresponding homologous clock of clock signal, acquisition transmitting terminal send echo signal and displaying.Default bit wide is adjusted, and according to tune
Bit wide and default overturning rate after whole generate echo signal.Default overturning rate is adjusted, and according to overturning rate adjusted and is preset
Bit wide generates echo signal.
Wherein, receiving end is also used to: using homologous clock corresponding with the clock signal that receiving end receives, acquisition is received
Terminate the echo signal received and displaying.
In the present embodiment, the verifying system of fpga chip interconnection parallel interface further include: oscillograph, if being used for the first mesh
It marks data and the second target data is inconsistent, then the received clock signal of clock signal and receiving end for detecting transmitting terminal transmission is
It is no consistent；If；Clock line then in parallel interface is normal；If it is not, then the clock line in parallel interface is abnormal.Namely
It says, if parallel interface is abnormal, the clock line of parallel interface can be detected first with the presence or absence of problem.That is: it is examined using oscillograph
Whether clock signal and the received clock signal in receiving end for surveying transmitting terminal transmission are consistent；If two clock signals are consistent, table
Bright clock line is normal；If two clock signals are inconsistent, show clock line exception.
Specifically, testing staff can based on oscillograph observation oscilloscope measure transmitting terminal waveform result whether just
Often；That is whether observation clock waveform meets the requirement of default clock signal, wherein clock frequency and duty ratio etc. can be primarily upon
Characteristic parameter.If clock waveform does not meet the requirement of default clock signal, then it is assumed that the clock signal of transmitting terminal may be wrong.Cause
After this can be adjusted the clock signal of transmitting terminal, then transmitted.
In the present embodiment, the verifying system of fpga chip interconnection parallel interface further include: host computer is used for transmitting terminal
The echo signal that the echo signal of transmission and receiving end receive compares, and comparing result is shown.
It should be noted that the parallel interface in the present embodiment be connect the parallel interface of different fpga chips, including when
Clock route and data circuit.That is, transmitting terminal can be a certain fpga chip, receiving end can be another fpga chip,
The two is connected by parallel interface.
As it can be seen that the transmitting terminal and receiving end in disclosed system are communicated by parallel interface.Wherein, it receives
End can generate signal, therefore the signal phase of the receiving end signal generated and transmitting terminal transmission according to identical rule with transmitting terminal
Together；And receiving end can compare the signal that the signal and transmitting terminal that itself is received are sent, if the two is consistent, table
The bright signal received is correct, i.e., parallel interface is normal；If the two is inconsistent, show the signal error received, it may be assumed that parallel
Interface is abnormal.If the signal that receiving end receives is correct, show that parallel interface can work normally, it is functional good.If
The signal error that receiving end receives then shows that parallel interface can not work normally, and functionality is impaired, and the electric general character may
There are problems.If the functionality for verifying parallel interface is good, then its electric general character is also certain, there is no problem.
A kind of verifying equipment of fpga chip interconnection parallel interface provided by the embodiments of the present application is introduced below, under
A kind of verifying equipment of fpga chip interconnection parallel interface of text description and a kind of above-described fpga chip are interconnected and are connect parallel
The verifying system of mouth can be cross-referenced.
Shown in Figure 2, the embodiment of the present application discloses a kind of verifying equipment of fpga chip interconnection parallel interface, packet
It includes:
Bit wide selecting module 201, the bit wide for goal-selling signal；
Overturning rate control module 202, the overturning rate for goal-selling signal；
Clock control module 203, for generating clock signal corresponding with echo signal；
Sending module 204, for sending echo signal and clock signal by parallel interface；
Receiving module 205, for receiving echo signal and clock signal；
Acquisition module 206, for the echo signal received to be converted to first object data；
The signal of generation for generating signal using bit wide and overturning rate, and is converted to the second target by correction verification module 207
Data；Judge whether first object data are consistent with the second target data；If so, parallel interface is normal；If it is not, then connecing parallel
Mouth is abnormal.
Wherein, bit wide selecting module, overturning rate control module, clock control module and sending module are set to transmitting terminal；
Receiving module, acquisition module and correction verification module are set to receiving end, specifically refer to Fig. 2.
In a specific embodiment, the verifying equipment of fpga chip interconnection parallel interface further include:
The data bit for being set to transmitting terminal enables module, and data bit, which enables module, can control each data bit closing or connect
It is logical, each data bit can be so detected one by one.
Data bit enables module can be with positioning failure data bit.If signal and sending module that receiving module receives are sent
Signal it is inconsistent, then show the signal error that receiving module receives, then it is parallel to can use the device measurings such as oscillograph
Interface clock signal；If clock signal is abnormal, illustrate that clock line is wrong；If clock signal is normal, data can be passed through
The enabled module positioning failure data bit in position.
Such as: some data bit is only closed, then transmits signal according to previous signal transmission process, if this receives mould
The data that block receives are consistent with the data that previous receiving module receives, then illustrate that the data bit being presently off is fault data
Position；Otherwise, it is connected to the data bit being presently off, closes next data bit, until orienting fault data position.If without legal
Fault data position is arrived in position, then it possible be multiple for illustrating that fault data is, therefore can close two, even more data bit, directly
To orienting fault data position.
In a specific embodiment, bit wide selecting module is also used to adjust default bit wide.Bit wide selecting module can be with
The bit wide of signal is controlled, bit wide is are as follows: the number of data bit shared by current demand signal or data.Wherein, bit wide is bigger, indicates same
When the data bit transmitted it is more, the requirement of interface circuit is higher.
In a specific embodiment, overturning rate control module is also used to adjust default overturning rate.Overturning rate controls mould
Block can control the overturning rate of parallel interface data bit.Overturning rate is are as follows: in the same rising edge clock of parallel interface or failing edge,
The data bit for carrying out level jump overturning accounts for the ratio of total data position.Such as: initial signal 10000100, after the jump signal
It is 10000111, latter two are 1 by 0 jump, then overturning rate is are as follows: 2/8=25%.Wherein, data bit level is from high to low
Jump is different with required electric energy is jumped from low to high, i.e., negative jump is different from electric energy needed for positive transition.Overturning rate is higher, right
The requirement of interface circuit is higher.Overturning rate control module can also control positive and negative jump respectively shared ratio, thus can be with
The various working conditions of parallel interface data bit are simulated, to carry out comprehensive verification to the functional of parallel interface.
In a specific embodiment, clock control module is also used to adjust clock by frequency multiplication mode or frequency dividing mode
Signal.If the equipment is realized by FPGA, the clock of different frequency can produce by frequency dividing or frequency multiplication by FPGA global clock
Signal, thus the working frequency of controllable parallel interface.Wherein, clock frequency is higher, and the requirement to parallel interface is higher.
In a specific embodiment, the verifying equipment of fpga chip interconnection parallel interface further include:
It is set to another acquisition module of transmitting terminal, when for utilizing corresponding with the clock signal that transmitting terminal is sent homologous
Clock, the echo signal and displaying, the echo signal actually sent with detection and the desired target letter sent that acquisition transmitting terminal is sent
It is number whether consistent.Wherein, the frequency of homologous clock is greater than or equal to the frequency for the clock signal that transmitting terminal is sent.
In a specific embodiment, the acquisition module for being set to receiving end is also used to: being received using with receiving end
The corresponding homologous clock of clock signal, the acquisition echo signal that receives of receiving end and displaying.Wherein, the frequency of homologous clock
Greater than or equal to the frequency for the clock signal that receiving end receives.
In a specific embodiment, the echo signal and receiving end reception that host computer sends transmitting terminal be can use
To echo signal compare, and comparing result is shown.Thus can by host computer show comparing result and
The correction verification module of correction verification module compares；If the two is consistent, illustrate that verification result is correct；If the two is inconsistent,
Technical staff can further determine that host computer comparing result mistake or correction verification module check errors, also or the two
It is incorrect.
Fig. 3 is referred to, Fig. 3 is a kind of verifying equipment realized by FPGA provided in this embodiment.Including it is each
Module can be corresponded to reference to corresponding contents disclosed above, therefore details are not described herein for the present embodiment.
Wherein, previous embodiment can be referred to by closing the more specifical course of work of modules, unit in this present embodiment
Disclosed in corresponding contents, no longer repeated herein.
As it can be seen that present embodiments providing a kind of verifying equipment of fpga chip interconnection parallel interface, which can be based on
FPGA realizes that the function of that is, above-mentioned modules can be realized using the logic circuit in FPGA.Namely pass through the volume in FPGA
The working condition of its parallel interface of journey logic control, to verify the functionality of parallel interface, while this equipment has debugging function
Can, it can be where precise positioning goes wrong.The various working conditions of parallel interface can also be sufficiently verified, which passes through tune
Whole bit wide and overturning rate can be achieved.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with it is other
The difference of embodiment, same or similar part may refer to each other between each embodiment.
The software mould that step described in conjunction with the examples disclosed in this document can directly use hardware, processor to execute
The combination of block or the two is implemented.Software module can be placed in random access memory (RAM), memory, read-only memory (ROM),
Institute is public in electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field
In any other form of readable storage medium storing program for executing known.
Specific examples are used herein to illustrate the principle and implementation manner of the present application, and above embodiments are said
The bright core concept for being merely used to help understand the application；At the same time, for those skilled in the art, according to the application's
Thought, there will be changes in the specific implementation manner and application range, in conclusion the content of the present specification should not be construed as
Limitation to the application.
Claims (10)
1. a kind of verifying system of fpga chip interconnection parallel interface characterized by comprising
Transmitting terminal for generating echo signal according to default bit wide and default overturning rate, and sends the mesh by parallel interface
Signal and the corresponding clock signal of the echo signal are marked to receiving end；
The receiving end, for the echo signal received to be converted to first object data；According to the default bit wide and institute
It states default overturning rate and generates signal, and the signal of generation is converted into the second target data；Judge the first object data and
Whether second target data is consistent；If so, the parallel interface is normal；If it is not, then the parallel interface is abnormal.
2. the verifying system of fpga chip interconnection parallel interface according to claim 1, which is characterized in that further include:
Oscillograph detects the transmitting terminal hair if inconsistent for the first object data and second target data
Whether the clock signal sent and the received clock signal in the receiving end are consistent；If；The then clock line in the parallel interface
Road is normal；If it is not, then the clock line in the parallel interface is abnormal.
3. the verifying system of fpga chip interconnection parallel interface according to claim 2, which is characterized in that
The transmitting terminal is also used to: if the clock line is normal, the target data position controlled in the default bit wide is closed,
And detection signal is generated according to the default bit wide and the default overturning rate, and the detection is sent by the parallel interface
Signal and the corresponding clock signal of the detection signal are to receiving end；
The receiving end is also used to: the detection signal received is converted to detection data；Judge the detection data and described
Whether the second target data is consistent；If so, the target data position is abnormal.
4. the verifying system of fpga chip interconnection parallel interface according to claim 3, which is characterized in that the transmitting terminal
It is also used to:
The clock signal is adjusted by frequency multiplication mode or frequency dividing mode.
5. the verifying system of fpga chip interconnection parallel interface according to claim 4, which is characterized in that the transmitting terminal
It is also used to:
Using the corresponding homologous clock of the clock signal sent with the transmitting terminal, the echo signal that the transmitting terminal is sent is acquired
And it shows.
6. the verifying system of fpga chip interconnection parallel interface according to claim 5, which is characterized in that the receiving end
It is also used to:
Using the corresponding homologous clock of the clock signal received with the receiving end, the target that the receiving end receives is acquired
Signal is simultaneously shown.
7. the verifying system of fpga chip interconnection parallel interface according to claim 6, which is characterized in that further include:
Host computer, the echo signal that signal and the receiving end for generating the transmitting terminal receive compare, and
Comparing result is shown.
8. the verifying system of fpga chip interconnection parallel interface according to claim 1, which is characterized in that the transmitting terminal
It is also used to:
The default bit wide is adjusted, and echo signal is generated according to bit wide adjusted and the default overturning rate.
9. the verifying system of fpga chip interconnection parallel interface according to claim 1, which is characterized in that the transmitting terminal
It is also used to:
The default overturning rate is adjusted, and echo signal is generated according to overturning rate adjusted and the default bit wide.
10. a kind of verifying equipment of fpga chip interconnection parallel interface characterized by comprising
Bit wide selecting module, the bit wide for goal-selling signal；
Overturning rate control module, for presetting the overturning rate of the echo signal；
Clock control module, for generating clock signal corresponding with the echo signal；
Sending module, for sending the echo signal and the clock signal by parallel interface；
Receiving module, for receiving the echo signal and the clock signal；
Acquisition module, for the echo signal received to be converted to first object data；
The signal of generation for generating signal using the bit wide and the overturning rate, and is converted to the second mesh by correction verification module
Mark data；Judge whether the first object data and second target data are consistent；If so, the parallel interface is just
Often；If it is not, then the parallel interface is abnormal.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113986600A (en) * | 2021-11-04 | 2022-01-28 | 北京智芯微电子科技有限公司 | Test method and device for chip serial interface and chip |
| CN113986600B (en) * | 2021-11-04 | 2023-02-03 | 北京智芯微电子科技有限公司 | Test method and device for chip serial interface and chip |
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