Circuit verification method for three-core power line plug wire
Technical Field
The invention relates to the technical field of three-core power lines, in particular to a circuit verification method for a three-core power line plug wire.
Background
Power cord plugs are widely used in the household appliance industry.
In order to improve efficiency and reduce cost, the power line plug wire is often manufactured in a manual mass production mode, but the manual mass production mode is adopted, so that the L pole, the N pole and the G pole of the power line plug wire are easily connected wrongly when in crimping, and the power line plug wire is not crimped in a one-to-one correspondence mode, so that the produced power line plug wire has unqualified products.
The traditional way of detecting the power cord and plug cord is that: and detecting the logic relation and the on-off of the detected finished product by adopting a logic detector. However, this device is not fully directed to the detection of a three-core, power cord and plug cord harness, and its connection is cumbersome and the cost of the device is high; the second step is as follows: adopt the break-make pen, detect one by one to each way of three-core plug power cord pencil, however, detect the number of times many, intensity is big, has caused the waste of cost of labor to the mill to detection efficiency is low, and artifical detection error rate is higher.
Disclosure of Invention
The invention aims to: aiming at the defects of the prior art, the circuit verification method of the three-core power line plug wire is simple to operate, automatic in detection, high in detection efficiency and capable of avoiding detection errors caused by human factors.
The technical scheme adopted by the invention is that the circuit verification method of the three-core power line plug wire is provided with a corresponding automatic verification control device, the automatic verification control device comprises a device body, a normally open relay, a matched power supply and a resistor, three paths of the three-core power line plug wire are respectively marked as a live wire, a zero wire and a ground wire, when the three-core power line plug wire is verified by the automatic verification control device, two ends of the live wire, two ends of the zero wire and two ends of the ground wire of the three-core power line plug wire are respectively correspondingly conducted with the positive pole and the negative pole of the power supply, the positive pole of the power supply is respectively connected with the corresponding ends of the live wire, the zero wire and the ground wire through resistors, the normally open relay is respectively connected between the negative pole of the power supply and the corresponding ends of the live wire, the zero wire and the ground wire, and the device body respectively collects the normally open relay, The circuit checking method comprises the following steps:
step 1, the device body sends out control signals to control the three normally open relays to be in a closed state, the device body respectively collects level signals between two ends of a live wire, between two ends of a zero wire and between two ends of a ground wire of the three-core power line plug wire,
if the level signals between the two ends of the live wire, between the two ends of the zero line and between the two ends of the ground wire of the three-core power line plug wire, which are respectively acquired by the device body, are changed from high level to low level, the step 2 is sequentially carried out;
if at least one of the level signals collected by the device body between the two ends of the live wire, the two ends of the zero wire and the two ends of the ground wire of the three-core power line plug wire is still a high level signal, the device body sends a control signal to control the three normally open relays to reset and send an alarm signal;
step 2, the device body sends out a control signal to control the normally open relay corresponding to the first three-core power line plug wire to be in a closed state, and the normally open relays corresponding to the other two three-core power line plug wires to be in a normally open state,
if the level signals between the two ends of the first three-core power line plug wire collected by the device body are changed from high level to low level, and the level signals between the two ends of the other two three-core power line plug wires are still high level, sequentially entering step 3;
if the level signals between the two ends of the first path of three-core power line plug wire collected by the device body are still in a high level and/or the level signals between the two ends of at least one path of three-core power line plug wire in the level signals between the two ends of the other two paths of three-core power line plug wires are changed from a high level to a low level, the device body sends out a control signal to control the three normally open relays to reset and send out an alarm signal;
step 3, the device body sends out a control signal to control the normally open relay corresponding to the second three-core power line plug wire to be in a closed state, and the normally open relays corresponding to the other two three-core power line plug wires to be in a normally open state,
if the level signals between the two ends of the second three-core power line plug wire collected by the device body are changed from high level to low level, and the level signals between the two ends of the other two three-core power line plug wires are still high level, sequentially entering step 4;
if the level signals between the two ends of the second path of the three-core power line plug wire collected by the device body are still in a high level, and/or the level signals between the two ends of at least one path of the three-core power line plug wires of the level signals between the two ends of the other two paths of the three-core power line plug wires are changed from a high level to a low level, the device body sends out a control signal to control the three normally open relays to reset and send out an alarm signal;
step 4, the device body sends out a control signal to control the normally open relay corresponding to the third three-core power line plug cord to be in a closed state, and the normally open relays corresponding to the other two three-core power line plug cords to be in a normally open state,
if the level signal between the two ends of the third three-core power line plug wire collected by the device body is changed from high level to low level, and the level signals between the two ends of the other two three-core power line plug wires are still high level, the device body sends out a qualified indicating signal, and the step 5 is sequentially carried out;
if the level signals between the two ends of the third three-core power line plug wire collected by the device body are still high level, and/or the level signals between the two ends of at least one of the other two three-core power line plug wires are changed from high level to low level, the device body sends out a control signal to control the three normally open relays to reset and send out an alarm signal;
step 5, the device body sends out a control signal to control the normally open relays corresponding to the three-core power line plug wires to be in a closed state,
if the level signals collected by the device body and between the two ends of the three-core power line plug wires are changed from low level to high level, the device body sends out control signals to control the three normally open relays to reset and stop sending out qualified indication signals.
Preferably, when the three-core power line plug wire is not validated by the validation automatic control device, the device body sends a starting standby indication signal;
-when said three-cord plug is verified by said verification automation device, said device body issues an interrupt standby indication signal.
Preferably, in step 1, if at least one of the level signals collected by the device body between the two ends of the live wire, the two ends of the zero wire and the two ends of the ground wire of the three-core power line plug wire is still at a high level, the delay module of the device body sends out a delay signal;
or, in step 2, if the level signal between the two ends of the first three-core power line plug wire collected by the device body is still at a high level, and/or the level signal between the two ends of at least one of the other two three-core power line plug wires is changed from a high level to a low level, the delay module of the device body sends a delay signal;
alternatively, the first and second electrodes may be,
in step 3, if the level signals between the two ends of the second path of three-core power line plug wire collected by the device body are still at a high level, and/or the level signals between the two ends of at least one path of three-core power line plug wire of the level signals between the two ends of the other two paths of three-core power line plug wires are changed from a high level to a low level, the delay module of the device body sends out a delay signal;
or, in step 4, if the level signal between the two ends of the third three-core power line plug wire collected by the device body is still at a high level, and/or the level signal between the two ends of the other two three-core power line plug wires at least has one level signal between the two ends of the three-core power line plug wire changed from a high level to a low level, the delay module of the device body sends a delay signal.
Preferably, the device body of the automatic validation control device is a single chip microcomputer.
The invention has the beneficial effects that: the invention has the advantages of simple operation, automatic detection, high detection efficiency and high detection accuracy, and avoids detection errors caused by human factors.
Drawings
The invention will be further described with reference to the accompanying drawings.
Fig. 1 is a functional block diagram of the circuit of the present invention.
Fig. 2 is a schematic diagram of a three-cord power cord plug.
The reference numbers in the figures mean: 1-power cord plug; 11-power line plug end socket; 111-L end plug; 112-an N-terminal plug; 113-ground plug; 12-power line jack terminal socket; 121-L end jack; 122-N terminal jack; 123-ground jack.
Detailed Description
Referring to fig. 1-2: the invention discloses a circuit verification method of a three-core power line plug wire, which is provided with a corresponding automatic verification control device and comprises a device body, a normally open relay, a matched power supply and a matched resistor, wherein three paths of the three-core power line plug wire 1 (comprising a power line plug end socket 11, a power line jack end socket 12 and a connecting part between the three paths) are respectively marked as a live wire (a crimping circuit between an L-end plug 111 and an L-end jack 121), a zero wire (a crimping circuit between an N-end plug 112 and an N-end jack 122) and a ground wire (a crimping circuit between a ground end plug 113 and a ground end jack 123). The three power supplies are DC5V, the resistors are selected according to actual verification requirements, and verification is met.
When the three-core power cord plug wire 1 is not verified by the automatic verification control device, the device body sends a standby starting indication signal;
when the three-core power cord plug wire 1 is verified by the verification automatic control device, the device body sends an interrupt standby indication signal.
When the three-core power line plug wire 1 is checked by the automatic checking control device, two ends of a live wire, two ends of a zero wire and two ends of a ground wire of the three-core power line plug wire 1 are respectively and correspondingly conducted with the positive pole and the negative pole of the power supply, resistors are respectively connected between the positive pole of the power supply and the corresponding ends of the live wire, the zero wire and the ground wire (one end of the resistor connected with the positive pole of the power supply), a normally open relay is respectively connected between the negative pole of the power supply and the corresponding ends of the live wire, the zero wire and the ground wire (one end of the normally open relay connected with the negative pole of the power supply), the device body respectively collects level signals between two ends of the live wire, between two ends of the zero wire and between two ends of the ground wire of the three-core power line plug wire 1,
the circuit verification method comprises the following sequential steps:
step 1, the device body sends out a control signal to control the three normally open relays to be in a closed state, the device body respectively collects level signals between two ends of a live wire, between two ends of a zero wire and between two ends of a ground wire of the three-core power line plug wire 1,
if the level signals between the two ends of the live wire of the three-core power line plug wire 1 (which refer to any two or more points on the crimping circuit between the L-end plug 111 and the L-end jack 121, preferably, two points of the L-end plug 111 and the L-end jack 121), and between the two ends of the zero wire (which refer to any two or more points on the crimping circuit between the N-end plug 112 and the N-end jack 122, preferably, two points of the N-end plug 112 and the N-end jack 122), and between the two ends of the ground wire (which refer to any two or more points on the crimping circuit between the ground plug 113 and the ground jack 123, preferably, two points of the ground plug 113 and the ground jack 123) which are respectively acquired by the device body all change from high level to low level, the step 2 is sequentially performed (it is determined that there is no three-way disconnection in the three-core power line plug wire 1);
if at least one of the level signals collected by the device body between the two ends of the live wire, the two ends of the zero wire and the two ends of the ground wire of the three-core power line plug wire 1 is still a high level signal, the device body sends a control signal to control the three normally open relays to reset (the normally open relays are in a normally open state, and all the level signals collected at the moment are high levels, the same below) and send an alarm signal;
step 2, the device body sends out a control signal to control the normally open relay corresponding to the first three-core power line plug wire 1 to be in a closed state, and the normally open relays corresponding to the other two three-core power line plug wires 1 to be in a normally open state,
if the level signals between the two ends of the first three-core power line plug wire 1 collected by the device body are changed from high level to low level, and the level signals between the two ends of the other two three-core power line plug wires 1 are still high level, sequentially entering step 3;
if the level signals between the two ends of the first three-core power line plug wire 1 collected by the device body are still at a high level, and/or the level signals between the two ends of at least one of the other two three-core power line plug wires 1 are changed from the high level to a low level, the device body sends out a control signal to control the three normally open relays to reset and send out an alarm signal;
step 3, the device body sends out a control signal to control the normally open relay corresponding to the second three-core power line plug wire 1 to be in a closed state, and the normally open relays corresponding to the other two three-core power line plug wires 1 to be in a normally open state,
if the level signals between the two ends of the second three-core power line plug wire 1 collected by the device body are changed from high level to low level, and the level signals between the two ends of the other two three-core power line plug wires 1 are still high level, sequentially entering step 4;
if the level signals between the two ends of the second three-core power line plug wire 1 collected by the device body are still in a high level and/or the level signals between the two ends of at least one of the other two three-core power line plug wires 1 are changed from the high level to the low level, the device body sends out a control signal to control the three normally open relays to reset and send out an alarm signal;
step 4, the device body sends out a control signal to control the normally open relay corresponding to the third three-core power line plug wire 1 to be in a closed state, and the normally open relays corresponding to the other two three-core power line plug wires 1 to be in a normally open state,
if the level signals between the two ends of the third three-core power line plug wire 1 collected by the device body are changed from high level to low level, and the level signals between the two ends of the other two three-core power line plug wires 1 are still high level, the device body sends out a qualified indicating signal (it is determined that the three-core power line plug wires 1 are in one-to-one correspondence crimping), and the steps sequentially enter step 5;
if the level signals between the two ends of the third three-core power line plug wire 1 collected by the device body are still at a high level, and/or the level signals between the two ends of the other two three-core power line plug wires 1 are at least level signals between the two ends of the three-core power line plug wire 1 which are changed from a high level to a low level, the device body sends out a control signal to control the three normally-open relays to reset and send out an alarm signal;
step 5, the device body sends out a control signal to control the normally open relays corresponding to the three-core power line plug wires to be in a closed state,
if the level signals collected by the device body and between the two ends of the three-core power line plug wires are changed from low level to high level, the device body sends out control signals to control the three normally open relays to reset and stop sending out qualified indication signals. At this time, it is stated that the three-core power line plug wire is verified, and the next three-core power line plug wire is waited for to be verified, and the process is repeated.
Preferably, in step 1, if at least one of the level signals collected by the device body between the two ends of the live wire, the two ends of the zero wire and the two ends of the ground wire of the three-core power line plug wire 1 is still at a high level, the delay module of the device body sends out a delay signal;
or, in step 2, if the level signal between the two ends of the first three-core power line plug wire 1 collected by the device body is still at a high level, and/or the level signal between the two ends of the other two three-core power line plug wires 1 is at least one level signal between the two ends of the three-core power line plug wire 1, the level signal is changed from a high level to a low level, the delay module of the device body sends a delay signal;
alternatively, the first and second electrodes may be,
in step 3, if the level signals between the two ends of the second three-core power line plug wire 1 collected by the device body are still at a high level, and/or at least one of the level signals between the two ends of the other two three-core power line plug wires 1 is changed from a high level to a low level, the delay module of the device body sends out a delay signal;
or, in step 4, if the level signal between the two ends of the third three-core power line plug 1 collected by the device body is still at a high level, and/or the level signal between the two ends of the other two three-core power line plug 1 has at least one level signal between the two ends of the three-core power line plug 1 changed from a high level to a low level, the delay module of the device body sends a delay signal.
The device body of the automatic validation control device is a single chip microcomputer. Preferably, the single chip microcomputer is of the type PIC16F 877. The model of the normally open relay is 3RH 11.
In addition, the K1, the K2 and the K3 are normally open relays; RB1, RB2, RB3, RB5, RB6, RD1, RD2 and RD4 are pins of the single-chip microcomputer, wherein the three groups of RB1 and RD1, RB2 and RD2 and RB3 and RD4 are used for collecting corresponding level signals; RB5 is connected with an alarm device and receives an alarm signal; the RB6 is connected with a qualified indicator light and receives a qualified indicator signal; an alarm module and a delay module are embedded in the single chip microcomputer.
The above detailed description is merely illustrative of the present invention and is not to be construed as limiting thereof. Although the present invention has been described in detail with reference to the specific embodiments thereof, it will be understood by those skilled in the art that: the above-mentioned specific technical solutions can still be modified, or some technical features thereof can be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the present invention in its essence.