CN110287628A - A kind of emulation mode of Nano quantum cellular automata circuit - Google Patents
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Abstract
The invention discloses a kind of emulation mode of Nano quantum cellular automata circuit, step includes: 1 according to the quantum cellular layout of Nano quantum cellular automata circuit, and cellulars all in circuit are grouped and are numbered by clock area；2 according to the quantum cellular in circuit each group, in neighbour's quantum cellular of addition adjacent packets, so that Nano quantum cellular automata circuit is divided into j sub-circuit；Quantum cellular position carries out parameter setting in 3 pairs of each sub-circuits, according to the weight matrix W responded between preset M × M type quantum cellular, synchronizes and carries out simulation calculation to each sub-circuit, obtain the truth table of all sub-circuits；4 according to the inputs of circuit and combine the truth table of sub-circuit, the output of you can get it Nano quantum cellular automata circuit.Simple calculating, which is used only, in the present invention can be obtained output, and without solving a large amount of Quantum Equation, computation complexity is substantially reduced.
Description
Technical field
The invention belongs to micro-nano device Circuits and Systems field, be related to a kind of Nano quantum cellular automata circuit
Emulation mode.
Background technique
Traditional integrated circuit is just undergoing one from microelectronic age to the transformation in nanoelectronic epoch, with cmos device
Feature size downsizing within 20 nanometers, Conventional CMOS technology is up to its physics limit quickly.Since nano-scale causes
The problem of, it is also difficult to solve by existing technology.So reducing power consumption in following IC design, improve
Integrated level, it is necessary to study the emerging device of new nanoscale.The emerging nanometer electricity of Conventional CMOS technology can be substituted as one kind
The features such as sub- device, Nano quantum cellular automata technology have size small, and integrated level is high, and the speed of service is fast, super low-power consumption, because
This is listed in a kind of revolutionary electronic device that can substitute Conventional CMOS technology.
Come since Nano quantum cellular automata concept is put forward for the first time, lot of domestic and international scholar, in experimental and theoretical study
There is huge progress.Nano quantum cellular automata technology provides a kind of revolutionary method to utilize device and device
Between interaction to carry out information calculating and transmitting, information is indicated and handled using voltage and circuit with Conventional CMOS technology
Method have difference substantially.Fundamentally avoid the possibility of high power consumption.
Up to the present, in terms of the simulation calculation of small-scale Nano quantum cellular automata circuit, occur it is some at
Fruit.Such as binary states approximation method, coherency states vector method, and have been developed the small-scale Nano quantum cellular automata of analysis
The emulation mode tool of circuit, unfortunately current emulation mode is largely based in cellular in Nano quantum cellular automata
In the quantum mechanics to interact between electronicsThe solution of equation needs to solve a large amount of
Equation, so that calculating complexity in simulation process greatly, another drawback is namely based on two mentioned kind emulation side above
Method can hardly correctly obtain simulation result when emulating to larger Nano quantum cellular automata circuit.
Summary of the invention
The present invention is that in place of overcoming the shortcomings of the prior art, it is automatic to provide a kind of Nano quantum cellular being simple and efficient
The emulation mode on electromechanical road is applicable not only to the emulation of small-scale Nano quantum cellular automata circuit, is equally applicable to larger
The emulation of the Nano quantum cellular automata circuit of scale, and Nano quantum can be obtained without solving a large amount of Quantum Equation
The output of cellular automata circuit, to substantially reduce computation complexity.
The present invention to achieve the above object of the invention, adopts the following technical scheme that
A kind of the characteristics of emulation mode of Nano quantum cellular automata circuit of the present invention, includes the following steps:
Step 1, according to the cellular layout of Nano quantum cellular automata circuit, to the Nano quantum cellular automata
All cellulars are grouped and are numbered by clock area in circuit, obtain the J group cellular of lower 4 clock areas of N number of clock,
Wherein, the jth group cellular of i-th of clock area is denoted as under any n-th of clockI ∈ { 0,1,2,3 }, n ∈
[1, N], j ∈ [1, J]；
Step 2, to the jth group cellular of i-th of clock area under n-th of clockAdd i+1 clock area
Neighbour's cellular in domain, to obtain j-th of sub-circuit of i-th of clock area under n-th of clock
Step 3 defines j-th of sub-circuitIn all quantum cellulars functional attributes, comprising: have input quantum cellular,
Export quantum cellular and regular quantum cellular；
As n=1, when using the input cellular of Nano quantum cellular automata circuit as i-th under n-th of clock
J-th of sub-circuit in clock regionIn input cellular；By j-th of son electricity of i-th of clock area under n-th of clock
RoadIn j-th sub-circuit of the added neighbour's cellular as i-th of clock area under n-th of clockIn it is defeated
Cellular out；By j-th of sub-circuitIn remaining cellular as conventional cellular；
As n=N, by j-th of sub-circuit of i-th of clock area under n-th of clockIn added neighbour
J-th sub-circuit of the cellular as i-th of clock area under n-th of clockInput cellular；By Nano quantum cellular
J-th sub-circuit of the output cellular of automatic machine circuit as i-th of clock area under n-th of clockIn output
Cellular；By j-th of sub-circuitIn remaining cellular be conventional cellular；
When n ∈ (1, N), using neighbour's cellular of lower (i-1)-th clock area of n-th of clock as n-th of timing
J-th of sub-circuit of i-th of clock area under clockIn input cellular；By i-th of clock area under n-th of clock
J-th of sub-circuit in domainIn j-th son of the added neighbour's cellular as i-th clock area under n-th of clock
CircuitOutput cellular；By j-th of sub-circuitIn remaining cellular be conventional cellular；
Step 4 defines j-th of sub-circuitIn the location parameter of each cellular be to be characterized with line number x and row number y, i.e.,
Any j-th of sub-circuitIn the location parameter of s-th of cellular be denoted as
Step 5, j-th of sub-circuit for calculating i-th of clock area under n-th of clockIn between each cellular
Euclidean distance and as the weight between corresponding two cellulars, to obtain j-th of sub-circuitWeight matrix
According to j-th of sub-circuitWeight matrixAnd j-th of sub-circuitIn input cellular
With output cellular to j-th of sub-circuitSimulation calculation is carried out, obtains j-th of sub-circuitMiddle input cellular and output
The truth table of cellular；
Step 6, according to the input value of Nano quantum cellular automata circuit and the truth table of all sub-circuits, received
The output valve of rice quantum cellular automation circuit, thus according to the input value and output of the Nano quantum cellular automata circuit
It is worth the logic function of the Nano quantum cellular automata circuit.
Compared with the prior art, the beneficial effects of the present invention are embodied in:
1, emulation mode of the present invention is that one kind is modeled and imitated to quantum cellular automation circuit based on cellular grade level
Very, compared with existing based on the interaction between electronics in cellular, without solving quantum mechanics in carrying out simulation process
InEquation need to only use simple calculations to can be obtained the output polarization of Nano quantum cellular automata circuit,
Calculating process is simplified, computation complexity substantially reduces, and has many advantages, such as general, efficient.
2, quantum cellular automation circuit is first divided into several multiple sub-circuits by emulation mode of the present invention, then several
Sub-circuit is synchronous to carry out simulation calculation, and therefore, this emulation mode can be adapted for large-scale simulation quantum cellular automation circuit,
Output polarization is obtained in the shortest time；
3, emulation mode of the present invention flexibly sets user institute by the size of M value in M × M type sub-circuit according to requiring
The simulation accuracy needed, to meet the output accuracy requirement of different user；
4, the present invention is a kind of general, flexible, efficient circuit emulation method, is keeping the simulator based on physics
Acceptable accuracy while, can in cellular grade Fast simulation Nano quantum cellular automata circuit, be Nano quantum cellular
Functional verification provides a preferable method in automatic machine circuit design process.
Detailed description of the invention
Fig. 1 is the flow diagram of circuit emulation method of the invention；
Fig. 2 is the 8 kinds of cellular schematic diagrames used in nanoscale quantum dot cellular automata circuit of the present invention；
Fig. 3 is the logic diagram that the present invention one has 2 inputs and 1 output quantum cellular automation circuit；
Fig. 4 is the quantum cellular layout of quantum cellular automation circuit used in the present invention；
Fig. 5 is the quantum cellular layout grouping schematic diagram of quantum cellular automation circuit of the present invention；
Fig. 6 is number result after the quantum cellular of quantum cellular automation circuit of the present invention is grouped；
Fig. 7 is that the quantum cellular of quantum cellular automation circuit of the present invention is grouped all sub-circuits to be formed；
Fig. 8 is the attributed graph that the present invention defines all quantum cellulars in sub-circuit；
Fig. 9 is number figure of the present invention to the quantum cellular in sub-circuit；
Figure 10 is M × M type sub-circuit cellular number schematic diagram in the present invention；
Figure 11 is the weight matrix figure of mutual response between each quantum cellular in sub-circuit of the present invention；
Figure 12 is that emulation obtains the simulation result diagram of each sub-circuit in the present invention；
Figure 13 is the relational graph in the present invention between the input and output of all sub-circuits；
Figure 14 is the result figure that example circuit is obtained by emulation in the present invention.
Specific embodiment
Example with reference, detailed detailed description of the present invention circuit emulation method will be passed through below.
This example considers have the Nano quantum cellular automata circuit of 2 inputs and 1 output to carry out simulation calculation to one,
Whole flow process is as shown in Figure 1；The quantum cellular of 8 seed types generally used in quantum cellular automation circuit, as shown in Fig. 2,
Respectively polarization value be 1 quantum cellular, polarization value be -1 quantum cellular, (quantum cellular is as defeated for input quantum cellular
Enter to hold quantum cellular), output quantum cellular (quantum cellular is as output end quantum cellular), clock0 quantum cellular (should
Quantum cellular is in 0 region of clock), clock1 quantum cellular (quantum cellular is in 1 region of clock), clock2 quantum cellular
(quantum cellular is in 2 region of clock) and clock3 quantum cellular (quantum cellular is in 3 region of clock)；To be emulated receives
The logic chart of rice quantum cellular automation circuit (abbreviation circuit) is as shown in Figure 3；Quantum cellular layout such as Fig. 4 institute of the circuit
Show；Specifically, a kind of emulation mode of Nano quantum cellular automata circuit includes the following steps:
1) according to the cellular layout of Nano quantum cellular automata circuit, to institute in Nano quantum cellular automata circuit
There is cellular to be grouped and numbered by clock area, obtain the J group cellular of lower 4 clock areas of N number of clock, wherein appoints
The jth group cellular of i-th of clock area under n-th of clock of anticipating is denoted asI ∈ { 0,1,2,3 }, n ∈ [1, N], j ∈
[1,J]；
In specific implementation, according to the quantum cellular layout of Nano quantum cellular automata circuit, as shown in figure 4, to receiving
All quantum cellulars are grouped and are numbered by clock area in rice quantum cellular automation circuit, can be by the amount in the circuit
Sub- cellular is divided into 5 groups, as shown in Figure 5.5 groups of quantum cellulars of lower 4 clock areas of 3 clocks are obtained, as shown in fig. 6,
The quantum cellular grouping of quantum cellular automation circuit is numbered, wherein the 0th clock area there are 2 groups of amounts under the 1st timing
Sub- cellular, two groups of quantum cellulars are denoted as respectivelyWithThere are 2 groups of quantum cellulars in the 1st clock area under 2nd timing,
Two groups of quantum cellulars are denoted as respectivelyWithThere is 1 group of quantum cellular in the 2nd clock area under 3rd timing, the group amount
Sub- cellular is denoted as
2) to the jth group cellular of i-th of clock area under n-th of clockIt adds in i+1 clock area
Neighbour's cellular, to obtain j-th of sub-circuit of i-th of clock area under n-th of clock
It obtains 5 groups of quantum cellulars to grouping to be handled to obtain 5 sub-circuits, as shown in fig. 7, when the 0th under the 1st timing
Clock regionGroup quantum cellular adds neighbour's cellular of the 1st clock area (asA quantum cellular in group andA quantum cellular in group), obtained sub-circuit is denoted as0th clock area under 1st timingGroup amount
Sub- cellular adds neighbour's cellular of the 1st clock area (asA quantum cellular in group andAn amount in group
Sub- cellular), obtained sub-circuit is denoted as1st clock area under 2nd timingWhen group quantum cellular addition the 2nd
Neighbour's cellular in clock region is (asA quantum cellular in group), obtained sub-circuit is denoted asUnder 2nd timing
1st clock areaGroup quantum cellular adds neighbour's cellular of the 2nd clock area (asA quantum in group
Cellular), obtained sub-circuit is denoted as2nd clock area under 3rd timingGroup quantum cellular is last group,
It does not need then to process, directly willThe sub-circuit that group quantum cellular is constituted is denoted as
3) j-th of sub-circuit is definedIn all quantum cellulars functional attributes, comprising: input quantum cellular, output quantity
Sub- cellular and regular quantum cellular；
As n=1, when using the input cellular of Nano quantum cellular automata circuit as i-th under n-th of clock
J-th of sub-circuit in clock regionIn input cellular；By j-th of son electricity of i-th of clock area under n-th of clock
RoadIn j-th sub-circuit of the added neighbour's cellular as i-th of clock area under n-th of clockIn it is defeated
Cellular out；By j-th of sub-circuitIn remaining cellular as conventional cellular；
As n=N, by j-th of sub-circuit of i-th of clock area under n-th of clockIn added neighbour
J-th sub-circuit of the cellular as i-th of clock area under n-th of clockInput cellular；By Nano quantum cellular
J-th sub-circuit of the output cellular of automatic machine circuit as i-th of clock area under n-th of clockIn output
Cellular；By j-th of sub-circuitIn remaining cellular be conventional cellular；
When n ∈ (1, N), using neighbour's cellular of lower (i-1)-th clock area of n-th of clock as n-th of timing
J-th of sub-circuit of i-th of clock area under clockIn input cellular；By i-th of clock area under n-th of clock
J-th of sub-circuit in domainIn j-th son of the added neighbour's cellular as i-th clock area under n-th of clock
CircuitOutput cellular；By j-th of sub-circuitIn remaining cellular be conventional cellular；
In specific implementation, as shown in figure 8, for sub-circuitFor, the input member of Nano quantum cellular automata circuit
Born of the same parents a is sub-circuitInput quantum cellular, add the 1st clock area neighbour's cellular (asOne in group
Quantum cellular andA quantum cellular in group) it is sub-circuitOutput quantum cellular, be denoted as f respectively11-1With
f11-2, sub-circuitIn remaining quantum cellular be regular quantum cellular；
For sub-circuitFor, the input cellular b of Nano quantum cellular automata circuit is sub-circuitIt is defeated
Enter quantum cellular, adds neighbour's cellular of the 1st clock area (asA quantum cellular in group andIn group
One quantum cellular) it is sub-circuitOutput quantum cellular, be denoted as f respectively12-1And f12-2, sub-circuitIn its surplus
Sub- cellular is regular quantum cellular；
For sub-circuitFor, by sub-circuitIn neighbour's member with the 0th clock area under the 1st clock
Born of the same parents are as sub-circuitIn input quantum cellular, be denoted as i respectively21-1And i21-2；By the 2nd clock under the 3rd clock
The sub-circuit in regionIn added neighbour's cellular conductOutput quantum cellular, be denoted as f21-1；By sub-circuitIn
Remaining quantum cellular be regular quantum cellular；
Similarly, for sub-circuitFor, by sub-circuitIn with the 0th clock area under the 1st clock
Neighbour's cellular is as sub-circuitIn input quantum cellular, be denoted as i respectively22-1And i22-2；It will be the 2nd under the 3rd clock
The sub-circuit of a clock areaIn added neighbour's cellular conductOutput quantum cellular, be denoted as f22-1；By sub- electricity
RoadIn remaining quantum cellular be regular quantum cellular；
For sub-circuitFor, by sub-circuitIn neighbour's member with the 1st clock area under the 2nd clock
Born of the same parents are as sub-circuitIn input quantum cellular, be denoted as i respectively31-1And i31-2；By Nano quantum cellular automata circuit
Cellular is exported as sub-circuitIn output cellular, be denoted as f；By sub-circuitIn remaining quantum cellular be regular quantum
Cellular.
4) j-th of sub-circuit is definedIn the location parameter of each cellular be to be characterized with line number x and row number y, i.e., arbitrarily
J-th of sub-circuitIn the location parameter of s-th of cellular be denoted as
As shown in figure 9, for sub-circuitThe position of middle cellular, input quantum cellular a is denoted as (1,1), output quantum member
Born of the same parents f11-1And f11-2Position be denoted as (3,1), (3,5), sub-circuit respectivelyIn remaining quantum cellular position be denoted as respectively (1,
2), (1,3), (1,4), (2,1) and (2,5)；
For sub-circuitThe position of middle quantum cellular, input quantum cellular b is denoted as (2,1), exports quantum cellular f12-1
And f12-2Position be denoted as (1,1), (1,5), sub-circuit respectivelyIn remaining quantum cellular position be denoted as respectively (2,2), (2,
And (2,4) 3)；
For sub-circuitMiddle quantum cellular, by sub-circuitMiddle input quantum cellular i21-1And i21-2Position difference
It is denoted as (1,2) and (3,2)；By sub-circuitOutput quantum cellular f21-1It is denoted as (2,3)；Sub-circuitIn remaining quantum
Cellular position is denoted as (2,1) and (2,2) respectively；
For sub-circuitMiddle quantum cellular, by sub-circuitMiddle input quantum cellular i22-1And i22-2Position difference
It is denoted as (1,2) and (3,2)；By sub-circuitOutput quantum cellular f21-1It is denoted as (2,1)；Sub-circuitIn remaining quantum
Cellular position is denoted as (2,2) and (2,3) respectively；
For sub-circuitMiddle quantum cellular, by sub-circuitMiddle input quantum cellular i31-1And i31-2Position difference
It is denoted as (2,1) and (2,3)；By sub-circuitIn the position of output cellular f be denoted as (6,2)；Sub-circuitIn its surplus
Sub- cellular position is denoted as (1,2), (2,2), (3,2) and (5,2) respectively；
5) j-th of sub-circuit of i-th of clock area under n-th of clock is calculatedIn Europe between each cellular
Formula distance and as the weight between corresponding two cellulars, to obtain j-th of sub-circuitWeight matrix
According to j-th of sub-circuitWeight matrixAnd j-th of sub-circuitIn input cellular and output member
Born of the same parents are to j-th of sub-circuitSimulation calculation is carried out, obtains j-th of sub-circuitMiddle input cellular and the true value for exporting cellular
Table；
It calculates in M × M type quantum cellular alignment placement, the weight to interact between any two cellular such as Figure 10 institute
Show, the present invention is using the Euclidean distance of any two quantum cellular as the weight to interact between two quantum cellulars.?
Weight matrix W to M × M type is as shown in figure 11；
According to the 5 of Nano quantum cellular automata sub-circuitsIn all quantum member
The position of born of the same parents and sub-circuit weight matrix carry out simulation calculation, you can get it 5 sub-circuitsInput quantum cellular and export quantum cellular truth table it is as shown in figure 12；
6) according to the input value of Nano quantum cellular automata circuit and the truth table of all sub-circuits, nanometer amount is obtained
The output valve of sub- cellular automata circuit, to must be received and paid out according to the input value of Nano quantum cellular automata circuit and output valve
The logic function of rice quantum cellular automation circuit.
According to the input value and sub-circuit of Nano quantum cellular automata circuit
Input quantum cellular and export quantum cellular truth table and sub-circuitInput quantity
The relationship of sub- cellular and output quantum cellular is as shown in figure 13, it is known that obtains the input and output of Nano quantum cellular automata circuit
Truth table is as shown in figure 14, to obtain Nano quantum member according to the input value of Nano quantum cellular automata circuit and output valve
The logic function of cellular automaton circuit.
The present invention mainly applies in the circuit function Qualify Phase of Nano quantum cellular automata circuit design process, is receiving
Rice quantum cellular automation circuit design provides a kind of simple, feasible, general, efficient circuit emulation method, is receiving
In rice quantum cellular automation electronic circuit design automation technical process, necessary verifying means are provided.
Claims (1)
1. a kind of emulation mode of Nano quantum cellular automata circuit, feature include the following steps:
Step 1, according to the cellular layout of Nano quantum cellular automata circuit, to the Nano quantum cellular automata circuit
In all cellulars be grouped and numbered by clock area, obtain the J group cellular of lower 4 clock areas of N number of clock,
In, the jth group cellular of i-th of clock area is denoted as under any n-th of clockI ∈ { 0,1,2,3 }, n ∈ [1,
N], j ∈ [1, J]；
Step 2, to the jth group cellular of i-th of clock area under n-th of clockIt adds in i+1 clock area
Neighbour's cellular, to obtain j-th of sub-circuit of i-th of clock area under n-th of clock
Step 3 defines j-th of sub-circuitIn all quantum cellulars functional attributes, comprising: have input quantum cellular, output
Quantum cellular and regular quantum cellular；
As n=1, using the input cellular of Nano quantum cellular automata circuit as i-th of clock area under n-th of clock
J-th of sub-circuit in domainIn input cellular；By j-th of sub-circuit of i-th of clock area under n-th of clock
In j-th sub-circuit of the added neighbour's cellular as i-th of clock area under n-th of clockIn output member
Born of the same parents；By j-th of sub-circuitIn remaining cellular as conventional cellular；
As n=N, by j-th of sub-circuit of i-th of clock area under n-th of clockIn added neighbour's cellular
J-th of sub-circuit as i-th of clock area under n-th of clockInput cellular；Nano quantum cellular is automatic
J-th sub-circuit of the output cellular on electromechanical road as i-th of clock area under n-th of clockIn output cellular；
By j-th of sub-circuitIn remaining cellular be conventional cellular；
When n ∈ (1, N), using neighbour's cellular of lower (i-1)-th clock area of n-th of clock as n-th of clock
J-th of sub-circuit of lower i-th of clock areaIn input cellular；By i-th clock area under n-th of clock
J-th of sub-circuitIn j-th sub-circuit of the added neighbour's cellular as i-th of clock area under n-th of clockOutput cellular；By j-th of sub-circuitIn remaining cellular be conventional cellular；
Step 4 defines j-th of sub-circuitIn the location parameter of each cellular be to be characterized with line number x and row number y, i.e., arbitrarily
J-th of sub-circuitIn the location parameter of s-th of cellular be denoted as
Step 5, j-th of sub-circuit for calculating i-th of clock area under n-th of clockIn Europe between each cellular
Formula distance and as the weight between corresponding two cellulars, to obtain j-th of sub-circuitWeight matrix
According to j-th of sub-circuitWeight matrixAnd j-th of sub-circuitIn input cellular and defeated
Cellular is to j-th of sub-circuit outSimulation calculation is carried out, obtains j-th of sub-circuitMiddle input cellular and output cellular
Truth table；
Step 6, according to the input value of Nano quantum cellular automata circuit and the truth table of all sub-circuits, obtain nanometer amount
The output valve of sub- cellular automata circuit, to be obtained according to the input value of the Nano quantum cellular automata circuit and output valve
The logic function of the Nano quantum cellular automata circuit out.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111221497A (en) * | 2020-01-10 | 2020-06-02 | 宁波大学 | Quantum cellular automata decimal full adder |
| CN117391007A (en) * | 2023-10-23 | 2024-01-12 | 上海合见工业软件集团有限公司 | Method for acquiring truth table of simulation node, electronic equipment and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1866464A (en) * | 2005-05-16 | 2006-11-22 | 中国科学院半导体研究所 | Mirror charge effect quantum cellular automation making method |
| US7880496B1 (en) * | 2009-02-09 | 2011-02-01 | University Of South Florida | Conservative logic gate for design of quantum dot cellular automata circuits |
| CN104407835A (en) * | 2014-10-11 | 2015-03-11 | 南京航空航天大学 | Three-dimensional quantum cellular automata adder |
| CN109522671A (en) * | 2018-11-30 | 2019-03-26 | 合肥工业大学 | Two-dimentional timing topology and its design method for Nano quantum cellular automata circuit |
-
2019
- 2019-07-01 CN CN201910585064.5A patent/CN110287628B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1866464A (en) * | 2005-05-16 | 2006-11-22 | 中国科学院半导体研究所 | Mirror charge effect quantum cellular automation making method |
| US7880496B1 (en) * | 2009-02-09 | 2011-02-01 | University Of South Florida | Conservative logic gate for design of quantum dot cellular automata circuits |
| CN104407835A (en) * | 2014-10-11 | 2015-03-11 | 南京航空航天大学 | Three-dimensional quantum cellular automata adder |
| CN109522671A (en) * | 2018-11-30 | 2019-03-26 | 合肥工业大学 | Two-dimentional timing topology and its design method for Nano quantum cellular automata circuit |
Non-Patent Citations (1)
| Title |
|---|
| 杨晓阔等: "量子元胞自动机器件和电路的研究进展", 《微纳电子技术》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111221497A (en) * | 2020-01-10 | 2020-06-02 | 宁波大学 | Quantum cellular automata decimal full adder |
| CN111221497B (en) * | 2020-01-10 | 2022-04-22 | 宁波大学 | Quantum cellular automata decimal full adder |
| CN117391007A (en) * | 2023-10-23 | 2024-01-12 | 上海合见工业软件集团有限公司 | Method for acquiring truth table of simulation node, electronic equipment and storage medium |
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