CN111221497A - Quantum cellular automata decimal full adder - Google Patents

Quantum cellular automata decimal full adder Download PDF

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CN111221497A
CN111221497A CN202010026412.8A CN202010026412A CN111221497A CN 111221497 A CN111221497 A CN 111221497A CN 202010026412 A CN202010026412 A CN 202010026412A CN 111221497 A CN111221497 A CN 111221497A
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full adder
decimal
exclusive
circuit layout
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CN111221497B (en
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储著飞
李泽强
夏银水
王伦耀
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Ningbo University
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/4925—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena

Abstract

The invention discloses a quantum cellular automata decimal full adder, which optimizes the number of logic nodes and the logic depth required by a QCA decimal full adder by combining an XOR logic operator with stronger expression capability and an advanced full adder carry structure on the premise of not changing the logic function of a circuit, thereby optimizing the area and the delay of a one-bit and multi-bit QCA decimal full adder circuit. Compared with a full adder with optimal performance in the prior art, the decimal full adder of the quantum cellular automata has excellent performance, is obviously improved in delay and area, has more obvious optimization effect particularly in an 8-bit decimal full adder of the quantum cellular automata, and has the delay and area improvements of 27.6 percent and 53.4 percent respectively. The invention greatly reduces the circuit cost and enriches the circuit research method in the circuit design. The invention provides a new research idea for the design of an arithmetic circuit based on majority logic and exclusive-OR logic, and has strong practical significance for the development of circuit design.

Description

Quantum cellular automata decimal full adder
Technical Field
The invention relates to the technical field of circuit design of quantum cellular automata, in particular to a decimal full adder of a quantum cellular automata.
Background
In integrated circuits, Complementary Metal Oxide (CMOS) is approaching its physical limits, with consequent quantum effects and heat dissipation and power consumption problems. However, it is difficult to fundamentally solve these problems by the existing techniques and processes. Therefore, in order to further increase the integration density of integrated circuits and shrink the feature size of the circuits, many new nanocircuit devices are produced. As one of the emerging nano devices, Quantum-dot cellular automata (QCA) has the characteristics of high integration level, low power consumption and high operation speed, and is considered as one of candidates for replacing the conventional CMOS device. The QCA utilizes coulomb force between cells to perform calculation and information transmission, and compared with a traditional CMOS mode which depends on voltage and current to transmit information, the non-current working mode of the QCA circuit realizes low energy consumption. Meanwhile, the transmission line and the logic gate of the QCA circuit are both composed of QCA cells, so that calculation and information transmission in the circuit are simultaneous, and a foundation is laid for low time delay of the QCA circuit.
Full adders play a crucial role in many arithmetic circuits. Especially for circuits requiring a large number of full adders, its efficiency almost determines the operating efficiency of the whole circuit. Binary coded decimal full adders are widely used in the fields of banking, computer industry, internet industry and the like. Therefore, the performance of the decimal full adder is crucial. The QCA circuit with the characteristics of high integration level, low power consumption and high operation speed provides possibility for the optimization of the binary coded decimal adder. In the conventional QCA circuit, most logic gates and inverters are used for design, and although complete logic functions can be realized, a logic expression is not compact enough, and the area and the delay are relatively high. The invention provides a decimal full adder based on an exclusive-OR logic gate and a plurality of logic gates, which optimizes the number of logic nodes and the logic depth required by a QCA decimal full adder by combining an exclusive-OR logic operator with stronger expression capability and an advanced full adder carry structure on the premise of not changing the logic function of a circuit so as to optimize the area and the delay of a one-bit and multi-bit QCA decimal full adder circuit.
Disclosure of Invention
The invention aims to solve the technical problem of designing a quantum cellular automaton decimal full adder which has excellent performance and obviously improves the delay and the area aiming at the defects of the prior art.
The technical scheme adopted by the invention for solving the technical problems is as follows: a quantum cellular automata decimal full adder is distributed on a circuit layout formed by three circuit layers, comprises a first four-bit full adder and a full adder correction circuit, and comprises nine input ends and five output ends; one of the input ends is decimal carry input, and the other eight input ends are divided into two groups, wherein each group comprises four input ends, and each group represents a decimal number from zero to nine; one of the outputs being decimal carry output, i.e. carry output dC of full decimal adder of quantum cellular automatonoutThe other four output ends jointly represent a decimal number from zero to nine, namely the sum output of the decimal full adder of the quantum cellular automaton; the first four-bit full adder comprises four majority logic gates and four exclusive-or logic gates, the full adder correction circuit comprises a decimal carry generation circuit and a second four-bit full adder, the decimal carry generation circuit consists of six majority logic gates, and the second four-bit full adder comprises three majority logic gates and four exclusive-or logic gates;
the four XOR logic gates contained in the first four-bit full adder are distributed on the first layer of the circuit layout, most of the four logic gates contained in the first four-bit full adder are distributed on the third layer of the circuit layout, the eight logic nodes form the first four-bit full adder, and the expression of the first four-bit full adder is as follows:
Figure BDA0002362634160000021
Figure BDA0002362634160000022
Figure BDA0002362634160000023
Figure BDA0002362634160000024
wherein the content of the first and second substances,
Figure BDA0002362634160000025
represents an exclusive or logic gate, "M ()" represents a majority logic gate; dA3、dA2、dA1、dA0、dB3、dB2、dB1、dB0Four binary digits of the decimal numbers A and B, respectively; bS3、bS2、bS1、bS0Respectively representing the sum generated by adding each binary bit corresponding to two addends in the first four-bit full adder; bCoutAnd H2、H1、H0Respectively representing the carry generated by adding each binary bit corresponding to two addends in the first four-bit full adder, wherein bCoutIs the carry output produced by adding the most significant bits of the two addends; in the first four-bit full adder, bS0The exclusive OR gate is positioned in the northeast direction of the circuit layout and is positioned at the first layer of the circuit layout; h0The majority of the logic gates are located at bS0The third layer is positioned above the exclusive-or logic gate and positioned in the circuit layout; bS1At the XOR gate is located at bS0The left side of the exclusive-or logic gate is positioned on the first layer of the circuit layout; h1The majority of the logic gates are located at bS1The third layer is positioned above the exclusive-or logic gate and positioned in the circuit layout; bS2At the XOR gate is located at bS1The left side of the exclusive-or logic gate is positioned on the first layer of the circuit layout; h2The majority of the logic gates are located at bS2Above the positioned exclusive or logic gate,and is positioned on the third layer of the circuit layout; bS3At the XOR gate is located at bS2The left side of the exclusive-or logic gate is positioned on the first layer of the circuit layout; bCoutThe majority of the logic gates are located at bS3The third layer is positioned above the exclusive-or logic gate and positioned in the circuit layout;
six majority logic gates contained in the decimal carry generation circuit are distributed on the first layer of the circuit layout, and the expression is as follows:
K1＝M(bCout,M(1,bCout,bs3),M(bs1,bs2,bs3))
K2＝M(1,K1,M(0,bS0,bS3))
dCout＝＝M(dCin，K1,K2)
wherein, K1And K2The intermediate state generated by the decimal carry generation circuit is represented without special meaning; the decimal carry generation circuit comprises six majority logic gates with inputs from the output of the first four-bit full adder and the carry input dC of the decimal full adder of the quantum cellular automatoninThe output of the decimal carry generation circuit is the carry output dC of the decimal full adder of the quantum cellular automatonout(ii) a Six majority logic gates contained in the decimal carry generation circuit are distributed in the south of the first four-bit full adder and are positioned on the first layer of the circuit layout;
the four exclusive-or logic gates contained in the second four-bit full adder are distributed on the first layer of the circuit layout, the three majority logic gates contained in the second four-bit full adder are distributed on the third layer of the circuit layout, seven logic nodes form the second four-bit full adder, the second four-bit full adder is positioned on the south-most surface of the circuit layout, the decimal full adder decimal sum correction calculation of the quantum cellular automata is realized, and the formula is as follows: "dS3dS2dS1dS0＝0dCoutdCout0+bS3bS2bS1bS0+dCin"the expression of the specific calculation process is:
Figure BDA0002362634160000031
Figure BDA0002362634160000032
Figure BDA0002362634160000033
Figure BDA0002362634160000034
wherein dS3、dS2、dS1、dS0Decimal output of a quantum cellular automaton decimal full adder represented by four binary numbers respectively; in the second four-bit full adder, dS0The exclusive OR gate is positioned in the south-east of the circuit layout and is positioned at the first layer of the circuit layout; m (0, bS)0,dCin) Most of the logic gates are located at dS0The third layer is positioned above the exclusive-or logic gate and positioned in the circuit layout; dS1At the XOR gate is located at dS0The left side of the exclusive-or logic gate is positioned on the third layer of the circuit layout; m (bS)1,dCout,M(0,bS0,dCin) A majority of the logic gates are located at dS1The third layer is positioned above the exclusive-or logic gate and positioned in the circuit layout; dS2At the XOR gate is located at dS1The left side of the exclusive-or logic gate is positioned on the first layer of the circuit layout; m (bS)2,dCout,M(bS1,dCout,M(0,bS0,dCin) ) a majority logic gate is located at dS)2The third layer is positioned above the exclusive-or logic gate and positioned in the circuit layout; dS3Therein is arrangedXOR gate at dS2The left side of the exclusive-or logic gate is positioned on the first layer of the circuit layout; the output end of the decimal full adder of the final quantum cellular automaton is expressed as four binary numbers' dS3dS2dS1dS0"and one carry out" dCout”。
Compared with the prior art, the invention has the following advantages:
1. the decimal full adder of the quantum cellular automata is a decimal full adder based on an exclusive-OR logic gate and a plurality of logic gates, and the number of logic nodes and the logic depth required by the QCA decimal full adder are optimized by combining an exclusive-OR logic operator with stronger expression capacity and an advanced full adder carry structure on the premise of not changing the logic function of a circuit, so that the area and the delay of circuits of the one-bit and multi-bit QCA decimal full adder are optimized.
2. Compared with the full adder with the optimal performance, the decimal full adder of the quantum cellular automata provided by the invention has excellent performance, and is obviously improved in the aspects of delay and area: the 1-digit decimal full adder of the quantum cellular automaton provided by the invention reduces the delay and the area by 6.7% and 42% respectively; the quantum cellular automaton 4-bit decimal full adder designed on the basis of the 1-bit decimal full adder reduces delay and area by 19% and 37.7% respectively; the optimization effect is more obvious when the method is applied to the 8-digit decimal full adder of the quantum cellular automaton, and the delay and the area are respectively improved by 27.6 percent and 53.4 percent. Therefore, the decimal full adder of the quantum cellular automaton greatly reduces the circuit cost and enriches the circuit research methods in the circuit design. The invention provides a new research idea for the design of an arithmetic circuit based on majority logic and exclusive-OR logic, can reduce the area of the circuit and realize the reduction of delay, and has stronger practical significance for the development of circuit design.
Drawings
FIG. 1 is a schematic diagram of a conventional decimal full adder;
FIG. 2 is a schematic diagram of a decimal full adder with carry improvement;
FIG. 3 is a diagram of a basic device of a quantum cellular automaton;
FIG. 4 is a schematic diagram of a first layer of a circuit layout of a decimal full adder for a quantum cellular automaton according to the present invention;
FIG. 5 is a schematic diagram of a second layer of a circuit layout of a quantum cellular automata decimal full adder according to the present invention;
FIG. 6 is a third level schematic diagram of a circuit layout of a quantum cellular automata decimal full adder according to the present invention;
FIG. 7 is a circuit simulation diagram of a decimal full adder of a quantum cellular automaton according to the present invention;
FIG. 8 is a schematic diagram of a circuit layout of a 4 decimal full adder of a quantum cellular automaton according to the present invention;
fig. 9 is a circuit simulation diagram of a 4-digit decimal full adder of a quantum cellular automaton according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
Fig. 1 is a schematic structural diagram of a conventional decimal full adder. As shown in fig. 1, the carry bit is located in the first part of the whole circuit, and therefore tends to increase the length of the critical path of the multi-bit decimal full adder circuit, which in turn affects the delay of the circuit. Therefore, the invention adopts the full adder structure shown in FIG. 2, changes the input path and position of carry, greatly reduces the critical path length of the circuit, and is more obvious particularly in a multi-bit decimal adder. The decimal full adder of the quantum cellular automata adopts three basic quantum cellular automata devices as shown in figure 3, which are respectively (a): an inverter, (b): most logic gates, (c): an exclusive or logic gate. The circuit layout schematic diagram of the decimal full adder of the quantum cellular automata is shown in fig. 4, and comprises two parts, wherein the first part is a four-bit full adder (namely a first four-bit full adder) which is represented as 'ADD 1' and comprises four majority logic gates and four exclusive OR logic gates; the second part is a full adder correction circuit part; the full-adder correction circuit portion in turn comprises two parts: a decimal carry generation circuit comprising six majority logic gates, denoted "CLpart", and a second four-bit full adder, another four-bit full adder, denoted "ADD 2", comprising three majority logic gates and four exclusive or logic gates.
The decimal full adder of the quantum cellular automata is distributed on a circuit layout formed by three circuit layers, nine input ends and five output ends are provided in total, one input end is decimal carry input, the other eight input ends are divided into two groups, each group comprises four input ends, and each group represents a decimal number from zero to nine; one of the outputs being decimal carry output, i.e. carry output dC of full decimal adder of quantum cellular automatonout. The four exclusive-or logic gates included in the first four-bit full adder are distributed on the first layer of the circuit layout, the four majority logic gates included in the first four-bit full adder are distributed on the third layer of the circuit layout, and the eight logic nodes form the first four-bit full adder, and the expression of the first four-bit full adder is as follows:
Figure BDA0002362634160000051
Figure BDA0002362634160000052
Figure BDA0002362634160000053
Figure BDA0002362634160000054
wherein the content of the first and second substances,
Figure BDA0002362634160000055
represents an exclusive or logic gate, "M ()" represents a majority logic gate; dA3、dA2、dA1、dA0、dB3、dB2、dB1、dB0Four binary digits of the decimal numbers A and B, respectively; bS3、bS2、bS1、bS0Respectively representing the sum generated by adding each binary bit corresponding to two addends in the first four-bit full adder; bCoutAnd H2、H1、H0Respectively representing the carry generated by adding each binary bit corresponding to two addends in the first four-bit full adder, wherein bCoutIs the carry output produced by adding the most significant bits of the two addends; in the first four-bit full adder, bS0The exclusive OR gate is positioned in the northeast direction of the circuit layout and is positioned at the first layer of the circuit layout; h0The majority of the logic gates are located at bS0The third layer is positioned above the exclusive-or logic gate and positioned in the circuit layout; bS1At the XOR gate is located at bS0The left side of the exclusive-or logic gate is positioned on the first layer of the circuit layout; h1The majority of the logic gates are located at bS1The third layer is positioned above the exclusive-or logic gate and positioned in the circuit layout; bS2At the XOR gate is located at bS1The left side of the exclusive-or logic gate is positioned on the first layer of the circuit layout; h2The majority of the logic gates are located at bS2The third layer is positioned above the exclusive-or logic gate and positioned in the circuit layout; bS3At the XOR gate is located at bS2The left side of the exclusive-or logic gate is positioned on the first layer of the circuit layout; bCoutThe majority of the logic gates are located at bS3And the third layer is positioned above the exclusive-OR logic gate and positioned on the third layer of the circuit layout.
Six majority logic gates contained in the decimal carry generation circuit are distributed on the first layer of the circuit layout, and the expression is as follows:
K1＝M(bCout,M(1,bCout,bs3),M(bs1,bs2,bs3))
K2＝M(1,K1,M(0,bS0,bS3))
dCout＝M(dCin，K1,K2)
wherein, K1And K2The intermediate state generated by the decimal carry generation circuit is represented without special meaning; the decimal carry generation circuit comprises six majority logic gates with inputs from the output of the first four-bit full adder and the carry input dC of the decimal full adder of the quantum cellular automatoninThe output of the decimal carry generation circuit is the carry output dC of the decimal full adder of the quantum cellular automatonout(ii) a Six majority logic gates contained in the decimal carry generation circuit are distributed in the south of the first four-bit full adder and are positioned on the first layer of the circuit layout;
the four exclusive-or logic gates contained in the second four-bit full adder are distributed on the first layer of the circuit layout, the three majority logic gates contained in the second four-bit full adder are distributed on the third layer of the circuit layout, seven logic nodes form the second four-bit full adder, the second four-bit full adder is positioned on the south-most surface of the circuit layout, the decimal full adder decimal sum correction calculation of the quantum cellular automata is realized, and the formula is as follows: "dS3dS2dS1dS0＝0dCoutdCout0+bS3bS2bS1bS0+dCin", wherein" 0dCoutdCout0 "is the" corrected addend "part in fig. 4, and the expression of the specific calculation process is:
Figure BDA0002362634160000061
Figure BDA0002362634160000062
Figure BDA0002362634160000063
Figure BDA0002362634160000064
wherein dS3、dS2、dS1、dS0Decimal output of a quantum cellular automaton decimal full adder represented by four binary numbers respectively; in the second four-bit full adder, dS0The exclusive OR gate is positioned in the south-east of the circuit layout and is positioned at the first layer of the circuit layout; m (0, bS)0,dCin) Most of the logic gates are located at dS0Above the XOR gate, and on the third layer of the circuit layout, with its input AND dS0The inputs of the exclusive-or gates are identical, and the output is taken as dS1The input of the exclusive or gate where it is located; dS1At the XOR gate is located at dS0The left side of the exclusive-or logic gate is positioned on the third layer of the circuit layout; m (bS)1,dCout,M(0,bS0,dCin) A majority of the logic gates are located at dS1The third layer is positioned above the exclusive-or logic gate and positioned in the circuit layout; dS2At the XOR gate is located at dS1The left side of the exclusive-or logic gate is positioned on the first layer of the circuit layout; m (bS)2,dCout,M(bS1,dCout,M(0,bS0,dCin) ) a majority logic gate is located at dS)2The third layer is positioned above the exclusive-or logic gate and positioned in the circuit layout; dS3At the XOR gate is located at dS2The left side of the exclusive-or logic gate is positioned on the first layer of the circuit layout; the output end of the decimal full adder of the final quantum cellular automaton is expressed as four binary numbers' dS3dS2dS1dS0"and one carry out" dCout”。
Compared with the full adder with the optimal performance (T.ZHang, V.Pudi and W.Liu, New Majority Gate-Based Parallel BCD Adderdesigns for Quantum-Dot Cellular Automata, IEEE Transactions on Circuits and systems II: Express Briefs, vol.66, No.7, pp.1232-1236, July 2019), the 1-digit decimal full adder with the Quantum Cellular Automata provided by the invention reduces 6.7% and 42% in delay and area respectively, and the data table of the simulation result is shown in FIG. 7. A quantum cellular automaton 4-bit decimal full adder designed on the basis of a 1-bit decimal full adder is shown in figure 8, and a circuit simulation diagram is shown in figure 9, which respectively reduces the delay and the area by 19 percent and 37.7 percent compared with the traditional full adder with the optimal performance. The optimization effect is more obvious when the method is applied to the 8-digit decimal full adder of the quantum cellular automaton, and the delay and the area are respectively improved by 27.6 percent and 53.4 percent. The performance comparison of the decimal full adder of the quantum cellular automaton provided by the invention and the full adder with the optimal traditional performance is shown in the table I.
Watch 1
Figure BDA0002362634160000071
In conclusion, the decimal full adder of the quantum cellular automata provided by the invention greatly reduces the circuit cost and enriches the circuit research methods in the circuit design. The invention provides a new research idea for the design of an arithmetic circuit based on majority logic and exclusive-OR logic, can reduce the area of the circuit and realize the reduction of delay, and has stronger practical significance for the development of circuit design.

Claims (1)

1. A quantum cellular automaton decimal full adder is characterized in that: the decimal full adder of the quantum cellular automata is distributed on a circuit layout formed by three circuit layers, comprises a first four-bit full adder and a full adder correction circuit, and comprises nine input ends and five output ends; one of the input ends is decimal carry input, and the other eight input ends are divided into two groups, wherein each group comprises four input ends, and each group represents a decimal number from zero to nine; one of the outputs being decimal carry output, i.e. carry output dC of full decimal adder of quantum cellular automatonoutThe other four output ends jointly represent a decimal number from zero to nine, namely the sum output of the decimal full adder of the quantum cellular automaton; the first four-bit full adder comprises four majority logic gates and four exclusive-or logic gates, the full adder correction circuit comprises a decimal carry generation circuit and a second four-bit full adder, the decimal carry generation circuit consists of six majority logic gates, and the second four-bit full adder comprises three majority logic gates and four exclusive-or logic gates;
the four XOR logic gates contained in the first four-bit full adder are distributed on the first layer of the circuit layout, most of the four logic gates contained in the first four-bit full adder are distributed on the third layer of the circuit layout, the eight logic nodes form the first four-bit full adder, and the expression of the first four-bit full adder is as follows:
Figure FDA0002362634150000011
Figure FDA0002362634150000012
Figure FDA0002362634150000013
Figure FDA0002362634150000014
wherein the content of the first and second substances,
Figure FDA0002362634150000015
represents an exclusive or logic gate, "M ()" represents a majority logic gate; dA3、dA2、dA1、dA0、dB3、dB2、dB1、dB0Four binary digits of the decimal numbers A and B, respectively; bS3、bS2、bS1、bS0Respectively representing each of two addends in the first four-bit full adderThe sum of the binary bit sums; bCoutAnd H2、H1、H0Respectively representing the carry generated by adding each binary bit corresponding to two addends in the first four-bit full adder, wherein bCoutIs the carry output produced by adding the most significant bits of the two addends; in the first four-bit full adder, bS0The exclusive OR gate is positioned in the northeast direction of the circuit layout and is positioned at the first layer of the circuit layout; h0The majority of the logic gates are located at bS0The third layer is positioned above the exclusive-or logic gate and positioned in the circuit layout; bS1At the XOR gate is located at bS0The left side of the exclusive-or logic gate is positioned on the first layer of the circuit layout; h1The majority of the logic gates are located at bS1The third layer is positioned above the exclusive-or logic gate and positioned in the circuit layout; bS2At the XOR gate is located at bS1The left side of the exclusive-or logic gate is positioned on the first layer of the circuit layout; h2The majority of the logic gates are located at bS2The third layer is positioned above the exclusive-or logic gate and positioned in the circuit layout; bS3At the XOR gate is located at bS2The left side of the exclusive-or logic gate is positioned on the first layer of the circuit layout; bCoutThe majority of the logic gates are located at bS3The third layer is positioned above the exclusive-or logic gate and positioned in the circuit layout;
six majority logic gates contained in the decimal carry generation circuit are distributed on the first layer of the circuit layout, and the expression is as follows:
K1＝M(bCout，M(1，bCout，bS3)，M(bS1，bS2，bS3))
K2＝M(1，K1，M(0，bS0，bS3))
dCout＝M(dCin，K1，K2)
wherein, K1And K2Represents the aboveThe decimal carry generation circuit generates an intermediate state without special meaning; the decimal carry generation circuit comprises six majority logic gates with inputs from the output of the first four-bit full adder and the carry input dC of the decimal full adder of the quantum cellular automatoninThe output of the decimal carry generation circuit is the carry output dC of the decimal full adder of the quantum cellular automatonout(ii) a Six majority logic gates contained in the decimal carry generation circuit are distributed in the south of the first four-bit full adder and are positioned on the first layer of the circuit layout;
the four exclusive-or logic gates contained in the second four-bit full adder are distributed on the first layer of the circuit layout, the three majority logic gates contained in the second four-bit full adder are distributed on the third layer of the circuit layout, seven logic nodes form the second four-bit full adder, the second four-bit full adder is positioned on the south-most surface of the circuit layout, the decimal full adder decimal sum correction calculation of the quantum cellular automata is realized, and the formula is as follows: "dS3dS2dS1dS0＝0dCoutdCout0+bS3bS2bS1bS0+dCin"the expression of the specific calculation process is:
Figure FDA0002362634150000021
Figure FDA0002362634150000022
Figure FDA0002362634150000023
Figure FDA0002362634150000024
wherein dS3、dS2、dS1、dS0Decimal output of a quantum cellular automaton decimal full adder represented by four binary numbers respectively; in the second four-bit full adder, dS0The exclusive OR gate is positioned in the south-east of the circuit layout and is positioned at the first layer of the circuit layout; m (0, bS)0，dCin) Most of the logic gates are located at dS0The third layer is positioned above the exclusive-or logic gate and positioned in the circuit layout; dS1At the XOR gate is located at dS0The left side of the exclusive-or logic gate is positioned on the third layer of the circuit layout; m (bS)1，dCout，M(0，bS0，dCin) A majority of the logic gates are located at dS1The third layer is positioned above the exclusive-or logic gate and positioned in the circuit layout; dS2At the XOR gate is located at dS1The left side of the exclusive-or logic gate is positioned on the first layer of the circuit layout; m (bS)2，dCout，M(bS1，dCout，M(0，bS0，dCin) ) a majority logic gate is located at dS)2The third layer is positioned above the exclusive-or logic gate and positioned in the circuit layout; dS3At the XOR gate is located at dS2The left side of the exclusive-or logic gate is positioned on the first layer of the circuit layout; the output end of the decimal full adder of the final quantum cellular automaton is expressed as four binary numbers' dS3dS2dS1dS0"and one carry out" dCout”。
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