CN103793562B - Active power distribution network transient state real-time emulation system method for designing based on FPGA - Google Patents

Abstract

A kind of active power distribution network transient state real-time emulation system method for designing based on FPGA, is divided into off-line simulation environment and in-circuit emulation environment, and off-line simulation environment is responsible for calculating the total clock cycle number n that every time step calculates_totalAnd emulation used time t_total, according to real-time simulation used time t_totalSimulation step length Δ t is set, and the relevant parameter calculated according to simulation step length Δ t and the basic parameter information that reads are uploaded to in-circuit emulation environment based on FPGA；In-circuit emulation environment completes the real-time calculating of emulation, by finite states machine control simulation status, each time step includes the formation of the history entries current source column vector calculation of each class component in each step-length, total history entries current source column vector, Solving Linear and updates step, history entries current source column vector calculation and the renewal step of each class component are completely self-contained, can concurrent processing.This invention ensures that the real-time during whole system transient emulation, there is preferable feasibility and the suitability.

Description

Active power distribution network transient state real-time emulation system method for designing based on FPGA

Technical field

The present invention relates to a kind of electric system simulation method for designing.Particularly relate to a kind of active power distribution network based on FPGA Transient state real-time emulation system method for designing.

Background technology

Active power distribution network transient state real-time simulation is the Digital Simulation mode that a kind of and real clock is Tong Bu, by imitating in real time True device is connected with actual physical device and can carry out exploitation and the test job of various control and protection device, and can illumination simulation, Active power distribution network complexity transient process under the multiple Run-time scenarios such as wind speed change, Voltage Drop, short trouble, removal of load, can Effectively reduce research and development and experimentation cost, it is to avoid the Devices to test impact on real system.Active power distribution network transient state real-time simulation master The design of distributed power generation to be used for (energy storage) cell controller is tested with test, active power distribution network EMS, active is joined Electric network protection device debugging etc..

In active power distribution network, in order to accurately portray a series of fast dynamic mistake including including electronic power switch action etc. Journey, the step-length of transient emulation becomes more and more less.In terms of emulation angle, when the existence of power electronic equipment can cause calculating matrix The series of problems such as switch motion, numerical value concussion between change, step-length, needs to expend longer meter for accurately solving of these problems Evaluation time and more calculating resource.The more important thing is, these extra consumption calculating the time are the most imponderable.By In distributed power source wide variety, the mathematical model of its control system is sufficiently complex, and logical judgment is many, has strong nonlinearity special Levy, thus it is in large scale to cause control system to solve.Tradition based on the conventional connection hardware such as CPU processor or DSP is the most imitative True device, is difficulty with the transient state real-time simulation modeled in detail under less simulation step length.By contrast, based on field-programmable The devices at full hardware of logic gate array (field-programmable gate array, FPGA) is calculated as real-time simulation and provides one Plant new approaches.The most fully configurable intrinsic hardware concurrent structure of FPGA, its logical resource can be configured to the most also Row processing unit also realizes the calculating of multi-layer highly-parallel；Meanwhile, fpga chip has a large amount of embedded block RAM, configurable For a large amount of distributed ROM or RAM, its data and address width, port number are the most configurable, and internal memory in tradition real-time simulator It is shared with bus mostly, and port is limited, limit the efficiency of transmission of data；FPGA allows to use pipelining, adds Strong data-handling efficiency, and, FPGA also has the interconnector that a large amount of transmission speed is exceedingly fast, and will not introduce excessive communication Postpone.

Therefore active power distribution network transient state real-time emulation system based on FPGA allows to calculate faster speed and less meter Calculate step-length, can be active power distribution network transient state real-time simulation to require strict part for step-length provide speed and precision to prop up Hold, compact, the most more advantage in the economy of construction cycle and cost；And in view of the mould of tradition real-time simulator The contents such as type and algorithm are the most open to user, research and develop simulation algorithm accurately and efficiently further unlikely.Phase Under Bi, active power distribution network transient state real-time simulator based on FPGA has exploitability, expansibility, it is possible to for active distribution Network control system, the research of Preservation tactics, new equipment debugging etc. provides test platform.

The basic method for solving of transient state real-time simulation problem can be divided into modal analysis (nodal analysis) and State-Variable Analysis Method (state space analysis) two classes.Relative to State variable analysis, modal analysis is at algorithm Realize the aspect such as difficulty, simulation calculation speed and there is greater advantage, therefore in transient off-line emulation such as EMTP, PSCAD/EMTDC In the transient state real-time simulation instrument such as instrument and RTDS, HYPERSIM, all using modal analysis as basic framework.

Transient emulation modal analysis comprises 2 basic steps:

1) use certain numerical integration method (such as trapezoidal integration) poor to the characteristic equation of dynamic element in system Differentiation, obtains the equivalent circuit of Equivalent Calculation conductance and history entries current source parallel form.Prop up with the inductance shown in accompanying drawing 1 As a example by road, shown in its basic Voltammetric Relation equation such as formula (1), available formula (2) and the difference of (3) form after application trapezoidal integration Divide equation.

$u_k\left(t\right)-u_m\left(t\right)=L\frac{{\mathrm{di}}_{\mathrm{km}}\left(t\right)}{\mathrm{dt}}---\left(1\right)$

$i_{\mathrm{km}}\left(t\right)=\frac{\mathrm{\Δt}}{2L}[u_k\left(t\right)-u_m\left(t\right)]+I_h[t-\mathrm{\Δt}]---\left(2\right)$

$I_h(t-\mathrm{\Δt})=i_{\mathrm{km}}(t-\mathrm{\Δt})+\frac{\mathrm{\Δt}}{2L}[u_k(t-\mathrm{\Δt})-u_m(t-\mathrm{\Δt})]$

It is G that difierence equation (2) is considered as a value_eqThe promise that the conductance of Δ t/ (2L) is in parallel with history entries current source Equivalent circuit form.

2) difference equation of the whole electrical system of simultaneous, can form nodal-admittance matrix G as shown in formula (4), solve this Equation can get the instantaneous value of each node voltage in system, and then obtains branch voltage and branch current.This solution procedure is not Disconnected propelling can complete the transient process of whole system and solve.

Gv=I_h (4)

Node conductance equation shown in formula (4) is system of linear equations, and the numerical software bag of various maturation can be used to ask Solve, and piece-wise linearization, puppet can be used non-for the various non-linear elements in electrical system, such as nonlinear impedance, motor etc. Linearly, the method such as predictor corrector method, penalty method carry out Local treatment, and system is still the linear side to formula (4) form on the whole Solving of journey group.In active power distribution network transient state real-time simulator based on FPGA, need to give full play to FPGA hardware the most excellent The system solution framework of gesture and pipelining, could meet the need of active power distribution network transient state real-time simulation based on little step-length Ask.To this end, the present invention proposes a kind of active power distribution network transient state real-time emulation system method for designing based on FPGA.This design side The system framework that method proposes can give full play to the technical advantage of FPGA hardware concurrency and pipelined architecture, it is ensured that whole Real-time in system transient modelling simulation process, and be that the detailed dynamic process using less step-length accurately to solve active power distribution network carries Supply reliable basis.

Summary of the invention

The technical problem to be solved is to provide a kind of active power distribution network of based on FPGA transient state real-time simulation system System method for designing.It can give full play to FPGA hardware concurrency and pipelined architecture technical advantage, it is ensured that whole system Real-time during transient emulation, and be that the detailed dynamic process using less step-length accurately to solve active power distribution network provides Reliable basis.

The technical solution adopted in the present invention is: a kind of active power distribution network transient state real-time emulation system based on FPGA designs Method, active power distribution network transient state real-time emulation system is divided into off-line simulation environment and in-circuit emulation environment, wherein off-line simulation ring Real-time simulation used time t is responsible in border_totalCalculating, according to real-time simulation used time t_totalSimulation step length Δ t is set, and will be according to imitative Relevant parameter that true step delta t calculates and the basic parameter information read are uploaded to in-circuit emulation ring based on FPGA Border；In-circuit emulation environment completes the real-time calculating of emulation, including the history entries current source column vector of class component each in each step-length Calculate, total history entries current source column vector is formed, Solving Linear and update step, specifically includes following steps:

The first step: under offline environment, uses primary element to be modeled active power distribution network, reads the most passive unit Part, circuit element, source element, circuit breaker element, the basic parameter information of electronic power switch element, statistics obtain described respectively The quantity of class component；

Second step: under offline environment, calculates basic passive element, circuit element, source element, chopper unit respectively The clock periodicity that part, the history entries current source column vector of electronic power switch element solve: n_{H, RLC}, n_{H, LINE}, n_{H, SOURCE}, n_{H, BREAKER}, n_{H, PE}, and update the clock periodicity of step: n_{U, RLC}, n_{U, LINE}, n_{U, SOURCE}, n_{U, BREAKER}, n_{U, PE}, wherein, n_h Represent the clock periodicity that history entries current source column vector solves, take the integer more than or equal to 0, n_uRepresent the clock updating step Periodicity, takes the integer more than or equal to 0, and RLC represents basic passive element, and LINE represents that circuit element, SOURCE represent power supply Element, BREAKER represents that circuit breaker element, PE represent electronic power switch element；

3rd step: under offline environment, calculates each class component history entries current source column vector described in the first step and is formed always Clock periodicity n needed for history entries current source column vector_hist, calculate and use parallel matrix-vector multiplication to realize linear equation The clock periodicity n that group solves_matrix；

4th step: under offline environment, calculating the calculating clock cycle sum needed for the emulation of each step is n_total=max (n_{H, RLC}, n_{H, Line}, n_{H, SOURCE}, n_{H, BREAKER}, n_{H, PE})+n_hist+n_matrix+max(n_{U, RLC}, n_{U, Line}, n_{U, SOURCE}, n_{U, BREAKER}, n_{U, PE})+n_other, wherein the history entries current source column vector of each class component described in the first step solves and updates the calculating of step Concurrently carrying out, max function representation takes maximum, n_otherRepresent the total clock cycle number of some scattered operations；

5th step: under offline environment, according to drive clock frequency f and the clock cycle sum n of FPGA_total, obtain T actual time needed for each step emulates in 4th step_total, t_total=n_total/ f, sets simulation calculation step delta t, and Δ t need to expire Foot t_total< Δ t is to ensure emulation real-time；

6th step: under offline environment, according to the equivalent electric of each class component described in the simulation step length Δ t calculating first step Lead, form nodal-admittance matrix, history entries current source and update the meter needed for computing in all kinds of component models described in calculating Calculate parameter, calculate the inverse matrix of nodal-admittance matrix；

7th step: history entries current source and renewal fortune in the equivalent conductance that the 6th step has been obtained, all kinds of component models Imitative described in basic parameter information described in calculating parameter needed for calculation, the inverse matrix of nodal-admittance matrix, the first step, the 5th step True step delta t is uploaded to in-circuit emulation environment based on FPGA；

8th step: under at thread environment, arranges emulation moment t=0, the emulation shape of finite state machine in global control module State is idle condition, starts emulation；

9th step: under at thread environment, simulation status enters state one, and simulation timer starts timing, calculates the first step The history entries current source of described each class component, generates history entries current source column vector, the calculating of wherein said each class component Being parallel, respective end signal is set high level after completing by the calculating task of each class component；

Tenth step: under at thread environment, carries out logical AND operation to the end signal of each class component described in the 9th step, when This signal is high level, after the most all elements complete the calculating of history entries current source, and the history entries current source that all elements are generated Column vector combines, and obtains total history entries current source column vector I_h, and store, generate state one end signal；

11st step: under at thread environment, simulation status enters state two, reads corresponding according to circuit breaker switch state Inverse matrix G of nodal-admittance matrix^-1, use parallel matrix-vector multiplication by inverse matrix G^-1And total history entries current source row Vector I_hCalculate node voltage column vector v, generate state two end signal；

12nd step: under at thread environment, simulation status enters state three, is updated described each class component respectively Computing, calculates terminal voltage and the branch current of each element, and stores, and the renewal of wherein said each class component calculates It is parallel；

13rd step: under at thread environment, simulation result user specified passes offline environment back, in order to Yong Hucha See；

14th step: under at thread environment, it is judged that when simulation timer whether timing is to Δ t, as met condition, then generate Step-length end signal, otherwise emulator waits until timing is to Δ t；

15th step: judge whether simulation time reaches emulation and end the moment, ends the moment as reached emulation, then emulates knot Bundle, otherwise returns the 9th step.

Primary element described in the first step includes: basic passive element, circuit element, source element, circuit breaker element, electricity Power electronic switching element.

Basic parameter information described in the first step includes: the basic resistance of passive element, inductance and capacitance parameter, circuit unit The resistance of part and inductance matrix, the amplitude of source element, frequency and initial phase, the offresistance of circuit breaker element, Guan Bi electricity Resistance, breaker actuation time, electronic power switch element represents the resistance of open circuit, electric capacity and represents the inductance of Guan Bi, all kinds of The node serial number of element, nodal-admittance matrix dimension.

The control scheduling of simulation status one, simulation status two and simulation status three in real-time simulation, is by finite state Machine realizes.

The active power distribution network transient state real-time emulation system method for designing based on FPGA of the present invention, it is possible to give full play to FPGA Hardware concurrent and the technical advantage of pipelined architecture, it is ensured that the real-time during whole system transient emulation, and be The detailed dynamic process using less step-length accurately to solve active power distribution network provides reliable basis.The simulation result of the present invention Can fit like a glove in stable state with transient process with the simulation result of business simulation software, the dynamic response characteristic of the two is protected Having held highly consistent, embodied good simulation accuracy, fully demonstrate present invention proposition is suitable to the active of FPGA realization The feasibility of power distribution network transient state real-time emulation system frame design method.The present invention has preferable feasibility and the suitability, for Realize containing distributed power source, energy storage device active power distribution network transient state real-time simulation in provide a kind of well resolving ideas.

Accompanying drawing explanation

Accompanying drawing 1 is inductive branch schematic diagram；

Accompanying drawing 2 is that active power distribution network transient state real-time emulation system based on FPGA solves framework；

Accompanying drawing 3 is global control module schematic diagram based on finite state machine；

Accompanying drawing 4 is that basic passive element history amount based on FPGA solves block diagram；

Accompanying drawing 5 is that circuit element history amount based on FPGA solves block diagram；

Accompanying drawing 6 is that power supply class component history amount based on FPGA solves block diagram；

Accompanying drawing 7 is that electronic power switch element history amount based on FPGA solves block diagram；

Accompanying drawing 8 is Solving Linear block diagram based on FPGA；

Accompanying drawing 9 is the flow chart of the active power distribution network transient state real-time emulation system method for designing based on FPGA of the present invention；

Accompanying drawing 10 is example system wiring figure；

Accompanying drawing 11 is the three-phase current that node 11 flows to node 12；

Accompanying drawing 12 is the three-phase voltage of node 12.

Detailed description of the invention

Below in conjunction with embodiment and accompanying drawing, the active power distribution network transient state real-time emulation system based on FPGA of the present invention is set Meter method is described in detail.

The active power distribution network transient state real-time emulation system method for designing based on FPGA of the present invention, as shown in Figure 2, active Power distribution network transient state real-time emulation system is divided into off-line simulation environment and in-circuit emulation environment, and wherein off-line simulation environment is responsible in real time Emulation used time t_totalCalculating, according to real-time simulation used time t_totalSimulation step length Δ t is set, and will count according to simulation step length Δ t The relevant parameter calculated and the basic parameter information read are uploaded to in-circuit emulation environment based on FPGA；In-circuit emulation ring Border completes the real-time calculating of emulation, including the history entries current source column vector calculation of class component each in each step-length, total history entries The formation of current source column vector, Solving Linear and renewal step are concrete as it is shown in figure 9, comprise the steps:

The first step: under offline environment, uses primary element to be modeled active power distribution network, reads all kinds of primary element Basic parameter information, statistics obtains the quantity of described each class component, and wherein, described primary element includes: the most passive unit Part, circuit element, source element, circuit breaker element, electronic power switch element etc.；Described basic parameter information includes: base The resistance of this passive element, inductance and capacitance parameter, the resistance of circuit element and inductance matrix, the amplitude of source element, frequency And initial phase, the offresistance of circuit breaker element, closed resistance, breaker actuation time, electronic power switch element represents The resistance of open circuit, electric capacity and the inductance of expression Guan Bi, the node serial number of each class component, nodal-admittance matrix dimension.

Second step: under offline environment, calculates basic passive element, circuit element, source element, chopper unit respectively The clock periodicity that the history entries current source column vector of each class components such as part, electronic power switch element solves: n_{H, RLC}, n_{H, LINE}, n_{H, SOURCE}, n_{H, BREAKER}, n_{H, PE}, and update the clock periodicity of step: n_{U, RLC}, n_{U, LINE}, n_{U, SOURCE}, n_{U, BREAKER}, n_{U, PE}, Wherein, n_hRepresent the clock periodicity that history entries current source column vector solves, take the integer more than or equal to 0, n_uRepresent and update step Clock periodicity, take the integer more than or equal to 0；

Active power distribution network includes the multiclass primary elements such as power supply, motor, transformator, circuit and switch models.Consider The element related in active power distribution network is more, here only for have the basic passive element of exemplary process mode, circuit element, Power supply class component and electronic power switch element illustrate, and provide the history entries current source of these several class components under offline environment Column vector solve and update step clock cycle sum computational methods.

(1) basic passive element

Basic passive element includes resistance R, inductance L and electric capacity C and RL, RC composite component etc. being made up of them.Right In this class component, its history amount solves and updates shown in general type such as formula (5) and the formula (6) of step.In formula, according to R, L, C Combining form is different, A₁、A₂、G_eqExpression the most different, as shown in table 1.

I_h(t-Δt)=A₁v(t-Δt)+A₂i(t-Δt) (5)

i(t)=G_eqv(t)+I_h(t-Δt) (6)

The basic passive element of table 1 calculates parameter expression

For the emulation of basic passive element, the massive parallelism of FPGA can be made full use of and realize deep pipeline knot Structure.As a example by history entries solves, as shown in Figure 4.Computing formula, A is solved according to history entries₁、A₂And the branch road electricity of a upper time step ((t-Δ t) can read from 4 RAM t-Δ t) and branch current i pressure v simultaneously, and entered by 2 Floating-Point Multipliers simultaneously Row multiplying, obtains history entries I finally by floating-point adder device_h(t-Δ t), is stored in RAM_histIn, based on next time step Calculate.In this module, RAM reading data needs 2 clock cycle, and floating number multiplication and additive operation employ integrated compiling The IP kernel that environment carries, it calculates clock number n_multiplyAnd n_addIt is respectively 5 and 7 clock cycle.Therefore, module initial time delay It it is 14 clock cycle.Under pipelined architecture, the result of calculation of first basic passive element will be after 14 clock cycle Obtain, work as N_RLCIndividual passive element passes sequentially through history entries and solves module when processing, its total clock cycle number n_{H, RLC}=14+ (N_RLC-1) the individual clock cycle.In like manner, its renewal step comprises two floating-point adders and a floating number multiplication, its total clock Periodicity n_{U, RLC}=21+(N_RLC-1) the individual clock cycle.

(2) circuit element

The history entries computing formula of circuit element and renewal calculate shown in publicity such as formula (7) and formula (8):

$\left[\begin{array}{c}{I}_{h1}(t-\mathrm{\&Delta;t})\\ I_{h2}(t-\mathrm{\&Delta;t})\\ I_{h3}(t-\mathrm{\&Delta;t})\end{array}\right]=\left[\begin{array}{ccc}{A}_{11}& A_{12}& A_{13}\\ A_{21}& A_{22}& A_{23}\\ A_{31}& A_{32}& A_{33}\end{array}\right]\left[\begin{array}{c}{v}_1(t-\mathrm{\&Delta;t})\\ v_2(t-\mathrm{\&Delta;t})\\ v_3(t-\mathrm{\&Delta;t})\end{array}\right]+\left[\begin{array}{ccc}{B}_{11}& B_{12}& B_{13}\\ B_{21}& B_{22}& B_{23}\\ B_{31}& B_{32}& B_{33}\end{array}\right]\left[\begin{array}{c}{i}_1(t-\mathrm{\&Delta;t})\\ i_2(t-\mathrm{\&Delta;t})\\ i_3(t-\mathrm{\&Delta;t})\end{array}\right]---\left(7\right)$

$\left[\begin{array}{c}{i}_1\left(t\right)\\ i_2\left(t\right)\\ i_3\left(t\right)\end{array}\right]=\left[\begin{array}{ccc}{A}_{11}& A_{12}& A_{13}\\ A_{21}& A_{22}& A_{23}\\ A_{31}& A_{32}& A_{33}\end{array}\right]\left[\begin{array}{c}{v}_1\left(t\right)\\ v_2\left(t\right)\\ v_3\left(t\right)\end{array}\right]+\left[\begin{array}{c}{I}_{h1}(t-\mathrm{\&Delta;t})\\ I_{h2}(t-\mathrm{\&Delta;t})\\ I_{h3}(t-\mathrm{\&Delta;t})\end{array}\right]$

As a example by history entries solves, as shown in Figure 5.[A] and [B] is 3x3 matrix, can use RAM respectively_A1、 RAM_A2、RAM_A3、RAM_B1、RAM_B2、RAM_B3Store each circuit element [A] and a line of [B] matrix.When emulation starts, [A] The branch voltage vector sum branch current vector of [B] and a upper time step reads from RAM simultaneously, and according to shown in accompanying drawing 5 Flow process carries out parallel matrix vector dot computing and parallel vector additive operation.History entries electric current when each circuit element Source I_h1(t-Δt)、I_h2(t-Δt)、I_h3(after t-Δ t) is calculated, it is re-converted into floating number, and by time delay, whole Close, extraction is stored in memory RAM after operating_hist.Delay_nclk module in accompanying drawing 5 represents and carries out prolonging of n clock cycle Time, it mostly being alignment of data and arrange, Fix2Float and Float2Fix module is for fixed-point number and the mutual conversion of floating number.When N_LINEIndividual circuit element passes sequentially through history entries and solves module when processing, the clock periodicity n of solution procedure_{H, LINE}=22+ (3*N_LINE-1).It addition, the clock periodicity n of its renewal process_{U, LINE}=33+(3*N_LINE-1)。

(3) power supply class component

Power module can process and includes single-phase electricity potential source, single-phase current, three-phase voltage source, three-phase current source and be subject to The control multiple power sources such as voltage source and controlled current source.As a example by alternating current source, its output is general all as shown in formula (9):

f(t)=Asin(ωt+θ) (9)

Wherein, A represents that amplitude, ω represent that angular frequency, θ represent initial phase.Look-up table is used to realize asking of this function Solving, its principle is as shown in Figure 6.

First by the sampling step length T less than simulation step length Δ t_sIn calculating a cycle in advance, all of unit is sinusoidal Value sin (ω t+ θ), and it is stored in RAM_sin, the initial phase θ of each alternating current source extrapolates corresponding to RAM simultaneously_sinInitially Location is also sequentially stored into RAM_θIn, RAM simultaneously_θEach phase place of middle storage advances with emulation and is incremented by, and its increment Inc is imitative True step-length and ratios delta t/T of sampling step length_s.Thus without calculating Nonlinear Sinusoidal function by complicated algorithm, only need Pass through RAM_θAddress date from RAM_sinMiddle reading unit sine value also carries out floating number multiplication, each exchange with amplitude A Amplitude A in source is stored in memory RAM the most in advance_AIn.Work as N_SOURCEIndividual source element passes sequentially through history entries and solves module and carry out During process, the clock periodicity n of solution procedure_{H, SOURCE}=9+(N_SOURCE-1).It addition, it updates step for the clock week solved Issue n_{U, SOURCE}=7+(N_SOURCE-1)。

(4) electronic power switch element

The present invention makes to carry out switch modeling with the following method, method particularly includes: use small inductor simulation during switch Guan Bi, open Closing and use small capacitances form simulation in series with a resistor when disconnecting, formula (10) row have been write and have been used switching off of obtaining of trapezoidal method difference With characteristic equation during Guan Bi.

$i\left(t\right)=\frac{\mathrm{\&Delta;t}}{2L_s}u\left(t\right)+\frac{\mathrm{\&Delta;t}}{2L_s}u(t-\mathrm{\&Delta;t})+i(t-\mathrm{\&Delta;t})$

$i\left(t\right)\frac{1}{\frac{\mathrm{\&Delta;t}}{2C_s}+R_s}u\left(t\right)-\frac{1}{\frac{\mathrm{\&Delta;t}}{2C_s}+R_s}u(t-\mathrm{\&Delta;t})-\frac{\frac{\mathrm{\&Delta;t}}{2C_s}-R_s}{\frac{\mathrm{\&Delta;t}}{2C_s}+R_s}i(t-\mathrm{\&Delta;t})---\left(10\right)$

L in formula (10)_sRepresent inductance during switch Guan Bi, C_sRepresent electric capacity when switching off, R_sWhen expression switches off Resistance, (t-Δ t) represents that (t-Δ t) represents this time for this time step and the switching current of a upper time step, u (t) and u to i (t) with i Step and the switch both sides voltage of a upper time step, Δ t represents simulation step length.Admittance when if formula (10) breaker in middle disconnects and closes Meet formula (11) and then ensure that when on off state switches, admittance matrix is constant, only rely on history amount change the most changeable switch shape State.

$\frac{\mathrm{\&Delta;t}}{2L_s}=\frac{1}{\frac{\mathrm{\&Delta;t}}{2C_s}+R_s}---\left(11\right)$

Use the method time, though switch how to change, admittance matrix remains constant, the most only need to store one inverse Matrix, greatly alleviates the storage pressure of inverse matrix.

The Realization of Simulation for switch element can make full use of the massive parallelism of FPGA, and realizes deep pipeline knot Structure.Illustrate as a example by its history amount solves, shown in its solution formula such as formula (12), two expression formulas in formula (10) combine Conjunction forms, and concrete FPGA realizes block diagram as shown in Figure 7.

i(t)=Gu(t)+I_h(t-Δt) (12)

I_h(t-Δt)=A₁u(t-Δt)+A2_i(t-Δt)

In formula (12), A₁And A₂Value determined by off state, RAM_v、RAM_iAnd RAM_histFor storage switch voltage, Switching current and history amount, RAM_{A1_open}、RAM_{A1_closed}、RAM_{A2_open}And RAM_{A2_closed}It is respectively used to store each open A when pass is opened or closed₁And A₂Value A_{1_open}、A_{1_closed}、A_{2_open}And A_{2_closed}, RAM_stateFor storing each IGBT's On off state state.As shown in Figure 8, each time step calculates when starting, A_{1_open}、A_{1_closed}、A_{2_open}、A_{2_closed}And State reads from memorizer simultaneously, wherein A_{1_open}、A_{1_closed}、A_{2_open}And A_{2_closed}Distributed by two data respectively Device, and judged this time step A by by off state state₁And A₂Value.The switch terminals voltage v of a upper time step (t-Δ t) and (t-Δ t) postpones a clock and reads, with output result A of data distributor switching current i₁、A₂Keep alignment of data, and same Time carry out multiplying by 2 Floating-Point Multipliers, obtain history amount I finally by floating-point adder device_h(t-Δ t), deposits Enter RAM_histIn, calculate for next time step.Work as N_PEIndividual electronic power switch element passes sequentially through history entries and solves module and carry out During process, the clock periodicity n of solution procedure_{H, PE}=15+(N_PE-1).It addition, the clock periodicity n of its renewal process_{U, PE}=21+ (N_PE-1)。

3rd step: under offline environment, calculates each class component history entries current source column vector described in the first step and is formed always Clock periodicity n needed for history entries current source column vector_hist, calculate and use parallel matrix-vector multiplication to realize linear equation The clock periodicity n that group solves_matrix；

Accompanying drawing 2 comprises total history entries current source column vector generation module and based on parallel matrix vector multiplication linear Solving equations module, its required clock periodicity is as described below.

In total history entries current source column vector generation module, need the history entries current source calculated according to each class component Column vector, total history entries current source is obtained in superposition.Superposition completes under fixed-point number numeral system in this process, needs to examine Worry floating number mutually changes, with fixed-point number, the clock cycle n consumed_convert, the clock periodicity of superposition is equal to matrix Dimension N_matrix, wherein floating number employs, with the mutually conversion of fixed-point number, the IP kernel that integrated translation and compiling environment carries, and it calculates clock Number n_convertIt is 6, the therefore clock periodicity n of this step_hist=2*n_convert+N_matrix。

Solving Linear is often part the most time-consuming in transient emulation, in order to reach to calculate faster speed, Ensureing emulation real-time, can prestore conductance matrix inverse matrix, shown in its computing formula such as formula (10).It is N for dimension_matrix Matrix, use N_matrixIndividual RAM stores, the data line of each RAM storage matrix.Now, system of linear equations can be asked Solution is converted into N_matrixIndividual can be parallel vector dot computing, as shown in formula (11).This module in accumulation process with circuit element Identical, repeat no more here, it calculates needs priority consider the mutually conversion of floating number multiplication, floating number and fixed-point number and determine Count cumulative, therefore its clock periodicity n_matrix=n_multiply+2n_convert.Module implementations as shown in Figure 8, by this Module can be calculated the instantaneous voltage value of each node.

v=YI_h, Y=G^-1 (10)

$\left[\begin{array}{c}{v}_1\\ v_2\\ ...\\ v_N\end{array}\right]=\begin{array}{c}\left[\begin{array}{cccc}{Y}_{\mathrm{1,1}}& Y_{\mathrm{1,2}}& ....& Y_{1,N}\\ Y_{\mathrm{2,1}}& Y_{\mathrm{2,2}}& ....& Y_{2,N}\\ ....& ....& ....& ....\\ Y_{N,1}& Y_{N,2}& ....& Y_{N,N}\end{array}\right]\left[\begin{array}{c}{I}_{h,1}\\ I_{h,2}\\ ....\\ I_{h,N}\end{array}\right]---\left(11\right)\end{array}$

Use double Resistance model for prediction to be simulated in view of chopper, when i.e. chopper disconnects, use the resistance that resistance is bigger Representing, during breaker closing, the resistance using resistance the least represents, circuit-breaker status change causes the change of system conductance matrix Change.Therefore in real-time simulation, all possible matrix structure is required for calculating in advance and storing to RAM, needs storage Calculating matrix number is 2^Nbreaker, wherein N_breakerFor chopper number, form state by the current state of each chopper Sequence, thus read corresponding conductance matrix inverse matrix.

4th step: under offline environment, as shown in Figure 2, the history entries current source row of each class component described in the first step Vector solves and updates the calculating and sending of step and carries out, and their clock periodicity that solves is determined, therefore by time-consuming elder Calculating the calculating clock cycle sum needed for the emulation of each step is n_total=max(n_{H, RLC}, n_{H, Line}, n_{H, SOURCE}, n_{H, BREAKER}, n_{H, PE}...) and+n_hist+n_matrix+max(n_{U, RLC}, n_{U, Line}, n_{U, SOURCE}, n_{U, BREAKER}, n_{U, PE}...) and+n_other, max letter Number expression takes maximum, n_otherRepresent the total clock cycle number of some scattered operations, such as the behaviour of systematic function module end signal Make；

5th step: under offline environment, according to drive clock frequency f and the clock cycle sum n of FPGA_total, obtain T actual time needed for each step emulates in 4th step_total, t_total=n_total/ f, sets simulation calculation step delta t, and Δ t need to expire Foot t_total< Δ t is to ensure emulation real-time；

6th step: under offline environment, according to the equivalent electric of each class component described in the simulation step length Δ t calculating first step Lead, form nodal-admittance matrix, history entries current source and update the meter needed for computing in all kinds of component models described in calculating Calculate parameter, calculate the inverse matrix of nodal-admittance matrix；

7th step: history entries current source and renewal fortune in the equivalent conductance that the 6th step has been obtained, all kinds of component models Imitative described in basic parameter information described in calculating parameter needed for calculation, the inverse matrix of nodal-admittance matrix, the first step, the 5th step True step delta t etc. is uploaded to in-circuit emulation environment based on FPGA；

The first step as above～the 7th step, complete under offline environment, and the simulation status in thread environment Control is realized by finite state machine, as shown in Figure 3, is provided with four kinds of running statuses and for every kind of state assignment one 3 bits represent, respectively idle condition (IDLE:000)；Simulation status one (STEP_I:001)；Simulation status two (STEP_II:010)；Simulation status three (STEP_III:100).

The operational process of this finite state machine is: emulator is initially in idle condition IDLE, when emulation commencing signal After Start draws high, system enters simulation status one STEP_I；After total history entries current source column vector generates, simulation status one End signal end_STEP_I puts 1, promotes emulation to enter simulation status two STEP_II；After Solving Linear completes, it is System draws high simulation status two end signal end_STEP_II, promotes emulation to enter simulation status three STEP_III；When emulation timing Device timing, to Δ t, draws high step-length end signal end_ Δ t, and this time step calculates and terminates, and promotes emulation to come back to simulation status one STEP_I also starts the emulation of next time step.Thus, real-time simulation is in simulation status one STEP_I, state two STEP_II, state Between three STEP_III tri-states, circulation advances, until emulation terminates.When reset signal Reset is drawn high, system can be returned again To idle condition.Idiographic flow is as described below.

8th step: under at thread environment, arranges emulation moment t=0, the emulation shape of finite state machine in global control module State is idle condition (IDLE), starts emulation；

9th step: under at thread environment, simulation status enters state one (STEP_I), and simulation timer starts timing, meter The history entries current source of the calculation each class component described in the first step, generates history entries current source column vector, wherein said all kinds of units The calculating of part is parallel, and respective end signal is set high level after completing by the calculating task of each class component；

Tenth step: under at thread environment, carries out logical AND operation to the end signal of each class component described in the 9th step, when This signal is high level, after the most all elements complete the calculating of history entries current source, and the history entries current source that all elements are generated Column vector combines, and obtains total history entries current source column vector I_h, and store, generate state one end signal (end_ STEP_I)；

11st step: under at thread environment, simulation status enters state two (STEP_II), according to circuit breaker switch state Read inverse matrix G of corresponding nodal-admittance matrix^-1, use parallel matrix-vector multiplication by inverse matrix G^-1And total history Item current source column vector I_hCalculate node voltage column vector v, generate state two end signal (end_STEP_II)；

12nd step: under at thread environment, simulation status enters state three (STEP_III), divides described each class component It is not updated computing, calculates terminal voltage and the branch current of each element, and store, wherein said each class component Update calculate be parallel；

13rd step: under at thread environment, simulation result user specified passes offline environment back, in order to Yong Hucha See；

14th step: under at thread environment, it is judged that when simulation timer whether timing is to Δ t, as met condition, then generate (end_ Δ t), otherwise emulator waits until timing is to Δ t step-length end signal；

15th step: judge whether simulation time reaches emulation and end the moment, ends the moment as reached emulation, then emulates knot Bundle, otherwise returns the 9th step.

The system framework that this method for designing proposes can give full play to the skill of FPGA hardware concurrency and pipelined architecture Art advantage, it is ensured that the real-time during whole system transient emulation, and for using less step-length accurately to solve active distribution The detailed dynamic process of net provides reliable basis.

Simulation status one (STEP_I) in heretofore described real-time simulation, simulation status two (STEP_II) and imitative The control scheduling of true state three (STEP_III), is realized by finite state machine.

The active power distribution network transient state real-time emulation system method for designing based on FPGA that the present invention proposes, belongs to power system Emulation field, is particularly well-suited to the real-time transient emulation of the active power distribution network containing distributed power source, energy storage device.The present invention proposes Active power distribution network transient state real-time emulation system RTDG (Real-Time Transient Simulator for based on FPGA Distributed Generation and Microgrid).Here enter as a example by European Union's low-voltage active power distribution network example system Row explanation, as shown in Figure 10, containing various lines and load type in system.Implement step and describe in detail as follows:

The first step: under offline environment, uses primary element to be modeled active power distribution network, reads the most passive unit The basic parameter information of all kinds of primary elements such as part, circuit element, source element, circuit breaker element, electronic power switch element, Statistics obtains the quantity of each class component, in this example, source element 3, basic passive element 42, circuit element 15, Circuit breaker element 1, electronic power switch element 0；

Second step: under offline environment, calculates basic passive element, circuit element, source element, circuit breaker element, electricity Clock cycle sum (the n that the history entries current source column vector of the elements such as power electrical switch solves_{H, RLC}, n_{H, LINE}, n_{H, SOURCE}, n_{H, BREAKER}, n_{H, PE}...) and the clock cycle sum (n of renewal step_{U, RLC}, n_{U, LINE}, n_{U, SOURCE}, n_{U, BREAKER}, n_{U, PE}...).N in this example_{H, RLC}=55, n_{H, LINE}=66, n_{H, SOURCE}=11, n_{H, BREAKER}=0, n_{H, PE}=0, n_{U, RLC}=62, n_{U, LINE}=77, n_{U, SOURCE}=13, n_{U, BREAKER}=22, n_{U, PE}=0；

3rd step: under offline environment, calculates each class component history entries current source column vector and forms total history entries current source Process clock periodicity n needed for column vector_hist, calculate use parallel matrix vector multiplication realize Solving Linear time Clock periodicity n_matrix；N in this example_matrix=67, n_hist=79, n_matrix=17；

4th step: under offline environment, calculating the total clock periodicity that calculates needed for the emulation of each step is n_total=max (n_{H, RLC}, n_{H, Line}, n_{H, SOURCE}, n_{H, BREAKER}, n_{H, PE}...) and+n_hist+n_matrix+max(n_{U, RLC}, n_{U, Line}, n_{U, SOURCE}, n_{U, BREAKER}, n_{U, PE}...) and+n_other, the history entries current source column vector of the most each class component solves and updates step Calculating and sending is carried out, and max function representation takes maximum, n_other=25, in this example, the n calculated according to formula_totalFor 264；

5th step: under offline environment, according to drive clock frequency f and the n of FPGA_total, obtain each step and calculate institute T actual time needed_total, t_total=n_total/ f, sets simulation calculation step delta t, and Δ t need to meet t_total< Δ t is to ensure emulation Real-time.In this example, clock frequency f is 135MHz, therefore t_totalBeing 1.956 μ s, Δ t is set as 2 μ s；

6th step: under offline environment, according to the equivalent electric of each class component described in the simulation step length Δ t calculating first step Lead, form nodal-admittance matrix, history entries current source and update the meter needed for computing in all kinds of component models described in calculating Calculate parameter, calculate the inverse matrix of nodal-admittance matrix；

7th step: history entries current source and renewal fortune in the equivalent conductance that the 6th step has been obtained, all kinds of component models Imitative described in basic parameter information described in calculating parameter needed for calculation, the inverse matrix of nodal-admittance matrix, the first step, the 5th step True step delta t is uploaded to in-circuit emulation environment based on FPGA；

8th step: under at thread environment, arranges emulation moment t=0, the emulation shape of finite state machine in global control module State is idle condition (IDLE), starts emulation；

9th step: under at thread environment, simulation status enters state one (STEP_I), and simulation timer starts timing, meter The history entries current source of the calculation each class component described in the first step, generates history entries current source column vector, wherein said all kinds of units The calculating of part is parallel, and respective end signal is set high level after completing by the calculating task of each class component；

Tenth step: under at thread environment, carries out logical AND operation to the end signal of each class component described in the 9th step, when This signal is high level, after the most all elements complete the calculating of history entries current source, and the history entries current source that all elements are generated Column vector combines, and obtains total history entries current source column vector I_h, and store, generate state one end signal (end_ STEP_I)；

11st step: under at thread environment, simulation status enters state two (STEP_II), according to circuit breaker switch state Read inverse matrix G of corresponding nodal-admittance matrix^-1, use parallel matrix-vector multiplication by inverse matrix G^-1And total history Item current source column vector I_hCalculate node voltage column vector v, generate state two end signal (end_STEP_II)；

12nd step: under at thread environment, simulation status enters state three (STEP_III), divides described each class component It is not updated computing, calculates terminal voltage and the branch current of each element, and store, wherein said each class component Update calculate be parallel；

13rd step: under at thread environment, simulation result user specified passes offline environment back, in order to Yong Hucha See；

14th step: under at thread environment, it is judged that when simulation timer whether timing is to Δ t, as met condition, then generate (end_ Δ t), otherwise emulator waits until timing is to Δ t step-length end signal；

15th step: judge whether simulation time reaches emulation and end the moment, ends the moment as reached emulation, then emulates knot Bundle, otherwise returns the 9th step.

The environment that performs of this example is altera corpIV GX FPGA530 official development board.Development board is joined Having Stratix IV Series FPGA EP4SGX530KH40C2N, this chip comprises 531200 logical blocks, and 212480 adaptive Answer logic module, 1280 M9K memorizeies, 64 M144K memorizeies, 1024 18x18 special multiplier, 8 PLL and 744 I/O.Except EP4SGX530KH40C2N chip, development board additionally provides the clock circuit of multiple frequency, and 3 users can Configuration button, a large amount of external memory storages, PCI Express slot, the peripheral circuit such as 10/100/1000Ethernet interface.

In terms of simulation velocity, the active power distribution network transient state real-time emulation system based on FPGA proposed by the present invention is set Meter method, it is possible to give full play to FPGA hardware concurrency and pipelined architecture, it is ensured that the real-time of whole system transient emulation； Accompanying drawing 11～12 compares the active power distribution network transient state real-time emulation system based on FPGA using the inventive method and imitates with business The simulation result of true software Matlab/SimPowerSystems.It can be seen in the drawings that Matlab/ The simulation result of SimPowerSystems can fit like a glove in stable state with transient process with the simulation result of FPGA, and two The dynamic response characteristic of person maintains highly consistent, has embodied good simulation accuracy, fully demonstrates what the present invention proposed Be suitable to the feasibility of the active power distribution network transient state real-time emulation system frame design method that FPGA realizes.

Above numerical testing proves, a kind of based on FPGA active power distribution network transient state real-time simulation that the present invention proposes Design method has preferable feasibility and the suitability, for realizing containing distributed power source, the active power distribution network of energy storage device Transient state real-time simulation provides a kind of well resolving ideas.

Claims (3)

1. an active power distribution network transient state real-time emulation system method for designing based on FPGA, it is characterised in that active power distribution network Transient state real-time emulation system is divided into off-line simulation environment and in-circuit emulation environment, and wherein off-line simulation environment is responsible for real-time simulation use Timet _totalCalculating, according to the real-time simulation used timet _totalSimulation step length Δ is sett, and will be according to simulation step length ΔtCalculate Relevant parameter and the basic parameter information read are uploaded to in-circuit emulation environment based on FPGA；In-circuit emulation environment completes The real-time calculating of emulation, including history entries current source column vector calculation, total history entries current source of class component each in each step-length Column vector is formed, Solving Linear and update step, specifically includes following steps:

The first step: under offline environment, uses primary element to be modeled active power distribution network, reads basic passive element, line Circuit component, source element, circuit breaker element, the basic parameter information of electronic power switch element, statistics obtains described all kinds of unit The quantity of part；

Second step: under offline environment, calculates basic passive element, circuit element, source element, circuit breaker element, electricity respectively The clock periodicity that the history entries current source column vector of power electronic switching element solves:n _h,RLC, n _h,LINE, n _h,SOURCE,n _h,BREAKER, n _h,PE, and update the clock periodicity of step:n _u,RLC, n _u,LINE, n _u,SOURCE, n _u,BREAKER, n _u,PE, its In,n _hRepresent the clock periodicity that history entries current source column vector solves, take the integer more than or equal to 0,n _uRepresent and update step Clock periodicity, takes the integer more than or equal to 0, and RLC represents basic passive element, and LINE represents that circuit element, SOURCE represent Source element, BREAKER represents that circuit breaker element, PE represent electronic power switch element；

3rd step: under offline environment, calculates each class component history entries current source column vector described in the first step and forms total history Clock periodicity needed for item current source column vectorn _hist, calculating uses parallel matrix-vector multiplication to realize system of linear equations and asks The clock periodicity solvedn _matrix；

4th step: under offline environment, the calculating clock cycle sum needed for calculating the emulation of each step isn _total=max(n _h,RLC,n _h,Line, n _h,SOURCE, n _h,BREAKER, n _h,PE)+ n _hist+ n _matrix+ max(n _u,RLC, n _u,Line, n _u,SOURCE, n _u,BREAKER,n _u,PE)+n _other, wherein the history entries current source column vector of each class component described in the first step solves and updates the calculating of step Concurrently carrying out, max function representation takes maximum,n _otherRepresent the total clock cycle number of some scattered operations；

5th step: under offline environment, according to the drive clock frequency of FPGAfAnd clock cycle sumn _total, obtain the 4th Each step real-time simulation used time in stept _total,t _total=n _total/f, set simulation calculation step deltat, ΔtNeed to meett _total<Δt To ensure emulation real-time；

6th step: under offline environment, according to simulation step length ΔtThe equivalent conductance of the calculating each class component described in the first step, shape Become nodal-admittance matrix, history entries current source and update the calculating ginseng needed for computing in all kinds of component models described in calculating Number, calculates the inverse matrix of nodal-admittance matrix；

7th step: history entries current source and renewal computing institute in the equivalent conductance that the 6th step has been obtained, all kinds of component models Basic parameter information described in the calculating parameter of need, the inverse matrix of nodal-admittance matrix, the first step, the step of the emulation described in the 5th step Long ΔtIt is uploaded to in-circuit emulation environment based on FPGA；

8th step: under at thread environment, arranges the emulation momentt=0, in global control module, the simulation status of finite state machine is Idle condition (IDLE), starts emulation；

9th step: under at thread environment, simulation status enters state one (STEP_I), and simulation timer starts timing, calculates the The history entries current source of each class component described in one step, generates history entries current source column vector, wherein said each class component Calculating is parallel, and respective end signal is set high level after completing by the calculating task of each class component；

Tenth step: under at thread environment, carries out logical AND operation to the end signal of each class component described in the 9th step, when this letter Number being high level, the most all elements complete after history entries current source calculates, the history entries current source that all elements are generated arrange to Amount combination, obtains total history entries current source column vectorI _h, and store, generate state one end signal (end_STEP_ I)；

11st step: under at thread environment, simulation status enters state two (STEP_II), reads according to circuit breaker switch state The inverse matrix of corresponding nodal-admittance matrixG ^-1, use parallel matrix-vector multiplication by inverse matrixG ^-1And total history entries electricity Stream source column vectorI _hCalculate node voltage column vectorv, generate state two end signal (end_STEP_II)；

12nd step: under at thread environment, simulation status enters state three (STEP_III), enters described each class component respectively Row updates computing, calculates terminal voltage and the branch current of each element, and stores, and wherein said each class component is more New calculating is parallel；

13rd step: under at thread environment, simulation result user specified passes offline environment back, in order to user checks；

14th step: under at thread environment, it is judged that whether timing is to Δ for simulation timertTime, as met condition, then generate step-length (end_ Δ t), otherwise emulator waits until timing is to Δ end signalt；

15th step: judge whether simulation time reaches emulation and end the moment, ends the moment as reached emulation, then emulation terminates, Otherwise return the 9th step.

Active power distribution network transient state real-time emulation system method for designing based on FPGA the most according to claim 1, its feature Being, the basic parameter information described in the first step includes: the basic resistance of passive element, inductance and capacitance parameter, circuit element Resistance and inductance matrix, the amplitude of source element, frequency and initial phase, the offresistance of circuit breaker element, closed resistance, The breaker actuation time, electronic power switch element represents the resistance of open circuit, electric capacity and represents the inductance of Guan Bi, each class component Node serial number, nodal-admittance matrix dimension.

A kind of active power distribution network transient state real-time emulation system method for designing based on FPGA, it is special Levy and be, simulation status one (STEP_I), simulation status two (STEP_II) and the simulation status three (STEP_ in real-time simulation III) control scheduling, is realized by finite state machine.