CN110266466B - Serial differential non-return-to-zero code identification method - Google Patents
Serial differential non-return-to-zero code identification method Download PDFInfo
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- CN110266466B CN110266466B CN201910560245.2A CN201910560245A CN110266466B CN 110266466 B CN110266466 B CN 110266466B CN 201910560245 A CN201910560245 A CN 201910560245A CN 110266466 B CN110266466 B CN 110266466B
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- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
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Abstract
The invention relates to a serial differential non-return-to-zero code identification method, based on the logical or non-operation result of two paths of differential signals corresponding to serial differential non-return-to-zero codes, a brand-new identification method is designed, each falling edge position of the result is taken as each starting mark position, the preset n times of the frequency of the serial differential non-return-to-zero codes is combined as the adopted clock frequency, the two paths of differential signals are respectively sampled, and then the data values corresponding to the serial differential non-return-to-zero codes are obtained by decoding, so that the identification of the serial differential non-return-to-zero codes can be realized by utilizing the sampling judgment and the storage of a digital circuit, and the control logic is simple and effective; the whole identification method is stable and reliable, has small errors, can correctly identify code values and output correct data only by simple falling edge judgment on each starting mark position for sampling, and has the characteristics of stable and reliable performance and small identification errors.
Description
Technical Field
The invention relates to a serial differential non-return-to-zero code identification method, and belongs to the technical field of serial code identification.
Background
The serial differential non-return-to-zero code is widely applied to civil and commercial fields all over the world, the signal of the system is most widely applied by the serial code, and the traditional identification mode of the serial differential non-return-to-zero code often brings larger errors in the processing of synchronization and identification and is more complicated to control.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a serial differential non-return-to-zero code identification method, which can realize identification of serial differential non-return-to-zero codes between external equipment and an application system with high accuracy.
The invention adopts the following technical scheme for solving the technical problems: the invention designs a serial differential non-return-to-zero code identification method, which comprises the following steps:
step A, aiming at two paths of differential signals corresponding to serial differential non-return-to-zero codes, carrying out logical NOR operation to obtain a signal S, and then entering step B;
b, acquiring the position of each falling edge in the signal S, taking each falling edge position as each starting mark position, and then entering the step C;
step C, sampling the two paths of differential signals respectively by using a clock frequency N from each starting mark position, obtaining differential sampling signals respectively corresponding to the two paths of differential signals after the sampling operation from each starting mark position is completed, and then entering the step D; the clock frequency N is equal to a preset N times of the serial differential non-return-to-zero code frequency;
and D, decoding the differential sampling signals respectively corresponding to the two paths of differential signals to obtain a decoded value, namely obtaining a data value corresponding to the serial differential non-return-to-zero code.
As a preferred technical solution of the present invention, the step B includes the steps of:
b1, delaying the signal S for a preset time length M to obtain a delayed signal S', and then entering a step B2; wherein M is equal to the reciprocal of a preset n times of the frequency of the serial differential non-return-to-zero code;
b2, sampling each falling edge in the signal S by adopting a clock frequency N, obtaining each pulse corresponding to the position between each falling edge in the signal S and the corresponding falling edge in the delay signal S', forming a mark signal F by each obtained pulse according to a time sequence, and then entering a step B3, wherein the clock frequency N is equal to the reciprocal of M;
and step B3, taking the rising edge of each pulse in the mark signal F as each starting mark position.
As a preferred technical scheme of the invention: n is more than or equal to 20.
As a preferred technical scheme of the invention: in the step D, the fault-tolerant control updating is performed on the differential sampling signals respectively corresponding to the two differential signals, and then the two updated differential sampling signals are decoded to obtain a decoded value, that is, a data value corresponding to the serial differential non-return-to-zero code is obtained.
As a preferred technical scheme of the invention: in the step D, firstly, validity verification and validity verification are respectively performed on the differential sampling signals respectively corresponding to the two paths of differential signals, and if the two paths of differential sampling signals are verified to be qualified, fault-tolerant control updating is further respectively performed on the two paths of differential sampling signals; and otherwise, if the two differential sampling signals have the condition of unqualified verification, the differential sampling signals corresponding to the two differential signals are respectively wrong.
As a preferred technical scheme of the invention: in the validity verification process, the number of the start marks in the mark signal F is counted, if the counting result is lower than the preset threshold of the number of the start marks, the serial differential non-return-to-zero code is judged to be illegal, and the serial differential non-return-to-zero code is discarded.
As a preferred technical scheme of the invention: and the threshold value of the number of the preset starting marks is equal to 5.
As a preferred technical scheme of the invention: the validity verification mode is a parity check mode.
Compared with the prior art, the serial differential non-return-to-zero code identification method has the following technical effects that:
the invention designs a brand-new identification method based on the logical or non-operation result of two paths of differential signals corresponding to serial differential non-return-to-zero codes, takes each falling edge position of the result as each starting mark position, combines preset n times of the frequency of the serial differential non-return-to-zero codes as the adopted clock frequency, respectively samples two paths of differential signals, and obtains the data value corresponding to the serial differential non-return-to-zero codes by decoding, so that the identification of the serial differential non-return-to-zero codes can be realized by utilizing the sampling judgment and the storage of a digital circuit, and the control logic is simple and effective; the whole identification method is stable and reliable, has small errors, can correctly identify code values and output correct data only by simple falling edge judgment on each starting mark position for sampling, and has the characteristics of stable and reliable performance and small identification errors; by using the method, the problem of correct identification of all serial differential non-return-to-zero codes can be thoroughly solved, the problem of false identification caused by nonstandard return-to-zero code duty ratio and the like can be effectively solved, and the purpose of correctly identifying the serial differential non-return-to-zero codes can be further achieved.
Drawings
FIG. 1 is a schematic flow chart of a serial differential NRZ code identification method according to the present invention;
FIG. 2 is a schematic diagram of two differential signals A, B corresponding to serial differential NRZ codes in the design application of the present invention;
FIG. 3 is a schematic diagram of a signal S obtained by performing a logical NOR operation on two differential signals in the application of the present invention;
FIG. 4 is a schematic illustration of a marker signal F obtained based on signal S in the design application of the present invention;
fig. 5 is a schematic diagram of sampling two differential signals respectively based on the flag signal F in the design and application of the present invention.
Detailed Description
The following description will explain embodiments of the present invention in further detail with reference to the accompanying drawings.
The invention designs a serial differential non-return-to-zero code identification method, in practical application, as shown in fig. 2, a serial differential non-return-to-zero code corresponds to two paths of differential signals, wherein when a differential signal A is at 1 and 0 levels, and a differential signal B is at 0 and 0 levels, the current bit is 1; when the differential signal a is at 0, 0 level, the differential signal B is at 1, 0 level, representing that the current bit is 0. According to the serial differential non-return-to-zero code identification method shown in fig. 1, the specific identification method comprises the following steps.
Step a, performing a logical nor operation on two paths of differential signals corresponding to the serial differential non-return-to-zero code, as shown in fig. 3, to obtain a signal S, and then entering step B.
And B, acquiring the position of each falling edge in the signal S, taking each falling edge position as each starting mark position, and then entering the step C.
In practical application, specifically for the step B, as shown in fig. 4, the design includes the following steps B1 to B3.
B1, delaying the signal S for a preset time length M to obtain a delayed signal S', and then entering a step B2; wherein M is equal to the inverse of a preset n times of the serial differential nrzi frequency.
And B2, sampling each falling edge in the signal S by adopting a clock frequency N respectively to obtain each pulse corresponding to the position between each falling edge in the signal S and the corresponding falling edge in the delay signal S', forming a mark signal F by each obtained pulse according to time sequence, and then entering the step B3, wherein the clock frequency N is equal to the reciprocal of M.
And step B3, taking the rising edge of each pulse in the mark signal F as each starting mark position.
Step C, as shown in FIG. 5, sampling the two paths of differential signals respectively by using a clock frequency N from each start mark position, obtaining differential sampling signals corresponding to the two paths of differential signals respectively after the sampling operation from each start mark position is completed, and then entering step D; the clock frequency N is equal to a preset N times of the serial differential non-return-to-zero code frequency, and N is designed to be larger than or equal to 20 in practical application.
And D, respectively carrying out validity verification and validity verification on the differential sampling signals respectively corresponding to the two paths of differential signals, if the two paths of differential sampling signals are verified to be qualified, further respectively carrying out fault-tolerant control updating on the two paths of differential sampling signals, and then decoding the two paths of updated differential sampling signals to obtain a decoded value, namely the data value corresponding to the serial differential non-return-to-zero code.
And otherwise, if the two differential sampling signals have the condition of unqualified verification, the differential sampling signals corresponding to the two differential signals are respectively wrong.
In practical application, in the validity verification process, the number of the start marks in the mark signal F is counted, if the counting result is lower than a preset start mark number threshold, it is determined that the serial differential non-return-to-zero code is illegal, the serial differential non-return-to-zero code is discarded, and the preset start mark number threshold is specifically designed to be equal to 5; as for the way of validity verification, a parity way may be specifically applied.
For the technical scheme of the serial differential non-return-to-zero code identification method, the requirement that the high-power sampling clock (20 times of the serial differential non-return-to-zero code frequency) and the serial differential non-return-to-zero code value are not deformed by more than 60 percent is needed, the high-power high-precision clock can meet the requirement of accurately sampling and generating the signal S, and the technical problems of mistaken identification and identification errors caused by the deformation of the serial non-return-to-zero code value due to interference and the like are effectively solved.
The serial differential non-return-to-zero code identification method is designed based on the logical or non-operation result of two paths of differential signals corresponding to the serial differential non-return-to-zero code, a brand-new identification method is designed, each falling edge position of the result is used as each starting mark position, the preset n times of the frequency of the serial differential non-return-to-zero code is combined to be used as the adopted clock frequency, the two paths of differential signals are respectively sampled, and then the data values corresponding to the serial differential non-return-to-zero code are obtained through decoding, so that the identification of the serial differential non-return-to-zero code can be realized by utilizing the sampling judgment and the storage of a digital circuit, and the control logic is simple and effective; the whole identification method is stable and reliable, has small errors, can correctly identify code values and output correct data only by simple falling edge judgment on each starting mark position for sampling, and has the characteristics of stable and reliable performance and small identification errors; by using the method, the problem of correct identification of all serial differential non-return-to-zero codes can be thoroughly solved, the problem of false identification caused by nonstandard return-to-zero code duty ratio and the like can be effectively solved, and the purpose of correctly identifying the serial differential non-return-to-zero codes can be further achieved.
The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.
Claims (7)
1. A serial differential non-return-to-zero code identification method is characterized by comprising the following steps:
step A, aiming at two paths of differential signals corresponding to serial differential non-return-to-zero codes, carrying out logical NOR operation to obtain a signal S, and then entering step B;
b, acquiring the position of each falling edge in the signal S, taking each falling edge position as each starting mark position, and then entering the step C;
the step B comprises the following steps:
b1, delaying the signal S for a preset time length M to obtain a delayed signal S', and then entering a step B2; wherein M is equal to the reciprocal of a preset n times of the frequency of the serial differential non-return-to-zero code;
b2, sampling each falling edge in the signal S by adopting a clock frequency N, obtaining each pulse corresponding to the position between each falling edge in the signal S and the corresponding falling edge in the delay signal S', forming a mark signal F by each obtained pulse according to a time sequence, and then entering a step B3, wherein the clock frequency N is equal to the reciprocal of M;
step B3, taking the rising edge of each pulse in the mark signal F as each starting mark position;
step C, sampling the two paths of differential signals respectively by using a clock frequency N from each starting mark position, obtaining differential sampling signals respectively corresponding to the two paths of differential signals after the sampling operation from each starting mark position is completed, and then entering the step D; the clock frequency N is equal to a preset N times of the serial differential non-return-to-zero code frequency;
and D, decoding the differential sampling signals respectively corresponding to the two paths of differential signals to obtain a decoded value, namely obtaining a data value corresponding to the serial differential non-return-to-zero code.
2. The serial differential non-return-to-zero code recognition method according to claim 1, characterized in that: n is more than or equal to 20.
3. The serial differential non-return-to-zero code recognition method according to claim 1, characterized in that: in the step D, the fault-tolerant control updating is performed on the differential sampling signals respectively corresponding to the two differential signals, and then the two updated differential sampling signals are decoded to obtain a decoded value, that is, a data value corresponding to the serial differential non-return-to-zero code is obtained.
4. The serial differential non-return-to-zero code recognition method according to claim 3, characterized in that: in the step D, firstly, validity verification and validity verification are respectively performed on the differential sampling signals respectively corresponding to the two paths of differential signals, and if the two paths of differential sampling signals are verified to be qualified, fault-tolerant control updating is further respectively performed on the two paths of differential sampling signals; and otherwise, if the two differential sampling signals have the condition of unqualified verification, the differential sampling signals corresponding to the two differential signals are respectively wrong.
5. The serial differential non-return-to-zero code recognition method according to claim 4, characterized in that: in the validity verification process, the number of the start marks in the mark signal F is counted, if the counting result is lower than the preset threshold of the number of the start marks, the serial differential non-return-to-zero code is judged to be illegal, and the serial differential non-return-to-zero code is discarded.
6. The serial differential non-return-to-zero code recognition method according to claim 5, characterized in that: and the threshold value of the number of the preset starting marks is equal to 5.
7. The serial differential non-return-to-zero code recognition method according to claim 4, characterized in that: the validity verification mode is a parity check mode.
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