CN110266313B - Two-step SAR ADC - Google Patents

Two-step SAR ADC Download PDF

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Publication number
CN110266313B
CN110266313B CN201910584930.9A CN201910584930A CN110266313B CN 110266313 B CN110266313 B CN 110266313B CN 201910584930 A CN201910584930 A CN 201910584930A CN 110266313 B CN110266313 B CN 110266313B
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flip
flop
dac
output
terminal
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CN110266313A (en
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周述
刘程斌
李天望
万鹏
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Hunan Goke Microelectronics Co Ltd
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Hunan Goke Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter

Abstract

The application discloses two-step SAR ADC includes: the output end of the first sampling unit and the output end of the second sampling unit are respectively connected with the input end of the first DAC and the input end of the second DAC, the output end of the first DAC and the output end of the second DAC are respectively connected with the input end of the comparator through the selection unit, the output end of the first DAC is further connected with the input end of the second DAC through the amplifier, the output end of the comparator is connected with the input end of the SAR Logic, and the output end of the SAR Logic is used for outputting Logic data. Obviously, compared with the prior art, the method and the device can use one less comparator, so that the space area and the energy consumption of the two-step SAR ADC are relatively reduced.

Description

Two-step SAR ADC
Technical Field
The invention relates to the technical field of power electronics, in particular to a two-step SAR ADC.
Background
Referring to fig. 1, fig. 1 is a structural diagram of a two-step SAR ADC in the prior art, where the two-step SAR ADC is composed of two SAR ADCs, a difference amplifier and digital Logic, the higher SAR ADC is composed of a DAC, a comparator and a SAR Logic, and the lower SAR ADC is composed of a DAC, a comparator and a SAR Logic. However, such a two-step SAR ADC requires more space area occupation and more energy consumption. At present, no effective solution exists for the technical problem.
Therefore, how to further reduce the space area occupation and the energy consumption of the two-step SAR ADC is an urgent technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention provides a two-step SAR ADC to reduce the space area occupation and energy consumption of the two-step SAR ADC. The specific scheme is as follows:
a two-step SAR ADC, comprising:
the device comprises a first DAC, a second DAC, an amplifier, a comparator, a SAR Logic, a first sampling unit for triggering the first DAC to sample, a second sampling unit for triggering the second DAC to sample, and a selection unit for switching on the first DAC and the comparator or switching on the second DAC and the comparator according to a preset rule;
the output end of the first sampling unit and the output end of the second sampling unit are respectively connected with the input end of the first DAC and the input end of the second DAC, the output end of the first DAC and the output end of the second DAC are respectively connected with the input end of the comparator through the selection unit, the output end of the first DAC is further connected with the input end of the second DAC through the amplifier, the output end of the comparator is connected with the input end of the SAR Logic, and the output end of the SAR Logic is used for outputting Logic data.
Preferably, the first sampling unit is specifically a first sampling switch, and the second sampling unit is specifically a second sampling switch.
Preferably, the first DAC and the second DAC are capacitive DACs.
Preferably, the first DAC has an output bit number of 2 M -1 MSB capacitor array, the second DAC having 2 output bits N -1 LSB capacitor array; wherein M is the number of output bits of the first DAC, and N is the number of output bits of the second DAC.
Preferably, the selection unit includes: a first switch for switching on the first DAC with the comparator or a second switch for switching on the second DAC with the comparator according to the preset rule;
correspondingly, the first output terminal and the second output terminal of the first sampling unit are respectively connected to the first input terminal and the second input terminal of the first DAC, the first output terminal and the second output terminal of the first DAC are respectively connected to the two input terminals of the first switch, the two output terminals of the first switch are respectively connected to the first input terminal and the second input terminal of the comparator, the first output terminal and the second output terminal of the first DAC are further respectively connected to the first input terminal and the second input terminal of the amplifier, the first output terminal and the second output terminal of the amplifier are respectively connected to the two input terminals of the second sampling unit, the first output terminal and the second output terminal of the second sampling unit are respectively connected to the first input terminal and the second input terminal of the second DAC, the first output terminal and the second output terminal of the second DAC are respectively connected to the two input terminals of the second switch, the two output terminals of the second switch are respectively connected to the two output terminals of the first switch, the two output terminals of the second switch are respectively connected to the first input terminal and the second input terminal of the comparator, the two output terminals of the second DAC are respectively connected to the Logic input terminal of the second DAC, the logical output data, the second output terminal of the third output terminal of the second DAC is connected to the logical output terminal of the logical output of the second DAC.
Preferably, the SAR Logic includes:
the first D flip-flop, the second D flip-flop, the third D flip-flop, the fourth D flip-flop, the fifth D flip-flop, the sixth D flip-flop, the seventh D flip-flop, the eighth D flip-flop, the ninth D flip-flop, the first NOT gate, the second NOT gate, the third NOT gate, the fourth NOT gate, the fifth NOT gate and the NAND gate;
correspondingly, the CLK end of the first D flip-flop, the CLK end of the second D flip-flop, the CLK end of the third D flip-flop, the CLK end of the fourth D flip-flop, the CLK end of the fifth D flip-flop, the CLK end of the sixth D flip-flop, the CLK end of the seventh D flip-flop, and the CLK end of the eighth D flip-flop are respectively connected to CLK, the rst end of the first D flip-flop, the rst end of the second D flip-flop, the rst end of the third D flip-flop, the rst end of the fourth D flip-flop, the rst end of the fifth D flip-flop, the rst end of the sixth D flip-flop, the rst end of the seventh D flip-flop, and the rst end of the eighth D flip-flop are respectively connected to the rst end of the ninth D flip-flop, the D end of the first D flip-flop is connected to VDD, and the Q end of the first D flip-flop is connected to the rst end of the second D flip-flop, the Q end of the second D flip-flop is connected with the D end of the third D flip-flop, the Q end of the third D flip-flop is connected with the D end of the fourth D flip-flop, the Q end of the fourth D flip-flop is connected with the D end of the fifth D flip-flop, the Q end of the fifth D flip-flop is connected with the D end of the sixth D flip-flop, the Q end of the sixth D flip-flop is connected with the D end of the seventh D flip-flop, the Q end of the seventh D flip-flop is connected with the D end of the eighth D flip-flop, the Q end of the first D flip-flop is further connected with the input end of the first NOT gate, the output end of the first NOT gate is connected with the first sampling unit, the Q end of the second D flip-flop is connected with the first CLK, the Q end of the third D flip-flop is connected with the second CLK, and the Q end of the fourth D flip-flop is connected with the first input end of the NAND gate, the Q end of the fifth D flip-flop is connected with the input end of the second not gate, the output end of the second not gate is connected with the second input end of the NAND gate, the output end of the NAND gate is connected with the input end of the third not gate, the output end of the third not gate is connected with the second sampling unit, the Q end of the sixth D flip-flop is connected with the third CLK, the Q end of the seventh D flip-flop is connected with the fourth CLK, the Q end of the eighth D flip-flop is connected with the input end of the fourth not gate, the output end of the fourth not gate is connected with the rst of the ninth D flip-flop, the CLK end of the ninth D flip-flop is connected with the input end of the third not gate, the D end of the ninth D flip-flop is connected with the first sampling unit, the Q end of the ninth flip-flop is connected with the first switch and the input end of the fifth not gate respectively, and the output end of the fifth not gate is connected with the second switch.
Preferably, the outputs of the first D flip-flop, the second D flip-flop, the third D flip-flop, the fourth D flip-flop, the fifth D flip-flop, the sixth D flip-flop, the seventh D flip-flop and the eighth D flip-flop in the reset state are all zero; the output of the ninth D trigger is 1 in a reset state; the output of the first sampling unit in the reset state is 1, and the output of the second sampling unit in the reset state is zero.
Preferably, the CLK is a clock signal in which the first to eighth triggered edges are active on a rising edge and the ninth triggered edge is active on a falling edge.
In the invention, firstly, the first DAC and the comparator are switched on by using the selection unit according to a preset rule, and under the condition that the second DAC and the comparator are switched off, the first sampling unit samples the input voltage of the first DAC, and then, the coarse conversion is carried out through the comparator and the SAR Logic; when the first DAC and the comparator are cut off by the selection unit and the second DAC and the comparator are turned on according to a preset rule, the second sampling unit samples the output voltage of the amplifier and performs fine conversion through the comparator and the SAR Logic. Obviously, the two-step SAR ADC provided by the invention only uses one comparator, and compared with the prior art, the two-step SAR ADC has the advantages that the space area occupation and the energy consumption of the two-step SAR ADC are relatively reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a block diagram of a prior art two-step SAR ADC;
fig. 2 is a structural diagram of a two-step SAR ADC according to an embodiment of the present invention;
fig. 3 is a block diagram of another two-step SAR ADC according to an embodiment of the present invention;
fig. 4 is a Logic structure diagram of an SAR Logic according to an embodiment of the present invention;
fig. 5 is a logic structure diagram of a two-step SAR ADC according to an embodiment of the present invention;
fig. 6 is a timing diagram of conversion of a two-step SAR ADC according to an embodiment of the present invention;
fig. 7 is a structural diagram of coarse conversion performed by the two-step SAR ADC according to the embodiment of the present invention;
fig. 8 is a structural diagram of a two-step SAR ADC for fine conversion according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a two-step SAR ADC according to an embodiment of the present invention performing a coarse conversion on a first bit and a second bit of 4-bit output data;
fig. 10 is a schematic diagram of a two-step SAR ADC according to an embodiment of the present invention performing a fine conversion on the third bit of the 4-bit output data;
fig. 11 is a schematic diagram of the two-step SAR ADC according to the embodiment of the present invention performing a fine conversion on the fourth bit of the 4-bit output data.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
Referring to fig. 2, fig. 2 is a structural diagram of a two-step SAR ADC according to an embodiment of the present invention, where the two-step SAR ADC specifically includes:
the device comprises a first DAC, a second DAC, an amplifier, a comparator, a SAR Logic, a first sampling unit for triggering the first DAC to sample, a second sampling unit for triggering the second DAC to sample, and a selection unit for switching on the first DAC and the comparator or switching on the second DAC and the comparator according to a preset rule;
the output end of the first sampling unit and the output end of the second sampling unit are respectively connected with the input end of the first DAC and the input end of the second DAC, the output end of the first DAC and the output end of the second DAC are respectively connected with the input end of the comparator through the selection unit, the output end of the first DAC is further connected with the input end of the second DAC through the amplifier, the output end of the comparator is connected with the input end of the SAR Logic, and the output end of the SAR Logic is used for outputting Logic data.
In the two-step SAR ADC provided in this embodiment, the first DAC and the second DAC may share one comparator by switching of the selection unit, that is, after the selection unit turns on the first DAC and the comparator according to the preset rule, the first DAC is in an operating state, and after the selection unit turns off the first DAC and the comparator according to the preset rule, and turns on the second DAC and the comparator, the first DAC is in an off state, and the second DAC is in an on state.
Specifically, when the first DAC is in an on state and the second DAC is in an off state, the first sampling unit samples the first DAC, and the comparator directly compares the input voltage of the first DAC to obtain a comparison value; and then, the second DAC carries out fine conversion on the output voltage of the amplifier, when the fine conversion is started, the first DAC and the comparator are cut off by the selection unit according to a preset rule, the second DAC and the comparator are switched on, and at the moment, the second sampling unit samples the output voltage of the amplifier and carries out fine conversion on the output voltage output by the amplifier through the comparator and the SAR Logic.
It is to be noted that, in the present embodiment, the emphasis is placed on the change of the connection structure in the two-step SAR ADC, and the process of performing the coarse conversion by the first DAC and performing the fine conversion by the second DAC is well known to those skilled in the art, so that detailed description thereof is omitted here.
It should be noted that, in practical application, the structural form of the first sampling unit and the second sampling unit may be any logic circuit with a trigger sampling function; the structure of the selection unit may be any logic circuit capable of implementing the switching function, and details are not described herein.
Obviously, the two-step SAR ADC provided by the present embodiment uses only one comparator, and compared with the prior art, the number of the comparators used is reduced, thereby relatively reducing the space occupation and the energy consumption of the two-step SAR ADC.
It can be seen that, in this embodiment, the first DAC and the comparator are firstly turned on by the selection unit according to the preset rule, and in the case of turning off the second DAC and the comparator, the first sampling unit samples the input voltage of the first DAC, and then, the coarse conversion is performed by the comparator and the SAR Logic; when the first DAC and the comparator are switched off and the second DAC and the comparator are switched on by the selection unit according to a preset rule, the second sampling unit samples the output voltage of the amplifier and performs fine conversion through the comparator and the SAR Logic. Obviously, the two-step SAR ADC provided by the embodiment only uses one comparator, and compared with the prior art, the two-step SAR ADC requires less comparator, so that the space area occupation and the energy consumption of the two-step SAR ADC are relatively reduced.
Based on the foregoing embodiments, this embodiment further describes and optimizes the technical solution, and as a preferred implementation, the first sampling unit is specifically a first sampling switch, and the second sampling unit is specifically a second sampling switch.
It will be appreciated that a wide variety of ways of sampling the first DAC and the second DAC can be implemented, such as: any logic circuit having a sampling function. Specifically, in this embodiment, the first sampling unit is set as a first sampling switch, and the second sampling unit is set as a second sampling switch. Because the structural style of the sampling switch is simpler, when the first sampling unit is set as the first sampling switch and the second sampling unit is set as the second sampling switch, the structural complexity of the two-step SAR ADC provided by the application can be reduced. In addition, the sampling switch has the advantage of low cost, so when the first sampling unit is set as the first sampling switch and the second sampling unit is set as the second sampling switch, the manufacturing cost of the two-step SAR ADC can be relatively reduced.
Based on the foregoing embodiments, the present embodiment further describes and optimizes the technical solution, and specifically, the structure types of the first DAC and the second DAC are specifically capacitive DACs.
Specifically, in this embodiment, the first DAC and the second DAC are configured as capacitive DACs, and the capacitive DACs have the advantages of low design cost, stable operation performance and reliability, so that when the first DAC and the second DAC are configured as capacitive DACs, not only the design cost of the two-step SAR ADC can be reduced, but also the overall reliability of the two-step SAR ADC during operation can be relatively improved.
In a preferred embodiment, the first DAC outputs a number of bits of 2 M MSB capacitor array of-1, second DAC for output bit number 2 N -1 LSB capacitor array;
where M is the number of output bits of the first DAC and N is the number of output bits of the second DAC.
Specifically, in the present embodiment, the first DAC is set to output a bit number of 2 M MSB capacitor array of-1, set second DAC to output bit number 2 N The LSB capacitor array of-1, so that the logic output with the output bit number of M + N can be obtained by using the first DAC and the second DAC, and the output precision of the two-step SAR ADC provided by the application is ensured.
In addition, it should be noted that the number of capacitors in the MSB capacitor array and the LSB capacitor array is related to the amplification factor of the amplifier, so in practical applications, the number of capacitors in the MSB capacitor array and the LSB capacitor array can be specifically set according to the amplification factor of the amplifier, which is well known to those skilled in the art and will not be described in detail herein. Moreover, compared with the traditional two-step SAR ADC, the structural manner provided by the embodiment can also reduce the number of capacitors in the capacitor array under the condition of converting the same number of bits.
Referring to fig. 3, fig. 3 is a structural diagram of another two-step SAR ADC according to an embodiment of the present invention. Based on the foregoing embodiments, this embodiment further describes and optimizes the technical solution, and specifically, the selecting unit includes: a first switch S1 for switching on the first DAC with the comparator according to a preset rule, or a second switch S2 for switching on the second DAC with the comparator;
correspondingly, the first output terminal and the second output terminal of the first sampling unit K1 are respectively connected to the first input terminal and the second input terminal of the first DAC, the first output terminal and the second output terminal of the first DAC are respectively connected to the two input terminals of the first switch S1, the two output terminals of the first switch S1 are respectively connected to the first input terminal and the second input terminal of the comparator, the first output terminal and the second output terminal of the first DAC are further respectively connected to the first input terminal and the second input terminal of the amplifier, the first output terminal and the second output terminal of the amplifier are respectively connected to the two input terminals of the second sampling unit K2, the first output terminal and the second output terminal of the second sampling unit K2 are respectively connected to the first input terminal and the second input terminal of the second DAC, the first output terminal and the second output terminal of the second DAC are respectively connected to the two input terminals of the second switch S2, the two output terminals of the second switch S2 are respectively connected to the two output terminals of the first switch S1, the two output terminals of the second switch S2 are also respectively connected to the first input terminal and the second input terminal of the Logic of the comparator, the SAR input terminal is connected to the third input terminal of the DAC, and the third input terminal of the second DAC is connected to the SAR input terminal of the second switch S2.
In the two-step SAR ADC disclosed in this embodiment, the first DAC and the second DAC share one comparator by turning on or off the first switch S1 and the second switch S2, that is, when the first DAC operates, the first switch S1 is in an on state, and the second switch S2 is in an off state; when the second DAC is operated, the first switch S1 is in an off state, and the second switch S2 is in an on state.
Specifically, when the first switch S1 is in an on state and the second switch S2 is in an off state, the first sampling unit K1 samples the input voltage of the first DAC, and the comparator directly compares the input voltage vip and vin of the first DAC to obtain a comparison value; after that, the second DAC performs a fine conversion on the output voltage of the amplifier, and when the fine conversion starts, the second sampling unit K2 samples the output voltage of the amplifier, and at the same time, the first switch S1 is in an off state and the second switch S2 is in an on state to perform the fine conversion on the output voltage of the amplifier.
In this embodiment, when the first switch is in an on state and the second switch is in an off state, the first sampling unit samples the input voltage of the first DAC, and then performs coarse conversion through the comparator and the SAR Logic; when the first switch is in an off state and the second switch is in an on state, the amplifier amplifies the voltage value output by the first DAC, and the second sampling unit samples the output voltage of the amplifier and performs fine conversion through the comparator and the SAR Logic. Obviously, with the two-step SAR ADC provided by the embodiment, only one comparator is used, and compared with the prior art, one less comparator is used, so that the space area occupation and the energy consumption of the two-step SAR ADC are relatively reduced.
Referring to fig. 4, fig. 4 is a structural diagram of a SAR Logic according to an embodiment of the present invention. Based on the above embodiments, this embodiment further describes and optimizes the technical solution, and specifically, the SAR Logic includes:
a first D flip-flop DFF1, a second D flip-flop DFF2, a third D flip-flop DFF3, a fourth D flip-flop DFF4, a fifth D flip-flop DFF5, a sixth D flip-flop DFF6, a seventh D flip-flop DFF7, an eighth D flip-flop DFF8, a ninth D flip-flop DFF9, a first not gate, a second not gate, a third not gate, a fourth not gate, a fifth not gate, and a nand gate;
wherein the CLK end of the first D flip-flop DFF1, the CLK end of the second D flip-flop DFF2, the CLK end of the third D flip-flop DFF3, the CLK end of the fourth D flip-flop DFF4, the CLK end of the fifth D flip-flop DFF5, the CLK end of the sixth D flip-flop DFF6, the CLK end of the seventh D flip-flop DFF7 and the CLK end of the eighth D flip-flop DFF8 are respectively connected with CLK, the rst end of the first D flip-flop DFF1, the rst end of the second D flip-flop DFF2, the rst end of the third D flip-flop DFF3, the rst end of the fourth D flip-flop DFF4, the rst end of the fifth D flip-flop DFF5, the rst end of the sixth D flip-flop DFF6, the rst end of the seventh D flip-flop DFF7 and the rst end of the eighth D flip-flop DFF8 are respectively connected with the ninth D flip-flop DFF9, the second D flip-flop D end of the D flip-flop DFF2 is connected with the D flip-flop DFF 2D flip-flop DFF3, and the D end of the second D flip-flop DFF2, the D flip-flop DFF3 is connected with the D2D flip-flop D3, the Q terminal of the third D flip-flop DFF3 is connected to the D terminal of the fourth D flip-flop DFF4, the Q terminal of the fourth D flip-flop DFF4 is connected to the D terminal of the fifth D flip-flop DFF5, the Q terminal of the fifth D flip-flop DFF5 is connected to the D terminal of the sixth D flip-flop DFF6, the Q terminal of the sixth D flip-flop DFF6 is connected to the D terminal of the seventh D flip-flop DFF7, the Q terminal of the seventh D flip-flop DFF7 is connected to the D terminal of the eighth D flip-flop DFF8, the Q terminal of the first D flip-flop DFF1 is further connected to the input terminal of the first not gate, the output terminal of the first not gate is connected to the first sampling unit K1, the Q terminal of the second D flip-flop DFF2 is connected to the first CLK, the Q terminal of the third D flip-flop f3 is connected to the second CLK, the Q terminal of the fourth D flip-flop DFF4 is connected to the first input terminal of the nand gate, the fifth D flip-flop DFF5 is connected to the second input terminal of the Q gate, the Q terminal of the second nand gate is connected to the second input terminal of the nand gate, the output end of the NAND gate is connected with the input end of the third NOT gate, the output end of the third NOT gate is connected with the second sampling unit K2, the Q end of the sixth D flip-flop DFF6 is connected with the third CLK, the Q end of the seventh D flip-flop DFF7 is connected with the fourth CLK, the Q end of the eighth D flip-flop DFF8 is connected with the input end of the fourth NOT gate, the output end of the fourth NOT gate is connected with the rst of the ninth D flip-flop DFF9, the Q end of the ninth D flip-flop DFF9 is connected with the input end of the third NOT gate, the D end of the ninth D flip-flop DFF9 is connected with the first sampling unit K1, the Q end of the ninth flip-flop is connected with the input ends of the first switch S1 and the fifth NOT gate respectively, and the output end of the fifth NOT gate is connected with the second switch S2.
In this embodiment, a specific Logic structure of the SAR Logic is provided, that is, a specific implementation process of the SAR Logic is used to cooperate with the first DAC to perform coarse conversion and the second DAC to perform fine conversion. It should be noted that, in practical applications, the D flip-flop may also be set as another type of flip-flop as long as the practical application purpose can be achieved.
Referring to fig. 5, fig. 5 is a logic structure diagram of a two-step SAR ADC according to an embodiment of the present invention. In the two-step SAR ADC, the first DAC is set as a capacitive DAC having an output bit number of 4 bits, and the second DAC is set as a capacitive DAC having an output bit number of 4 bits. In the two-step SAR ADC shown in fig. 5, the first sampling unit K1 samples the first DAC, the second sampling unit K2 samples the second DAC, and at the same time, the on-state or off-state of the first DAC and the second DAC is controlled by turning on or off the first switch S1 and the second switch S2.
Specifically, the outputs of the first D flip-flop DFF1, the second D flip-flop DFF2, the third D flip-flop DFF3, the fourth D flip-flop DFF4, the fifth D flip-flop DFF5, the sixth D flip-flop DFF6, the seventh D flip-flop DFF7, and the eighth D flip-flop DFF8 in the reset state are all zero; the output of the ninth D flip-flop DFF9 in the reset state is 1; the output of the first sampling unit K1 in the reset state is 1, and the output of the second sampling unit K2 in the reset state is zero.
In order to ensure the implementability of the SAR Logic in the actual use process, initial states of a first D flip-flop DFF1, a second D flip-flop DFF2, a third D flip-flop DFF3, a fourth D flip-flop DFF4, a fifth D flip-flop DFF5, a sixth D flip-flop DFF6, a seventh D flip-flop DFF7 and an eighth D flip-flop DFF8 in the SAR Logic are also set in advance. Specifically, in this embodiment, the outputs of the first D flip-flop DFF1, the second D flip-flop DFF2, the third D flip-flop DFF3, the fourth D flip-flop DFF4, the fifth D flip-flop DFF5, the sixth D flip-flop DFF6, the seventh D flip-flop DFF7, and the eighth D flip-flop DFF8 in the reset state are all set to zero, the output of the first sampling unit K1 in the reset state is set to 1, and the output of the second sampling unit K2 in the reset state is set to zero. The first switch S1 and the second switch S2 are turned on when the control signal is 1, and the first switch S1 and the second switch S2 are turned off when the control signal is zero. Thus, when the CLK receives the trigger signal, the SAR Logic can perform coarse conversion and fine conversion in cooperation with the first DAC and the second DAC, and thus realize corresponding data conversion.
Specifically, CLK is a clock signal in which the first to eighth active edges are active on the rising edge and the ninth active edge is active on the falling edge.
In the embodiment, the CLK is set to be a clock signal in which the first to eighth triggered edges are active as rising edges and the ninth triggered edge is active as falling edge; in practical applications, CLK may also be set to a clock signal in which the first to eighth active edges are active on the falling edge and the ninth active edge is active on the rising edge.
Referring to fig. 6, fig. 6 is a conversion timing diagram of a two-step SAR ADC according to an embodiment of the present invention. In this embodiment, a specific description will be given by taking an example in which the first DAC is set to 4 bits and the second DAC is set to 4 bits. In this embodiment, it is assumed that the outputs of the first D flip-flop DFF1, the second D flip-flop DFF2, the third D flip-flop DFF3, the fourth D flip-flop DFF4, the fifth D flip-flop DFF5, the sixth D flip-flop DFF6, the seventh D flip-flop DFF7, and the eighth D flip-flop DFF8 in the reset state are all zero; the output of the ninth D flip-flop DFF9 in the reset state is 1; the output of the first sampling unit K1 in the reset state is 1, and the output of the second sampling unit K2 in the reset state is zero.
When the first sampling unit K1 samples the input voltage of the first DAC, and when the first rising edge of the clock signal CLK arrives, the first sampling unit K1 becomes zero, at this time, the sampling is finished, and simultaneously, the voltage across the comparator is divided into vip and vin, and the comparator directly compares the vip and vin to obtain a comparison value. When the second rising edge of the clock signal CLK comes, the first CLK changes from zero to 1, and meanwhile, the first CLK latches the first comparison result of the comparator to obtain the value of the highest bit of the SAR ADC. Simultaneously, the first DAC operates to enable the comparator to carry out second comparison, when the third rising edge of the CLK comes, the second CLK is changed from zero to 1, and meanwhile, the second CLK latches the second comparison result of the comparator to obtain the second highest bit value of the SAR ADC; at the same time, the first DAC is operated, the comparator performs the third comparison, and when the fourth rising edge of CLK comes, the second sampling unit K2 changes from zero to 1, at which time the second sampling unit S2 samples the output of the amplifier, and at the same time, the first switch S1 changes from 1 to zero, and the second switch changes from zero to 1. When the fifth rising edge of CLK comes, the second sampling unit K2 changes from 1 to zero, and the sampling ends.
After that, the SAR ADC performs a fine conversion, when the sixth rising edge of CLK comes, the third CLK becomes 1 from zero, and the third CLK latches the third comparison result of the comparator to obtain the value of the next bit of the SAR ADC, and at the same time, the first DAC operates so that the comparator performs the fourth comparison. When the seventh rising edge of the CLK comes, the fourth CLK changes from zero to 1, and the fourth CLK latches the fourth comparison result of the comparator to obtain the value of the last bit of the SAR ADC, so far, a 4-bit conversion process is finished, and when the eighth rising edge of the CLK comes, all the D flip-flops are reset.
Therefore, by the technical scheme provided by the embodiment, the implementability of the SAR Logic in practical application is ensured, and the overall reliability of the two-step SAR ADC in the using process is relatively ensured.
Based on the disclosure of the above embodiments, the present embodiment explains the working principle of the two-step SAR ADC. Referring to fig. 7, fig. 7 is a structural diagram of the coarse conversion of the two-step SAR ADC according to the embodiment of the present invention. In the embodiment, the first DAC is set as an MSB capacitor array with an output bit number of 4 bits, the first sampling unit K1 is used to sample the first DAC, and the first switch S1 is used to control the on/off states of the first DAC and the comparator.
When the coarse conversion starts, the first sampling unit K1 is closed, the first switch S1 is closed, at this time, the first sampling unit K1 samples the input voltage of the first DAC, and after the sampling of the first sampling unit K1 is completed, in the first DAC formed by the MSB capacitor array, the lower plates of all capacitors are connected to vref, which is denoted by 1 in this embodiment, and at the same time, the upper plate of the capacitor at the upper half of the first DAC is vip and the upper plate of the capacitor at the lower half of the first DAC is vin.
At this time, the comparator directly compares the magnitudes of vip and vin; when vip is more than vin, the output of the comparator is high potential, namely, the highest bit of the two-step SAR ADC is 1; when vip is less than vin, the output of the comparator is low potential, namely, the highest bit of the two-step SAR ADC is zero; in addition, when vip > vin, the comparator output is 1, SAR logic changes the voltage of the highest bit capacitor of the upper half from vref to zero, and at this time, the positive input voltage of the comparator is changed from vip to vip-0.5vref; when vip < vin, the output of the comparator is zero, SAR logic changes the voltage of the capacitor at the highest bit in the lower half from vref to zero, and the negative input voltage of the comparator changes from vin to vip-0.5vref.
Then, the comparator compares vip-0.5vref and vin, if vip-0.5vref > vin, the comparator outputs a high potential, that is, the second highest bit of the two-step SAR ADC is 1, at this time, SAR Logic changes the voltage of the first half capacitor from vref to zero, at this time, the voltage at the positive input end of the comparator changes from vp to vip-0.5vref, and the voltage vn at the negative input end of the comparator remains unchanged; if vip-0.5vref < vin, the comparator outputs a low level, i.e., the second highest level of the two-step SAR ADC is zero, at this time, SAR Logic changes the voltage of the capacitor in the lower half from vref to zero, the voltage of the positive input terminal of the comparator keeps vp constant and is vip-0.5vref, and the voltage of the negative input terminal of the comparator changes from vn to vin-0.25vref. At this point, the coarse conversion is over, and the voltage difference across the comparator is: vp-vn = vip-vin-0.75vref, and the output voltage of the amplifier is 4 × (vp-vn) =4 (vip-vin-0.75 vref) =4 (vip-vin) -3vref at this time.
Then, the two-step SAR ADC performs fine conversion, please refer to fig. 8, where fig. 8 is a structural diagram of the two-step SAR ADC performing fine conversion according to the embodiment of the present invention; at this time, the second sampling unit K2 samples the output voltage of the amplifier, and at the same time, the first switch S1 is turned off, and the second switch S2 is turned on. Then, the whole conversion flow of 4 bits is as shown in fig. 9, fig. 10 and fig. 11.
Referring to fig. 9, fig. 9 is a schematic diagram of the two-step SAR ADC according to the embodiment of the present invention performing the coarse conversion on the first bit and the second bit of the 4-bit output data, where first, when the two-step SAR ADC performs the coarse conversion, the highest bit is 1 or 0, that is, at this time, the two-step SAR ADC outputs 1xxx and 0xxx, and then, the two-step SAR ADC performs the coarse conversion on the next bit, at this time, the next higher bit also has two output situations, that is, the next higher bit also outputs 1 or 0, that is, at this time, the two-step SAR ADC outputs 11xx, 10xx, 01xx, and 00xx.
And then, through time sequence control, the first switch S1 is turned off, the second switch S2 is turned on, and at the moment, the second sampling unit K2 samples the output of the amplifier and performs fine conversion. Referring to fig. 10, fig. 10 is a schematic diagram illustrating a fine conversion of the third bit of the 4-bit output data by the two-step SAR ADC according to the embodiment of the present invention; at this time, 01xx is converted to 011x and 010x,00xx is converted to 001x and 000x,11xx is converted to 111x and 110x, and 10xx is converted to 101x and 100x. Referring to fig. 11, fig. 11 is a schematic diagram of the two-step SAR ADC according to the embodiment of the present invention performing a fine conversion on the fourth bit of the 4-bit output data. At this time, 011x is converted into 0111 and 0100, 010x is converted into 0101 and 0100, 001x is converted into 0011 and 0010, and 000x is converted into 0001 and 0000;111x would be converted to 1111 and 1110, 110x would be converted to 1101 and 1100, 101x would be converted to 1011 and 1010, and 100x would be converted to 1001 and 1000.
Therefore, the two-step SAR ADC completes the whole data conversion process of the 4-bit output data, and obviously, compared with the two-step SAR ADC in the prior art, the two-step SAR ADC provided by the embodiment uses one less comparator, so that the space area occupation and the energy consumption of the two-step SAR ADC can be relatively reduced. Moreover, the two-step SAR ADC provided by the present embodiment can also relatively increase the conversion speed when converting data.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. For the disclosure of other embodiments, the descriptions of the embodiments can be referred to each other, so the descriptions are simple, and the relevant points can be referred to each other.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
The two-step SAR ADC provided by the present invention is described in detail above, and the principle and the implementation of the present invention are explained in the present document by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (8)

1. A two-step SAR ADC, comprising:
the device comprises a first DAC, a second DAC, an amplifier, a comparator, a SAR Logic, a first sampling unit for triggering the first DAC to sample, a second sampling unit for triggering the second DAC to sample and a selection unit for switching on the first DAC and the comparator or switching on the second DAC and the comparator according to a preset rule;
the output end of the first sampling unit and the output end of the second sampling unit are respectively connected with the input end of the first DAC and the input end of the second DAC, the output end of the first DAC and the output end of the second DAC are respectively connected with the input end of the comparator through the selection unit, the output end of the first DAC is further connected with the input end of the second DAC through the amplifier, the output end of the comparator is connected with the input end of the SAR Logic, and the output end of the SAR Logic is used for outputting Logic data.
2. The two-step SAR ADC according to claim 1, wherein the first sampling unit is specifically a first sampling switch and the second sampling unit is specifically a second sampling switch.
3. The two-step SAR ADC of claim 1, wherein the first DAC and the second DAC are of a capacitive type.
4. The two-step SAR ADC of claim 3 wherein said first DAC has an output bit number of 2 M -1 MSB capacitor array, the second DAC having 2 output bits N -1 LSB capacitor array; wherein M is the number of output bits of the first DAC, and N is the number of output bits of the second DAC.
5. The two-step SAR ADC according to any one of claims 1 to 4, wherein the selection unit comprises: a first switch for turning on the first DAC with the comparator or a second switch for turning on the second DAC with the comparator according to the preset rule;
correspondingly, the first output terminal and the second output terminal of the first sampling unit are respectively connected to the first input terminal and the second input terminal of the first DAC, the first output terminal and the second output terminal of the first DAC are respectively connected to the two input terminals of the first switch, the two output terminals of the first switch are respectively connected to the first input terminal and the second input terminal of the comparator, the first output terminal and the second output terminal of the first DAC are further respectively connected to the first input terminal and the second input terminal of the amplifier, the first output terminal and the second output terminal of the amplifier are respectively connected to the two input terminals of the second sampling unit, the first output terminal and the second output terminal of the second sampling unit are respectively connected to the first input terminal and the second input terminal of the second DAC, the first output terminal and the second output terminal of the second DAC are respectively connected to the two input terminals of the second switch, the two output terminals of the second switch are respectively connected to the two output terminals of the first switch, the two output terminals of the second switch are respectively connected to the first input terminal and the second input terminal of the comparator, the Logic input terminal of the second DAC is connected to the third input terminal of the second DAC, and the Logic output data.
6. The two-step SAR ADC of claim 5, wherein the SAR Logic comprises:
the first D flip-flop, the second D flip-flop, the third D flip-flop, the fourth D flip-flop, the fifth D flip-flop, the sixth D flip-flop, the seventh D flip-flop, the eighth D flip-flop, the ninth D flip-flop, the first NOT gate, the second NOT gate, the third NOT gate, the fourth NOT gate, the fifth NOT gate and the NAND gate;
correspondingly, the CLK end of the first D flip-flop, the CLK end of the second D flip-flop, the CLK end of the third D flip-flop, the CLK end of the fourth D flip-flop, the CLK end of the fifth D flip-flop, the CLK end of the sixth D flip-flop, the CLK end of the seventh D flip-flop, and the CLK end of the eighth D flip-flop are respectively connected to CLK, the rst end of the first D flip-flop, the rst end of the second D flip-flop, the rst end of the third D flip-flop, the rst end of the fourth D flip-flop, the rst end of the fifth D flip-flop, the rst end of the sixth D flip-flop, the rst end of the seventh D flip-flop, and the rst end of the eighth D flip-flop are respectively connected to the rst end of the ninth D flip-flop, the D end of the first D flip-flop is connected to VDD, and the Q end of the first D flip-flop is connected to the D end of the second D flip-flop, the Q end of the second D flip-flop is connected with the D end of the third D flip-flop, the Q end of the third D flip-flop is connected with the D end of the fourth D flip-flop, the Q end of the fourth D flip-flop is connected with the D end of the fifth D flip-flop, the Q end of the fifth D flip-flop is connected with the D end of the sixth D flip-flop, the Q end of the sixth D flip-flop is connected with the D end of the seventh D flip-flop, the Q end of the seventh D flip-flop is connected with the D end of the eighth D flip-flop, the Q end of the first D flip-flop is further connected with the input end of the first NOT gate, the output end of the first NOT gate is connected with the first sampling unit, the Q end of the second D flip-flop is connected with the first CLK, the Q end of the third D flip-flop is connected with the second CLK, and the Q end of the fourth D flip-flop is connected with the first input end of the NAND gate, the Q terminal of the fifth D flip-flop is connected to the input terminal of the second not gate, the output terminal of the second not gate is connected to the second input terminal of the nand gate, the output terminal of the nand gate is connected to the input terminal of the third not gate, the output terminal of the third not gate is connected to the second sampling unit, the Q terminal of the sixth D flip-flop is connected to the third CLK, the Q terminal of the seventh D flip-flop is connected to the fourth CLK, the Q terminal of the eighth D flip-flop is connected to the input terminal of the fourth not gate, the output terminal of the fourth not gate is connected to the rst of the ninth D flip-flop, the CLK terminal of the ninth D flip-flop is connected to the input terminal of the third not gate, the D terminal of the ninth D flip-flop is connected to the first sampling unit, the Q terminal of the ninth D flip-flop is connected to the input terminals of the first switch and the fifth not gate, and the output terminal of the fifth not gate is connected to the second switch.
7. The two-step SAR ADC of claim 6, wherein the outputs of the first D flip-flop, the second D flip-flop, the third D flip-flop, the fourth D flip-flop, the fifth D flip-flop, the sixth D flip-flop, the seventh D flip-flop, and the eighth D flip-flop in the reset state are all zero; the output of the ninth D trigger is 1 in a reset state; the output of the first sampling unit in the reset state is 1, and the output of the second sampling unit in the reset state is zero.
8. The two-step SAR ADC of claim 7, wherein the CLK is a clock signal in which a first to eighth triggering edge is active on a rising edge and a ninth triggering edge is active on a falling edge.
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