CN110265346A - The processing method of wafer - Google Patents
The processing method of wafer Download PDFInfo
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- CN110265346A CN110265346A CN201910471444.6A CN201910471444A CN110265346A CN 110265346 A CN110265346 A CN 110265346A CN 201910471444 A CN201910471444 A CN 201910471444A CN 110265346 A CN110265346 A CN 110265346A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Manufacturing & Machinery (AREA)
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- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The present invention provides a kind of new wafer processing method, by attaching support membrane to the ultra-thin wafers back side after being thinned, so that the support membrane is combined together with the ultra-thin wafers, thus redistributes to the internal stress of ultra-thin wafers, reduce fragmentation risk.After being cut into chip, support membrane is still integrated with chip, improves fragment problems of the chip in the encapsulation process such as subsequent patch, routing.
Description
Technical field
The present invention relates to wafer processing techniques fields, more particularly to be thinned after ultra-thin wafers cutting, transfer and encapsulation
Support protection technique in process.
Background technique
In recent years, flexible electronic technology becomes research hotspot.So-called flexible electronic is by organic or inorganic material electronics member
Part is produced on the new electronic technology on flexible Drawability plastics or thin metal matrix plate.It is flexible compared with conventional electronics
Electric requirements chip has certain curved surface adaptability, and it is thin as far as possible that this requires chips, and to have certain bendability.
In relation to studies have shown that 300 μm of thickness thinning or more of wafer can not be bent with absolute rigidity；It is thinned
Wafer of the thickness in 100~300 μ ms has apparent rigidity, is deteriorated, shifted as thickness reduces mechanical stability
It is easy to happen in journey broken；The wafer that thickness thinning is contracted in 50~100 μ ms starts have flexible ability, but still belongs to
In rigidity, bending deformation quantity easily ruptures when being more than a certain amount of；Ultra-thin wafers only when thickness thinning is lower than 50 μm
With good flexible bending ability.Therefore, preparation is lower than the ultra-thin wafers of 50 μ m thicks, becomes conventional semiconductor chip soft
The key factor applied in property electronic technology.
However, being 50 μm of flexible chips below for thickness thinning, due to its very thin thickness and without supporter, warpage becomes
Shape is very big, is easy to happen breakage in pickup and fitting, causes to encapsulate yield reduction.Therefore, for thickness thinning be 50 μm with
Under flexible chip, the transfer between process can not be carried out using conventional method.
Summary of the invention
In view of this, it is necessary to provide the wafer processing method in the cutting and encapsulation process of a kind of new ultra-thin wafers,
The pickup for improving ultra-thin wafers and the yield during fitting.
The present invention provides a kind of wafer processing method, includes the following steps: to provide original wafer, including picture surface and opposite
The back side, which has the chip design that is separated by Cutting Road；Protective film is attached on the surface of the chip design；To the original
The back side of beginning wafer carries out thinning operation, obtains ultra-thin wafers；Support membrane is attached at the back side of the ultra-thin wafers；Removal protection
Film；Dicing tape is attached on the surface of the support membrane；The ultra-thin wafers are cut along the Cutting Road of picture surface；And core
Piece separation.
According to one embodiment of present invention, which includes corase grinding, fine grinding and polishing treatment.
According to one embodiment of present invention, the ultra-thin wafers with a thickness of 15-50 μm.
According to one embodiment of present invention, the mode of the attaching of support membrane is the mode with the taut patch of cutting iron hoop.
It according to one embodiment of present invention, further include the step that extra support membrane is cut off along the center of the cutting iron hoop
Suddenly, before cutting off, corresponding blade running track is set according to the size of cutting iron hoop and cuts film angle, and according to support membrane
Film speed is cut in property adjustment.It is 90 ° that this, which cuts film angle, and cutting film speed is 15-20 °/s.
According to one embodiment of present invention, which includes organic film, gluing oxidant layer and release film layer, should be from
Type film layer is removed before the back side for attaching to the ultra-thin wafers.
According to one embodiment of present invention, the material of the organic film is solid polyimides, polyurethane or poly- two
Methylsiloxane.
According to one embodiment of present invention, when cutting to the ultra-thin wafers, the ultra-thin wafers and the branch are penetrated
Support film.
In the application, by with silicon face will there is the support membrane of strong adhesion strength to be attached to backside of wafer, with ultra-thin wafers
Adherency is integrated, so that protective film/wafer double-layer structure of script becomes protective film/wafer/support membrane sandwich structure,
Wafer is caught in the middle in this way, and support membrane can redistribute the internal stress of ultra-thin wafers after being thinned, in this way can be with
It is effectively improved the stress distribution of chip, internal stress is reduced, to reduce the risk of fragmentation.In addition, ultra-thin wafers are cut into core
After piece, support membrane is still integrated with chip, and to the supporting role of chip, there are still also further improve chip rear in this way
Fragment problems in the encapsulation process such as continuous patch, routing.
The above description is only an overview of the technical scheme of the present invention, in order to better understand the technical means of the present invention,
And it can be implemented in accordance with the contents of the specification, and in order to allow above and other objects, features and advantages of the invention can
It is clearer and more comprehensible, special below to lift preferred embodiment, detailed description are as follows.
Detailed description of the invention
Fig. 1 is wafer processing method schematic diagram of the invention；
Fig. 2 is the structural schematic diagram of original wafer；
Fig. 3 is the structural schematic diagram in the picture surface attaching protective film of original wafer；
Fig. 4 is the structural schematic diagram after original wafer in Fig. 3 is thinned；
Fig. 5 is the schematic diagram that support membrane is attached to the back side of ultra-thin wafers in Fig. 4；
Fig. 6 is the structural schematic diagram of support membrane in Fig. 5；
Fig. 7 is the schematic diagram that support membrane extra in Fig. 5 is cut off along cutting iron hoop center；
Fig. 8 is the schematic diagram that ultra-thin wafers shown in Fig. 7 are overturn to 180 °；
Fig. 9 is the protective film schematic diagram removed in Fig. 8；
Figure 10 is that the ultra-thin wafers of Fig. 9 are overturn to 180 ° and attach dicing tape in the support film surface of the ultra-thin wafers
Schematic diagram；
Figure 11 is to overturn the ultra-thin wafers of Figure 10 so that the face-up schematic diagram of figure；
Figure 12 is the schematic diagram that the ultra-thin wafers of Figure 11 are cut into individual chip；
Figure 13 is the schematic diagram that a certain chip in Figure 12 is separated from the dicing tape；
Figure 14 is that will be fitted to the schematic diagram of substrate in Figure 13 by isolated chip；
Figure 15 is the schematic diagram that ultra-thin wafers are carried out with thickness measure；
Figure 16 is to attach support membrane and do not attach the support transfer effect comparison diagram of support membrane；
Figure 17 is the picture surface top view after the wafer of comparative example 1 is cut by laser；
Figure 18 is the picture surface top view after the wafer of embodiment 4 is cut by laser；
Figure 19 is the chip patch and routing effect photo under high-power microscope；
Figure 20 is the three-point bending resistance intensity experiment schematic diagram of chip wafer.
Specific embodiment
It is of the invention to reach the technical means and efficacy that predetermined goal of the invention is taken further to illustrate, below in conjunction with
Preferred embodiment, the present invention is described in detail as follows.
It is as shown in Figure 1 wafer processing method schematic diagram of the invention.It includes the following steps: offer original wafer,
Including picture surface and the opposite back side, which has the chip design separated by Cutting Road；On the surface of the chip design
Attach protective film；Thinning operation is carried out to the back side of the original wafer, obtains ultra-thin wafers；It is attached at the back side of the ultra-thin wafers
Support membrane；Remove protective film；Dicing tape is attached on the surface of the support membrane；Along the Cutting Road of picture surface to the ultra-thin wafers
It is cut；And chip separation.Specifically, which includes the following steps:
Firstly, the original wafer 110 includes picture surface 112 and the back side 114 as shown in Fig. 2, providing original wafer 110, it is somebody's turn to do
Picture surface 112 and the back side 114 are located at the opposite two sides of the original wafer 110.It has designed and has added on the picture surface 112
Work has chip design 115, and each chip design 115 includes the chip of an individualism, leads between two neighboring chip
Reserved Cutting Road 116 is crossed to be separated from each other.The Cutting Road 116 is mainly used for pair of blade or laser beam when wafer is cut
It is quasi-.The chip design 115 is mainly by etching figure on the surface of original wafer 110 or depositing the material of different layers and shape
At being structure as a whole with original wafer 110.The back side 114 is for being ground, being thinned, being polished.In general, the original wafer
110 diameter is 12 inches or 8 inches.
Then, as shown in figure 3,115 surface of chip design in picture surface 112 pastes protective film 120.The protective film 120
Effect be protection chip design 115, avoid the porous ceramics disk of itself and subsequent stripping apparatus from generating suction-operated and generate and draw
Hurt, be stained.Specifically, under actual condition, in subsequent thinning process, which needs picture surface 112 downward
It is placed on the scratch diskette being made of porous ceramics, if the not protection of the protective film 120, the chip figure of the picture surface 112
It is easy to appear scratch, damage case 115.In addition, the waste water generated in thinning process also can be to the picture surface 112
Chip design 115 pollutes.The material of the protective film 120 be organic film, preferably UV (ultraviolet) or non-UV film, such as
The non-UV film of Nitto UB-3103ACUV film, Nitto BT-130P.
Then, the original wafer 110 is thinned by grinding the back side 114 of the original wafer 110, is obtained as shown in Figure 4
Ultra-thin wafers 111.Specifically, using milling apparatus to the original of 112 coated with protective film 120 of picture surface as shown in Figure 3
The back side 114 of wafer 110 roughly ground, fine grinding and polishing treatment, final to obtain with a thickness of 50 μm of ultra-thin wafers 111 below.
The milling apparatus is the full-automatic grinding polishing machine of the ability with 12 inches of processing and following wafer, model DISCO
DGP8761 ACCERETECH PG3000RMX.In one embodiment, the ultra-thin wafers 111 with a thickness of 15-50 μm,
Preferably 15-35 μm.
Then, as shown in figure 5, attaching support membrane 130 at the back side of ultra-thin wafers 111 114.By attaching the support membrane
130, which can be obedient to the shape of the support membrane 130 and keep smooth, no longer generation warpage, it is sagging the problems such as, benefit
Support is provided to the ultra-thin wafers 111 with the planarization of the support membrane 130 and tension.
The mode of the attaching is preferably the mode with the taut patch of cutting iron hoop 140, as shown in figure 5, the cutting iron hoop 140 be with
The cutting crystal wafer special-purpose member of the integrated full-automatic cutting laminator of above-mentioned milling apparatus, mainly play fixed supporting role.This is complete
Model DISCODFM2800 or the NITTO MA3000III of automatic cutting laminator.
It is illustrated in figure 6 the structural schematic diagram of the support membrane 130.The support membrane 130 sequentially includes organic film 132, glue
Adhesive layer 134 and release film layer 136.Wherein, the material of the organic film 132 is solid polyimides (PI), polyurethane
(PU), the organic films such as dimethyl silicone polymer (PDMS).Due to the resistant of high or low temperature, electric insulating quality, bonding of polyimides
Good characteristics, the material of the organic film 132 such as property, radiation resistance, resistance to medium are preferably polyimide film.Optionally, should
Kapton is NITTO AS-020PI12 or NITTOAS-020PIB12NM etc..In one embodiment, the organic film
Layer 132 with a thickness of 0.012mm, the overall thickness of the organic film 132 and the gluing oxidant layer 134 is 0.030mm, the release film layer
136 with a thickness of 0.050mm.It should be noted that in semicon industry, polyimides commonly liquid is coated in surface
Resolidification is a film afterwards.The disadvantages of the method are as follows process structure and step are more complicated, material consumption is more, and is coating
The improper chip design that can also pollute picture surface 112.Above-mentioned ask can solve using solid organic film 132 of the invention
Topic.
The process of the taut patch includes the steps that membrane, press mold, makes organic film 132 far from the back side of the ultra-thin wafers 111
114, the coiled support membrane 130 is straightened with full-automatic cutting laminator, by the gluing while tearing release film 136 off
Oxidant layer 134 is attached to the back side 114 of the ultra-thin wafers 111 and the surface of the cutting iron hoop 140.
After completing taut film, which leaves behind the gluing oxidant layer 134 and the organic film 132.The release film
Layer 136 is removed before the back side 114 for attaching to the ultra-thin wafers 111.When the release film layer 136 is primarily to facilitate pad pasting into
Row membrane, the support membrane 130 using rolling packaging structure, if without release film layer 136, the organic film 132 without glue
On one side together with the gluing oxidant layer 134 winding, and good bonding strength will lead to membrane difficulty, and the layer tension after having pasted compared with
Greatly.After increasing the release film layer 136, the film surface after being easy membrane and pad pasting is without obvious tension.As a result, due to the gluing
The effect of agent 134 may adhere to the ultra-thin wafers 111 and the cutting iron hoop so that the support membrane 130 has good adhesiveness
140 surface.In one embodiment, the adhesion strength of support membrane 130 is 6.7N/20mm.
Preferably, after completing taut film, confirm between the ultra-thin wafers 111 and the support membrane 130, the cutting iron hoop 140
Between the support membrane 130 the defects of bubble-free, corrugation and granule foreign, and to keep crystal circle center and cutting iron hoop 140
Center is consistent, wafer positioning is corresponded in the positioning with the cutting iron hoop 140.
Later, optionally, with reference to Fig. 7, extra support membrane 130 is cut off along the center of cutting iron hoop 140.It is specific next
It says, the support membrane 130 at edge is cut off with the hymenotome that cuts of the full-automatic cutting laminator institute band integrated with milling apparatus, it should
Model DISCO DFM2800 or the NITTO MA3000II of full-automatic cutting laminator.Preferably, it before cutting off, presses
Corresponding blade running track is set according to the size of cutting iron hoop 140 and cuts film angle, and the support pasted according to picture surface 112
Film speed is cut in the property adjustment of film 130.Preferably, because being to cut film along the center of cutting iron hoop 140, this cuts film angle, also
I.e. the positive angle theta of blade and the ultra-thin wafers 111 is 90 °.In one embodiment, which is polyimides
Film, the gluing oxidant layer 134 and the adhesiveness on the surface of the ultra-thin wafers 111 are stronger, therefore the speed for cutting film cannot be too fast, usually
Control is in 15-20 °/s.It is cut by controlling this and film angle and cuts film speed, it can be by the extra branch on the cutting iron hoop 140
Support film 130 is uniformly cut down along the center line of the cutting iron hoop 140, and without residual film and residue glue.
Then, with reference to Fig. 8, the ultra-thin wafers 111 shown in Fig. 7 for posting support membrane 130 and protective film 120 are carried out 180 °
Overturning, so that the picture surface 112 and the protective film 120 are upward.Specifically, in the full-automatic cutting integrated with milling apparatus
In laminator, the ultra-thin wafers 111 with cutting iron hoop 140 are carried out automatically by 180 ° of overturnings by mechanical arm, make its picture surface
112 upwards.
Then, with reference to Fig. 9, the protective film 120 is removed, obtain attaching Supported film 130 has supported what is fixed to surpass
Thin wafer 111.Specific operation are as follows: in the full-automatic cutting laminator integrated with milling apparatus, using with the protective film 120
The preferable adhesive tape gluing of adhesion strength is thrown off to the edge of the protective film 120, by it from the picture surface 112 of the ultra-thin wafers 111, by
This obtains the ultra-thin wafers 111 with support protection structure.This have support protection structure ultra-thin wafers 111 can carry out with
It is shifted between field procedure afterwards.Structure is protected in so-called support, refers to the support membrane 130 that 111 back side of ultra-thin wafers is pasted, specifically
For be the organic film 132 for being glued oxidant layer 134 and attaching to 111 back side of ultra-thin wafers.
Then, as shown in Figure 10, there are the ultra-thin wafers 111 of support protection structure to carry out 180 ° of overturnings this again, makes
It is downward to obtain picture surface 112.Then, dicing tape 150, specifically, the dicing tape are attached on the surface of the support membrane 130
150 are attached to the organic film 132 of the support membrane 130.As shown in figure 11, it after having attached dicing tape 150, re-starts
180 ° of overturnings, so that the picture surface 112 is upward.
Then, as shown in figure 12, cut along the Cutting Road 116 of picture surface 112, penetrate the ultra-thin wafers 111 with
And the support membrane 130, ultra-thin wafers 111 are divided into single chip 160, every chips 160 by ultra-thin wafers 111 figure
And tear the composition of support membrane 130 of release film off.Preferably, which is also only partially cut, but does not penetrate.
Then, as shown in figure 13, every chips 160 are separated from the dicing tape 150, the patch for next step
Piece.Specifically, as shown in figure 13, from the lower section external force of the dicing tape 150 by every chips 160 from the dicing tape
150 surfaces jack up, so that every chips 160 are separated from the dicing tape 150.The chip isolated includes corresponding
Ultra-thin wafers and support membrane part.
Finally, as shown in figure 14, the chip 160 separated is fitted to required position on substrate 170, and use gold thread
180 connect the chip 160 and the pad 190 on the substrate 170, realize the interconnection of chip 160 and substrate 170.
Embodiment 1:
(1) wafer is thinned by grinding the back side of original wafer: using having 12 inches of processing and following wafer
The full-automatic grinding polishing machine of the model DISCO DGP8761 of ability, to 12 inches of 112 coated with protective film 120 of picture surface
Original wafer 110 carry out grinding and polishing treatment, obtain the ultra-thin wafers 111 with a thickness of 15 μm.
(2) back side 114 for the ultra-thin wafers 111 completed in grinding is using the taut patch support membrane 130 of cutting iron hoop 140.The branch
Supportting film 130 includes organic film 132, gluing oxidant layer 134 and the release film layer 136 that material is polyimides, in taut patch process
Middle removing release film layer 136 stretches tight after the completion of patch, and the back side 114 of the ultra-thin wafers 111 is pasted with the gluing of the support membrane 130
Oxidant layer 134 and the organic film 132.The material of the organic film 132 is polyimides.
(3) extra support membrane 130 is cut off along the center of cutting iron hoop 140.In the present embodiment, the cutting iron hoop
140 size is 12 inches, using the full-automatic cutting laminator institute of the model DISCO DFM2800 integrated with milling apparatus
The hymenotome that cuts of band cuts off the support membrane 130 at edge, the front angle (cutting film angle) of blade and the ultra-thin wafers 111
θ is 90 °, and cutting film speed is 20 °/s.
(4) ultra-thin wafers 111 are overturn 180 °, keeps its picture surface 112 upward.In above-mentioned model DISCO
In the full-automatic cutting laminator of DFM2800, the ultra-thin wafers 111 with cutting iron hoop 140 are carried out automatically by mechanical arm
180 ° of overturnings, make it face up.
(5) protective film 120 on picture surface 112 is thrown off, the fixed ultra-thin wafers supported of supported membrane 130 are obtained
111.In the full-automatic cutting laminator of above-mentioned model DISCO DFM2800, using preferable with 120 adhesion strength of protective film
Adhesive tape gluing to the edge of the protective film 120, it is thrown off from the picture surface 112, thus to obtain have support protection structure
Ultra-thin wafers 111.
(6) in the taut patch dicing tape 150 in the surface of the support membrane 130 of the ultra-thin wafers 111.
(7) it is cut along the Cutting Road 116, the ultra-thin wafers 111 and the support membrane 130 is penetrated, by ultra-thin crystalline substance
Circle 111 is divided into single chip 160.Then, every chips 160 are separated from the dicing tape 150, in substrate 170
Position needed for upper carries out patch operation.
Embodiment 2:
(1) wafer is thinned by grinding the back side of original wafer: using having 12 inches of processing and following wafer
The full-automatic grinding polishing machine of the model ACCRETECH PG3000RMX of ability, to the 8 of 112 coated with protective film 120 of picture surface
The original wafer 110 of inch carries out grinding and polishing treatment, obtains the ultra-thin wafers 111 with a thickness of 20 μm.
(2) back side 114 for the ultra-thin wafers 111 completed in grinding is using the taut patch support membrane 130 of cutting iron hoop 140.The branch
Supportting film 130 includes organic film 132, gluing oxidant layer 134 and the release film layer 136 that material is polyimides, in taut patch process
Middle removing release film layer 136 stretches tight after the completion of patch, and the back side 114 of the ultra-thin wafers 111 is pasted with the gluing of the support membrane 130
Oxidant layer 134 and the organic film 132.The material of the organic film 132 is polyimides.
(3) extra support membrane 130 is cut off along the center of cutting iron hoop 140.In the present embodiment, the cutting iron hoop
140 size is 8 inches, using the full-automatic cutting laminator of the model NITTO MA3000III integrated with milling apparatus
The hymenotome that cuts of institute's band cuts off the support membrane 130 at edge, and the front angle of blade and the ultra-thin wafers 111 (cuts film angle
Degree) θ be 90 °, cut film speed be 20 °/s.It in the above conditions, can be by the support membrane 130 on the cutting iron hoop 140 along iron hoop
Center line is uniformly cut down, and without residual film and residue glue.Preferably, the size and the ruler for the wafer processed of iron hoop 140 are cut
It is very little consistent.
(4) ultra-thin wafers 111 are overturn 180 °, keeps its picture surface 112 upward.In above-mentioned model NITTO
In the full-automatic cutting laminator of MA3000III, by mechanical arm automatically will with cutting iron hoop 140 ultra-thin wafers 111 into
180 ° of row overturnings, make it face up.
(5) protective film 120 on picture surface 112 is thrown off, is obtained by the fixed ultra-thin crystalline substance supported of organic film 132
Circle 111.In the full-automatic cutting laminator of above-mentioned model NITTO MA3000III, using with 120 adhesion strength of protective film
Preferable adhesive tape gluing throws off it from the picture surface 112 to the edge of the protective film 120, thus to obtain having support protection
The ultra-thin wafers 111 of structure.
(6) in the taut patch dicing tape 150 in the surface of the support membrane 130 of the ultra-thin wafers 111.
(7) it is cut along the Cutting Road 116, the ultra-thin wafers 111 and the support membrane 130 is penetrated, by ultra-thin crystalline substance
Circle 111 is divided into single chip 160.Then, every chips 160 are separated from the dicing tape 150, in substrate 170
Position needed for upper carries out the operation of patch, routing.
Embodiment 3:
(1) wafer is thinned by grinding the back side of original wafer: using having 12 inches of processing and following wafer
The full-automatic grinding polishing machine of the model DISCO DGP8761 of ability, to 8 inches of 112 coated with protective film 120 of picture surface
Original wafer 110 carries out grinding and polishing treatment, obtains the ultra-thin wafers 111 with a thickness of 35 μm.
(2) back side 114 for the ultra-thin wafers 111 completed in grinding is using the taut patch support membrane 130 of cutting iron hoop 140.The branch
Supportting film 130 includes organic film 132, gluing oxidant layer 134 and the release film layer 136 that material is polyimides, in taut patch process
Middle removing release film layer 136 stretches tight after the completion of patch, and the back side 114 of the ultra-thin wafers 111 is pasted with the gluing of the support membrane 130
Oxidant layer 134 and the organic film 132.The material of the organic film 132 is polyimides.
(3) extra support membrane 130 is cut off along the center of cutting iron hoop 140.In the present embodiment, the cutting iron hoop
140 size is 8 inches, using the full-automatic cutting laminator institute of the model DISCO DFM2800 integrated with milling apparatus
The hymenotome that cuts of band cuts off the support membrane 130 at edge, the front angle (cutting film angle) of blade and the ultra-thin wafers 111
θ is 90 °, and cutting film speed is 20 °/s.It in the above conditions, can be by the support membrane 130 on the cutting iron hoop 140 along in iron hoop
Heart line is uniformly cut down, and without residual film and residue glue.
(4) ultra-thin wafers 111 are overturn 180 °, keeps its picture surface 112 upward.In above-mentioned model DISCO
In the full-automatic cutting laminator of DFM2800, the ultra-thin wafers 111 with cutting iron hoop 140 are carried out automatically by mechanical arm
180 ° of overturnings, make it face up.
(5) protective film 120 on picture surface 112 is thrown off, is obtained by the fixed ultra-thin crystalline substance supported of organic film 132
Circle 111.In the full-automatic cutting laminator of above-mentioned model DISCO DFM2800, using with 120 adhesion strength of protective film compared with
Good adhesive tape gluing throws off it from the picture surface 112 to the edge of the protective film 120, thus to obtain having support protection knot
The ultra-thin wafers 111 of structure.
(6) in the taut patch dicing tape 150 in the surface of the support membrane 130 of the ultra-thin wafers 111.
(7) it is cut along the Cutting Road 116, the ultra-thin wafers 111 and the support membrane 130 is penetrated, by ultra-thin crystalline substance
Circle 111 is divided into single chip 160.Then, every chips 160 are separated from the dicing tape 150, in substrate 170
Position needed for upper carries out patch operation.
Embodiment 4:
Difference from Example 1 is, the original wafer be thinned rear obtained ultra-thin wafers 111 with a thickness of 25
μm, the material of the organic film 132 of support membrane 130 used is polyimides.
Embodiment 5:
Difference from Example 1 is, the original wafer be thinned rear obtained ultra-thin wafers 111 with a thickness of 25
μm, the material of the organic film 132 of support membrane 130 used is polyurethane.
Embodiment 6:
Difference from Example 1 is, the original wafer be thinned rear obtained ultra-thin wafers 111 with a thickness of 25
μm, the material of the organic film 132 of support membrane 130 used is dimethyl silicone polymer.
Comparative example 1:
Comparative example 1 is the conventional processing method for not using support membrane 130 to be supported protection.Specifically, including such as
Lower step:
(1) wafer is thinned by grinding the back side of original wafer: using having 12 inches of processing and following wafer
The full-automatic grinding polishing machine of the model DISCO DGP8761 of ability, it is original to 12 inches of picture surface coated with protective film
Wafer carries out grinding and polishing treatment, obtains the ultra-thin wafers with a thickness of 25 μm.
(2) the directly taut patch dicing tape in the back side of the ultra-thin wafers after being thinned and the surface of the cutting iron hoop.
(4) it is cut along the Cutting Road, ultra-thin wafers is divided into single chip.Then, by every chips from
The dicing tape is separated, and required position carries out patch operation on substrate.
Below by way of experiment, compliance test result is carried out to above embodiments 1-6 and comparative example 1:
1. the thickness measure of ultra-thin wafers:
The thickness of ultra-thin wafers after being thinned is enterprising in the included non-contact optical measuring instrument of full-automatic thinned machine
The schematic diagram of row thickness measure, measurement is shown in Figure 15, using ultra-thin wafers to the penetrability of infrared light, passes through infrared light attenuation degree
Functional relation I=I between thickness0The thickness d after reality is thinned is calculated, wherein I representative sensor in exp (ud)
The intensity of the received ray after the measured object, I0The intensity that emission source issues ray is represented, u represents measured material to ray
Absorption coefficient.The thickness d of the ultra-thin wafers measured using the above method refers to the integral thickness of wafer, that is, the core in Figure 13
Wafer thickness in piece 160 other than support membrane 130, the ultra-thin wafers 111 being previously mentioned in each embodiment and comparative example
This thickness that thickness also refers to.In addition, because the figure of wafer designs in advance, figure with a thickness of fixed value,
For example, 8 μm.The measurement result of embodiment 1-6 and comparative example 1 is shown in Table 1.
Note that the back side attaches support membrane is after grinding wafer, primarily to enhancing the bending strength of chip, therefore
In the thickness measure stage for wafer thickness and fluctuation without influence.Difference of the TTV between maxima and minima in table.
Table 1 is shown, for 25 μm of target thickness thinning, thickness fluctuation is controlled in ± 1 μ m, TTV < 2 μm, as a result
It meets the requirements；For 15 μm of target thickness thinning, thickness fluctuation is controlled in ± 2 μ ms, as a result TTV < 2 μm meet and want
It asks；For 20 μm of target thickness thinning, thickness fluctuation is controlled in ± 2 μ ms, as a result TTV < 2 μm are met the requirements；For
35 μm of target thickness thinning, thickness fluctuation control in ± 2 μ ms, as a result TTV < 2 μm are met the requirements.Therefore, different real
It applies thickness thinning and fluctuation under example, TTV etc. to be not much different, meets control range.
The thickness of 1 ultra-thin wafers of table
| Embodiment 1 | Embodiment 2 | Embodiment 3 | Embodiment 4 | Embodiment 5 | Embodiment 6 | Comparative example 1 | |
| Organic film used | PI | PI | PI | PI | PU | PDMS | / |
| Target thickness/um | 15 | 20 | 35 | 25 | 25 | 25 | 25 |
| 1 | 16.88 | 21.68 | 34.60 | 25.12 | 24.69 | 24.96 | 26.41 |
| 2 | 16.03 | 22.12 | 34.50 | 23.57 | 23.34 | 24.27 | 25.83 |
| 3 | 17.29 | 21.59 | 33.92 | 25.18 | 24.52 | 25.41 | 25.64 |
| 4 | 15.92 | 22.30 | 33.80 | 24.46 | 23.64 | 24.11 | 26.67 |
| 5 | 17.50 | 22.50 | 35.43 | 23.71 | 23.01 | 23.45 | 25.23 |
| 6 | 17.41 | 22.40 | 33.68 | 25.00 | 24.94 | 25.28 | 24.80 |
| 7 | 16.65 | 20.80 | 33.50 | 24.99 | 24.31 | 24.29 | 24.96 |
| 8 | 16.20 | 20.64 | 35.42 | 24.62 | 24.46 | 24.52 | 26.49 |
| 9 | 17.30 | 21.58 | 33.91 | 23.55 | 23.28 | 23.91 | 25.81 |
| Average value (Ave) | 16.80 | 21.73 | 34.31 | 24.47 | 24.02 | 24.47 | 25.76 |
| Maximum value (Max) | 17.50 | 22.50 | 35.43 | 25.18 | 24.94 | 25.41 | 26.67 |
| Minimum value (Min) | 15.92 | 20.64 | 33.50 | 23.55 | 23.01 | 23.45 | 24.80 |
| TTV | 1.58 | 1.86 | 1.93 | 1.63 | 1.93 | 1.96 | 1.87 |
| Tolerance | 1.80 | 1.73 | -0.69 | -0.53 | -0.98 | -0.53 | 0.76 |
2. support transfer result:
After completing to be thinned, after taking the taut patch dicing tape of 25 μm of wafers respectively, wafer attach support membrane after, wafer patch
After attached support membrane and dicing tape, observation support transfer result.
As shown in figure 16 be support transfer effect comparison diagram, be respectively from up to down comparative example 1 grinding back surface after directly
Photo after patch dicing tape 150 directly pastes photo and embodiment after support membrane 130 after 4 grinding back surface of embodiment
4 overleaf grind after first paste comparison diagram between photo after the support membrane 130 pastes the dicing tape 150 again.It can from comparison
Know, compared with backside of wafer directly pastes the conventional method comparative example 1 of dicing tape: 1) the taut patch support membrane in the back side of embodiment 4 is (poly-
Acid imide film) after, wafer does not occur the defects of phenomena such as damaged, crackle, pad pasting interface bubble-free, impurity, not through manual manipulation
There are other bad problems, as a result meet demand；2) back side of embodiment 4 is first stretched tight, and patch support membrane (polyimide film) again cut by appropriateness
After adhesive tape, wafer does not occur phenomena such as damaged, crackle, and the defects of the interface bubble-free of two membranes, impurity, is taken manually
It puts and other bad problems does not occur, as a result meet demand.On the other hand, cutting glue is directly attached when support membrane is not present
There is bubble at the dotted line frame of picture surface as shown in comparative example 1 in band.
3. wafer cutting effect:
25 μm obtained in embodiment 4 and comparative example 1 of wafer is cut by laser, Figure 17 show comparative example
1 wafer be cut by laser along Cutting Road 116 after wafer picture surface top view.Although can be seen that as far as possible
Control cutting force degree, such as depth of cut shallower (50~75um), Cutting Road width relative narrower (< 20 μm), but partial region
Still there is the phenomenon that along Cutting Road edge chipping, such as the B area in figure.
Figure 18 show the wafer for attaching Supported film and dicing tape of embodiment 4 along the progress laser of Cutting Road 116
Wafer picture surface top view after cutting.Even if can be seen that in the biggish situation of cutting force degree, for example depth of cut is deeper
(125~175 μm), Cutting Road are wider (< 30 μm), and it is still neat to be formed by Cutting Road edge, and it is existing not occur apparent chipping
As.Its reason is mainly that the backside of wafer after being thinned attaches Supported film (polyimide film), can be by the stress of inside wafer
Redistribution, and support membrane can play certain buffer function during chip disconnects, and be not easy in wafer cutting
Stress occurs and concentrates generation chipping.
4. the patch and routing of chip 160 are verified:
The finished product after patch and routing is observed under Keyence VHX6000 Powerful Light Microscope, is obtained shown in Figure 19
Photo, as the result is shown: chip can be normally placed on the substrate 170 of flexible circuit board, the chip 160 in fetching process simultaneously
Phenomena such as not cracked, bottom overflow adhesive, the binding force meet demand after annealing.Meanwhile not going out in 180 bonding process of gold thread
Phenomena such as existing chip fracture phenomenon, gold thread 180 is without rosin joint, desoldering, meets the requirements through push-pull effort test bond strength.
5. the three-point bending resistance intensity experiment of chip:
It is as shown in figure 20 the three-point bending resistance intensity experiment schematic diagram of obtained chip wafer 160, as shown, will cut
The both ends that chip 160 after cutting is placed on test fixture 202,204 are fixed, by applying applied external force for the pressure of top
First 210 push movement, and come into contact with 160 surface of chip, and chip 160 receives external force and bends, and bend to certain
Occur to be crushed after degree, by the three-point bending resistance intensity of the available chip 160 of following formula, the results are shown in Table 2.
σ in formulamax,3-plFor 160 flexural strength of chip；G is the distance of test fixture 202,204 both ends；W is chip 160
Width；T is the thickness of chip 160.
2 three-point bending resistance strength test results of table
| Condition | Thickness | Data 1 | Data 2 | Data 3 | Average value | Maximum value | Minimum value | |
| Embodiment 1 | PI | 15 | 220 | 205 | 190 | 205 | 220 | 190 |
| Embodiment 2 | PI | 20 | 270 | 290 | 305 | 288 | 305 | 270 |
| Embodiment 3 | PI | 35 | 315 | 295 | 340 | 317 | 340 | 295 |
| Embodiment 4 | PI | 25 | 290 | 310 | 275 | 292 | 310 | 275 |
| Embodiment 5 | PU | 25 | 280 | 315 | 260 | 285 | 315 | 260 |
| Embodiment 6 | PDMS | 25 | 285 | 305 | 250 | 280 | 305 | 250 |
| Comparative example 1 | Nothing | 25 | 190 | 240 | 200 | 210 | 240 | 190 |
Table 2 illustrates first, and for the chip of same thickness, the intensity of the chip (embodiment 4-6) of Supported film support is bright
The aobvious chip (comparative example 1) higher than free-standing film support.Secondly, for the chip of different thickness, due to being produced in thinning process
Raw mechanical stress influences, and chip thickness is thinner, and intensity decreases, i.e., chip is easier to occur under external vertical
Damaged (Examples 1 to 4).
In conclusion in wafer thinning process, due to mechanical abrasive action, biggish damage can be generated in backside of wafer
Layer and residual stress distribution, cause the wafer that obvious buckling deformations occur after grinding.These stressor layers and damage
Hurt the presence of layer, stress concentration point easy to form.Ultra-thin wafers back using the prior art described in comparative example 1, after being thinned
Face directly attaches dicing tape, will lead to wafer or chip in subsequent transfer, cutting, patch and routing bonding process, holds
It is influenced vulnerable to applied external force and breakage occurs, cause higher fraction defective.
In the application, by with silicon face will there is the support membrane of strong adhesion strength to be attached to backside of wafer, with ultra-thin wafers
Adherency is integrated, so that protective film/wafer double-layer structure of script becomes protective film/wafer/support membrane sandwich structure,
Wafer is caught in the middle in this way, and support membrane can redistribute the internal stress of ultra-thin wafers after being thinned, in this way can be with
It is effectively improved the stress distribution of chip, internal stress is reduced, to reduce the risk of fragmentation.In addition, ultra-thin wafers are cut into core
After piece, support membrane is still integrated with chip, and to the supporting role of chip, there are still also further improve chip rear in this way
Fragment problems in the encapsulation process such as continuous patch, routing.
Simultaneously as the support membrane is cured film, room temperature fitting is not necessarily to hot setting, therefore, the operation of the application
Simple process, raw material expend less, can improve production efficiency, and to equipment without excessive demand with effectively save cost.
The above described is only a preferred embodiment of the present invention, be not intended to limit the present invention in any form, though
So the present invention has been disclosed as a preferred embodiment, and however, it is not intended to limit the invention, any technology people for being familiar with this profession
Member, without departing from the scope of the present invention, when the technology contents using the disclosure above make a little change or modification
It is right according to the technical essence of the invention for the equivalent embodiment of equivalent variations, but without departing from the technical solutions of the present invention
Any simple modification, equivalent change and modification made by above embodiments, all of which are still within the scope of the technical scheme of the invention.
Claims (10)
1. a kind of wafer processing method, characterized by the following steps:
Original wafer is provided, including picture surface and the opposite back side, which has the chip design separated by Cutting Road；
Protective film is attached on the surface of the chip design；
Thinning operation is carried out to the back side of the original wafer, obtains ultra-thin wafers；
Support membrane is attached at the back side of the ultra-thin wafers；
Remove protective film；
Dicing tape is attached on the surface of the support membrane；
The ultra-thin wafers are cut along the Cutting Road of picture surface；And
Chip separation.
2. wafer processing method according to claim 1, it is characterised in that: the thinning operation includes corase grinding, fine grinding and throwing
Light processing.
3. wafer processing method according to claim 1, it is characterised in that: the ultra-thin wafers with a thickness of 15-50 μm.
4. wafer processing method according to claim 1, it is characterised in that: the thinning operation, which uses, has 12 inches of processing
And the full-automatic grinding polishing machine of the ability of following wafer；Attaching operation is using full-automatic cutting laminator；And/or the support
The mode of the attaching of film is the mode with the taut patch of cutting iron hoop.
5. wafer processing method according to claim 4, it is characterised in that: further include being cut along the center of the cutting iron hoop
The step of except extra support membrane, before cutting off, is arranged corresponding blade running track according to the size of cutting iron hoop and cuts film
Angle, and film speed is cut according to the adjustment of the property of support membrane.
6. wafer processing method according to claim 5, it is characterised in that: it is 90 ° that this, which cuts film angle, and cutting film speed is
15-20°/s。
7. wafer processing method according to claim 1, it is characterised in that: the support membrane includes organic film, adhesive
Layer and release film layer, the release film layer are removed before the back side for attaching to the ultra-thin wafers.
8. wafer processing method according to claim 7, it is characterised in that: the material of the organic film is solid polyamides
Imines, polyurethane or dimethyl silicone polymer.
9. wafer processing method according to claim 1, it is characterised in that: when being cut to the ultra-thin wafers, penetrate
The ultra-thin wafers and the support membrane.
10. wafer processing method according to claim 1, it is characterised in that: the chip isolated includes corresponding ultra-thin
Wafer and support membrane part.
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| CN111146225A (en) * | 2019-12-24 | 2020-05-12 | 中芯集成电路（宁波）有限公司 | Forming method and chip separation method of combined image sensor chip |
| CN111799152A (en) * | 2020-07-20 | 2020-10-20 | 绍兴同芯成集成电路有限公司 | Wafer double-sided metal process |
| CN112758885A (en) * | 2020-12-25 | 2021-05-07 | 中国电子科技集团公司第十三研究所 | Cutting method of MEMS (micro-electromechanical systems) special-shaped chip |
| CN112975148A (en) * | 2021-02-07 | 2021-06-18 | 苏州镭明激光科技有限公司 | Wafer laser invisible cutting equipment and cutting method |
| CN114012917A (en) * | 2021-11-05 | 2022-02-08 | 苏州燎塬半导体有限公司 | Preparation method of gallium oxide single crystal wafer |
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| CN111146225A (en) * | 2019-12-24 | 2020-05-12 | 中芯集成电路（宁波）有限公司 | Forming method and chip separation method of combined image sensor chip |
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| CN112975148A (en) * | 2021-02-07 | 2021-06-18 | 苏州镭明激光科技有限公司 | Wafer laser invisible cutting equipment and cutting method |
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| CN114953214A (en) * | 2022-07-01 | 2022-08-30 | 苏州晶方光电科技有限公司 | Cutting method of wafer-level optical lens |
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