CN110263354A - The logical expression of cmos transmission gate logic circuit extracts and design at switch level method - Google Patents
The logical expression of cmos transmission gate logic circuit extracts and design at switch level method Download PDFInfo
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Abstract
The invention discloses a kind of extraction of the logical expression of cmos transmission gate logic circuit and design at switch level methods, Boolean algebra system are extended, the Boolean algebra system being expanded；Corresponding switching stage signal flow diagram model is established by cmos transmission gate logic circuit, thus model extraction goes out the equivalent signal flow graph model of the circuit output function, and the switch-level function expression of the circuit is obtained by the Boolean algebra system that switching stage signal flow diagram models coupling extends, to obtain cmos transmission gate logic circuit.The cmos transmission gate logic circuit that the present invention is designed by this method, required metal-oxide-semiconductor number is less, and required session number is less, can reduce power consumption and save chip area；And designed switching stage cmos transmission gate logic circuit is full swing, the design suitable for Low Power Digital Circuit.
Description
Technical field
The present invention relates to a kind of logical expressions of logic circuit to extract and design at switch level method, more particularly to one kind
The logical expression of cmos transmission gate logic circuit extracts and design at switch level method.
Background technique
Complementary metal ﹣ oxide semiconductor (Complementary metal-oxide semiconductor, CMOS) collection
The superior performances such as its is low in energy consumption at circuit because, and integrated level is high, strong antijamming capability, and supply voltage range is wide, ultra-large
In integrated circuit (VLSI) design, one kind being had become with the logic circuit that the combination of the various different modes of cmos transmission gate is constituted
Wide circuit form.Studies have shown that better simply circuit structure, this circuit often can be obtained using design at switch level method
Structure is to combine the cmos transmission gate logic circuit constituted with the various different modes of cmos transmission gate.
But how from cmos transmission gate logic circuit that is actual or having designed, corresponding logic function is extracted,
That is the extraction problem of logical expression verifies the analysis of logic circuit, Design and Features, all has significance.
Signal flow diagram is a kind of network model of the operating structure of indication circuit or system, in signal and system and information
It is widely used in science.CMOS logic circuit can be used corresponding signal flow diagram model to describe.Two-value Boolean algebra is Britain's number
The algebraic process that scholar George boolean (Geonge Boole) proposes in Research logic thinking and reasoning process in 19th century.It
Strong tool is provided to the logical design of digital circuit and system.But with design at switch level and low power dissipation design
Theoretical development, Boolean algebra theory seem obvious deficiency.For this purpose, having been presented for various switching stages (component-level) in the prior art
Design and analog simulation method.
Such as: CSA (Connector-switch-attenuator, the CSA) reason of cmos digital circuit switch grade analog simulation
By the theory thinks on the respectively sys node of the branch of metal-oxide-semiconductor containing source that there are multivalued logic signals, and thinks that each logical value is made
It is related with the driving capability of corresponding each branch current with intensity, thereby establish multivalue lattice structure.But it establishes in this lattice knot
Operation on structure is more complex.
Such as switch-signal theory that cmos digital circuit switch grade designs, the theory is the variable in cmos digital circuit
Signal variable and switching variable are divided into, signal algebraical sum switching algebra and the connective operation between them are thereby established；
The theory establishes two independent algebra systems, therefore operation and law are more.Utilize certain CMOS numbers of the Theoretical Design
Word circuit can not achieve full-swing design, cause power consumption larger.
Such as design at switch level method of the cmos digital circuit based on robust neural network, by introducing minterm inhibition
Thought carrys out simplified function, reduces the number of metal-oxide-semiconductor in circuit, but is only limitted to the design that CMOS determines source transmission circuit.
It is combined by the theory to cmos circuit disclosed in the prior art, Simulating Test Study obtains following result:
(1) in cmos circuitry, it is still to variable be divided into signal variable and switching variable, but need not establish respective only
Vertical algebra system can carry out operation and abbreviation under the Unified frame of Boolean algebra.
(2) in circuit design stage, it is believed that each driving capability phase of the branch current of metal-oxide-semiconductor containing source on sys node
Together, it is only necessary to consider the action intensity of four logical values on sys node, the operation relation of four logical values can be extended with one
Boolean algebra System describe.In breadboardin simulation stage, by optimizing the breadth length ratio of each NMOS tube and the width of each PMOS tube
Long ratio, is close to match, and can make the driving capability of each metal-oxide-semiconductor branch current close to identical in this way；But the breadth length ratio of metal-oxide-semiconductor is also
It is related with chip area, speed, power consumption, it needs to comprehensively consider.
(3) in cmos circuitry, circuit to be designed can be thought of as being made of signal and metal-oxide-semiconductor network.Load C MOS net
The influence of network can be equivalent to load capacitance.In circuit design stage it is considered that the load open circuit, it is only necessary to consider signal and
Interaction between metal-oxide-semiconductor network.
In CMOS IC design, area, speed, power consumption and Power dissipation delay are important technology indexs.Chip face
Product is made of device occupied area and wiring occupied area.Area shared by device is often indicated with area index, if each NMOS tube
Breadth length ratio it is equal, the breadth length ratio of each PMOS tube is equal, respectively n=(W/L)nWith p=(W/L)p, then area index is SE=
Nn·n+PnP, wherein NnAnd PnRespectively NMOS tube number and PMOS tube number.As it can be seen that also in used chip metal-oxide-semiconductor number
Mesh carrys out secondary indication device area.
The switching speed circuit of cmos circuit is often measured with the propagation delay time, and the propagation delay time is smaller, switch speed
It spends higher.The power consumption of cmos circuit is made of quiescent dissipation and dynamic power consumption.Before CMOS technology becomes prevailing technology, dynamic
Power consumption is the major part of circuit power consumption, and static leakage current power consumption can be ignored.The load capacitance of dynamic power consumption and circuit, input
Signal frequency and supply voltage it is square directly proportional.After CMOS technology becomes prevailing technology, with CMOS integrated circuit work
The continuous reduction of skill characteristic size, circuit power voltage constantly reduce, and circuit performance is continuously improved.Power dissipation delay
(Powerdelay product, PDP) is the important indicator for comparing integrated circuit technique performance, and value is smaller, and circuit performance is got over
It is good.
However, deriving above-mentioned conclusion even if the prior art is combined, but can still it bring following problems:
(1) chip area shared by the elements such as metal-oxide-semiconductor reduces in chip, and wiring occupied area increases, and saves area and answers
Consider to save face shared by device and wiring occupied area.
(2) circuit power voltage reduces, and reduces dynamic power consumption；But technology feature size reduces, and makes metal-oxide-semiconductor threshold voltage
Also accordingly reduce with gate oxide thickness, the conductive sub-threshold current leakage generated of metal-oxide-semiconductor subthreshold (weak transoid) and grid leakage current
The quiescent dissipation of caused metal-oxide-semiconductor increases, and reduces power consumption and is considered as reducing dynamic power consumption and reduces quiescent dissipation.
When CMOS technology technology enters the deep-submicron stage, circuit level is increased substantially, and portable device is a large amount of
Occur, seems even more important than saving area with low-power consumption at a high speed.It can be seen that saving area, reducing power consumption and improve and deposited between speed
In contradiction.
Summary of the invention
It is an object of the invention to overcome defect of the existing technology, a kind of patrolling for cmos transmission gate logic circuit is provided
Expression formula is collected to extract and design at switch level method.
In order to achieve the above objectives, the technical scheme adopted by the invention is that: a kind of logic of cmos transmission gate logic circuit
Expression formula is extracted and design at switch level method, Boolean algebra system is extended, the Boolean algebra system being expanded；By
Cmos transmission gate logic circuit establishes corresponding switching stage signal flow diagram model, and thus model extraction goes out the circuit output function
Equivalent signal flow graph model, and the switch of the circuit is obtained by the Boolean algebra system that switching stage signal flow diagram models coupling extends
Grade function expression, to obtain cmos transmission gate logic circuit.
Further, described to be extended Boolean algebra system, the Boolean algebra system being expanded refers to: logical value
Set V={ ф, 0,1, U }, variable are signal variable and switching variable, and signal variable and switching variable are two-valued variable, are taken
Value set is respectively subclass { 0,1 } and { ф, U }；
Signal variable logical value 1 and 0 respectively indicates the size of physical quantity related with signal properties；
Switching variable logical value U and ф indicate the size of physical quantity related with network element or node property；
It establishes Boolean algebra system respectively in set { 0,1 } and { ф, U }, establishes the Boolean algebra on set { 0,1 }
For signal algebra, the Boolean algebra established on set { ф, U } is switching algebra, the formula of their available Boolean algebras and
Theorem carries out operation and abbreviation.
Further, by the logic value set V and "AND", "or", " non-" three kinds of basic logic operations, one is constituted
Four value Boolean algebra systems, four value variable ξ, η ∈ V, three kinds of basic logic operations are respectively defined as
1: ξ η@min (ξ, η) of formula,
2: ξ+η@max (ξ, η) of formula,
Formula 3:
For subclass { 0,1 } and { ф, U }, there are ordering relation 1 > 0 and U > ф, signal algebraical sum switching algebra respectively
It is the subalgebra of four value Boolean algebras on subclass { 0,1 } and { ф, U } respectively；Increase a logical value threshold value 0.5 as 1
With 0 cut off value, ordering relation is 1 >, 0.5 > 0, and threshold comparison operation is divided into low threshold comparison operation and high threshold comparison operation, respectively
It is defined as
Formula 4:
Formula 5:
Signal realizes that transistor unit makees the control of signal to the control action of transistor unit by threshold comparison operation
Realize that the controlled signal value collection of generation is combined into { ф, 0,1 } with by AND operation, wherein signal variable value collection be combined into 0,
1}；It is defined on set { ф, U }n× { 0,1 }nOn operation be " line or " operation, reflect n controlled signal in its sys node
On interaction, on sys node, signal value collection is combined into { ф, 0,1, U }, wherein signal variable value collection be combined into 0,
1 }, logic value set V and five arithmetic expressions constitute the Boolean algebra system of an extension.
Further, the transistor unit refers to the control action of signal by AND operation realization: metal-oxide-semiconductor
Switch state is indicated " to control " operation with AND operation, be defined as to the control action of input signal
Formula 6:
G is switching variable or switch function in formula, indicates the control action of metal-oxide-semiconductor, g ∈ { ф, U }；Symbol " [] " indicates
Input signal source, y are input signal, y ∈ { 0,1 }；The output signal that the operation obtains after executing is controlled signal,
Value collection is combined into { ф, 0,1 }, and wherein ф is high-impedance state.
Further, the corresponding relationship of the end value He the signal variable value of the threshold comparison operation, corresponding relationship
With symbolIt indicates, is expressed as theorem formula 1:The corresponding relationship is considered as a kind of transformation, direct transform by
Switching variable transforms to signal variable, is expressed as with symbol " → " 0.5x→x；Inverse transformation is by signal variable inverse transformation
To switching variable, it is expressed as with symbol " ← "0.5X ← x,
What two series connection metal-oxide-semiconductor branches connected determines source transmission circuit x0.5y0.5[1] and0.5x0.5Y [0], is converted respectively
For the necessary condition for becoming source transmission circuit accordingly, symbol is usedIt indicates, is used in combinationIt indicates It indicates
It is then theorem formula 2
Source transmission circuit is determined by what two metal-oxide-semiconductor branches of connecting connected, and the contravariant of one of metal-oxide-semiconductor control variable is made
To become source, to replace determining the metal-oxide-semiconductor in the transmission of source, change source transmission circuit is obtained；
The PMOS tube branch and NMOS tube branch of the y of transmission respectively (1) and y (0) of two output end parallel connections, if its control becomes
Amount is mutually non-, then two input terminals can be connected in parallel y, obtain a cmos transmission gate branch, which can transmit without loss
Signal variable y, i.e. theorem formula 3
When it is significant level that it, which controls variable, if input signal is 1, PMOS tube and NMOS tube transmit 1 He of signal respectively
1t is acted on its sys node, generates signal 1；Actual physical process [2,5] is, as sys node level Vout≥(VDD-
VTN) after, NMOS tube transmission 1t signal terminates, and PMOS tube transmits 1 signal of signal ability when sys node level is supply voltage
Terminate；If input signal is 0, NMOS tube and PMOS tube transmit signal 0 and ot respectively, act on its sys node, generate letter
Number 0；Actual physical process is, as sys node level Vout≤(-VPT) after, PMOS tube transmission ot signal terminates, and NMOS tube passes
Defeated 0 signal just terminates when sys node level is ground level (0V)；When it is inactive level that it, which controls variable, two MOS
Pipe is turned off, and output end is high-impedance state ф, violates constraint condition at this time, ф belongs to illegal state；
If the PMOS sub-network of f and the switch function of NMOS sub-network are respectivelyWithThen with equivalence of drawing a conclusion:
(1) the negative logic expression formula of the function is anti-, i.e. the negative logic expression formula of the function inverse function and the anti-letter of the function
Several positive logic expression formulas dual formula each other；
(2) switch function of the PMOS sub-network of the function and the switch function of NMOS sub-network dual function each other；
(3) the PMOS sub-network and NMOS sub-network of the function dual network each other；
(4) switch-level function expression (transfer function) of the function is
Theorem formula 4
For the change source transmission series connection PMOS tube branch (x of function f0.5y0.5) [z], it enablesIndicate product itemThe set of the level signal composition of contained function f=1,For product itemThe voltage of contained Z=0 is believed
Number set, ifThen the branch can transmit without lossIt will not produce
Raw U1 level signal；
For function f change source transmission series connection NMOS branch (0.5x0.5Y) [z] is enabledIndicate product itemThe set of the level signal composition of contained function f=0, the voltage letter that { xy (z (1)) } is Z=1 contained by product item (xy)
Number set, if { xy (z (1)) } I { xyz (f (0)) }=empty set, the branch can transmit without lossIt will not
Generate U2 level signal.
Further, in order to indicate the voltage signal transmitted on two branches of metal-oxide-semiconductor containing source on its sys node
Interaction, " line or " operation for defining two input signals or controlled signal on sys node is formula 7:
g1[y1]+g2[y2]@max(g1[y1],g2[y2]),
Constraint condition: work as y1≠y2When,Otherwise, y1=y2When, g1+g2=U,
When constraint condition is unsatisfactory for, the state of two input signals on sys node will be clashed, and form low-resistance
State U is high-impedance state ф, and in both cases, the value of output signal variable not can determine that setting is forbidden.
Further, described corresponding switching stage signal flow diagram model is established by cmos transmission gate logic circuit to refer to:
The element legs of cmos transmission gate logic circuit have PMOS tube branch, NMOS tube branch, cmos transmission gate branch and line branch
Four classes, wherein PMOS tube and NMOS tube are single-groove road transmission gate, transmit 0 signal of 1 signal and transmission without loss respectively, and CMOS is passed
Defeated door branch is double channel transmission gate, transmits signal variable without loss, this three classes branch is controlled branch, and line branch is
Uncontrolled branch, is direct transmission branch, and the switch-level function expression of four class component branches is respectively
f1=x0.5·[1],f2=0.5x·[0],f4=U [y]=[y],
By given cmos transmission gate logic circuit, the signal stream of element legs in cmos transmission gate logic circuit is utilized
Graph model obtains the switching stage signal flow diagram model of the circuit, and in switching stage signal flow diagram model, the arrow of branch road is indicated
The transmission direction of signal, switching variable or switch constant beside arrow are the control of the branch, left and right two ends of the branch
Point is known as the node of signal flow diagram, and the corresponding node signal of each node, wherein the node on the left side is known as source node or input
Node, connecting signal source, the node on the right are known as function node or output node, and connection loads, the output signal on the node
For controlled signal.
The method have the benefit that: the cmos transmission gate logic circuit designed by this method, required metal-oxide-semiconductor number
Mesh is less, and required session number is less, can reduce power consumption and save chip area；And designed switching stage CMOS transmission
Gate logic is full swing, the design suitable for Low Power Digital Circuit.
Detailed description of the invention
The present invention is further elaborated with embodiment with reference to the accompanying drawing.
Fig. 1 is element legs figure in cmos transmission gate circuit of the present invention；
Fig. 2 is cmos transmission gate circuit signal flow graph model of the present invention；
Fig. 3 is cmos transmission gate circuit EX1 circuit diagram of the present invention；
Fig. 4 is the cmos transmission gate circuit signal flow graph model of Fig. 3 of the present invention
Fig. 5 is the signal flow diagram that Fig. 3 of the present invention transmits 1 signal
Fig. 6 is the equivalent signal flow graph model of Fig. 3 output function of the present invention；
Fig. 7 is cmos transmission gate logic circuit EX2 circuit diagram of the present invention；
Fig. 8 is Fig. 7 signal flow diagram model of the present invention；
Fig. 9 is the equivalent signal flow graph model of Fig. 7 output function of the present invention；
Figure 10 is the equivalent signal flow graph of transmission gate circuit of the present invention；
Figure 11 is Figure 10 signal flow diagram model of the present invention；
Figure 12 is that Figure 10 of the present invention determines source transmission circuit EX3A；
Figure 13 is that Figure 10 of the present invention becomes source transmission circuit EX3B；
Figure 14 is CMOS full adder circuit EX4A of the present invention with driving output；
Figure 15 is CMOS full adder circuit EX4B of the present invention without driving output.
Specific embodiment
Embodiment 1
A kind of the logical expression extraction and design at switch level method of cmos transmission gate logic circuit, by Boolean algebra system
It is extended, the Boolean algebra system being expanded；Corresponding switching stage signal flow diagram is established by cmos transmission gate logic circuit
Model, thus model extraction goes out the equivalent signal flow graph model of the circuit output function, and by switching stage signal flow diagram model knot
The Boolean algebra system for closing extension obtains the switch-level function expression of the circuit, to obtain cmos transmission gate logic circuit.
The number of contained metal-oxide-semiconductor still be can yet be regarded as the important indicator for measuring circuit power consumption and area in circuit.Research hair
It is existing, it using full swing cmos transmission gate circuit structure, can be lost to avoid threshold voltage, reduce subthreshold value power consumption, reduce metal-oxide-semiconductor
Number.Present invention discloses how optimization full swing cmos transmission gate Logic Circuit Designs, and optimization aim is to make institute in circuit
It is reached with the number of metal-oxide-semiconductor minimum or smaller.Emulation experiment shows that the cmos circuit that the present invention designs has preferable level matter
Amount, lower power consumption lagged product, the design suitable for Low-Power CMOS transmission gate logic.
Described to be extended Boolean algebra system, the Boolean algebra system being expanded refers to: logic value set V=
{ ф, 0,1, U }, variable are signal variable and switching variable, and signal variable and switching variable are two-valued variable, value set point
It Wei not subclass { 0,1 } and { ф, U }；
Signal variable logical value 1 and 0 respectively indicates the size of physical quantity related with signal properties；
Switching variable logical value U and ф indicate the size of physical quantity related with network element or node property；
It establishes Boolean algebra system respectively in set { 0,1 } and { ф, U }, establishes the Boolean algebra on set { 0,1 }
For signal algebra, the Boolean algebra established on set { ф, U } is switching algebra, the formula of their available Boolean algebras and
Theorem carries out operation and abbreviation.
By the logic value set V and "AND", "or", " non-" three kinds of basic logic operations, a four value boolean are constituted
Algebra system, four value variable ξ, η ∈ V, three kinds of basic logic operations are respectively defined as
1: ξ η@min (ξ, η) of formula,
2: ξ+η@max (ξ, η) of formula,
Formula 3:
For subclass { 0,1 } and { ф, U }, there are ordering relation 1 > 0 and U > ф, signal algebraical sum switching algebra respectively
It is the subalgebra of four value Boolean algebras on subclass { 0,1 } and { ф, U } respectively；Increase a logical value threshold value 0.5 as 1
With 0 cut off value, ordering relation is 1 >, 0.5 > 0, and threshold comparison operation is divided into low threshold comparison operation and high threshold comparison operation, respectively
It is defined as
Formula 4:
Formula 5:
Signal realizes that transistor unit makees the control of signal to the control action of transistor unit by threshold comparison operation
Realize that the controlled signal value collection of generation is combined into { ф, 0,1 } with by AND operation, wherein signal variable value collection be combined into 0,
1}；It is defined on set { ф, U }n× { 0,1 }nOn operation be " line or " operation, reflect n controlled signal in its sys node
On interaction, on sys node, signal value collection is combined into { ф, 0,1, U }, wherein signal variable value collection be combined into 0,
1 }, logic value set V and five arithmetic expressions constitute the Boolean algebra system of an extension.
The transistor unit refers to the control action of signal by AND operation realization: the switch state pair of metal-oxide-semiconductor
The control action of input signal is indicated " to control " operation with AND operation, is defined as
Formula 6:
G is switching variable or switch function in formula, indicates the control action of metal-oxide-semiconductor, g ∈ { ф, U }；Symbol " [] " indicates
Input signal source, y are input signal, y ∈ { 0,1 }；The output signal that the operation obtains after executing is controlled signal,
Value collection is combined into { ф, 0,1 }, and wherein ф is high-impedance state.
Theorem 1: the end value of the threshold comparison operation and the corresponding relationship of the signal variable value, corresponding relationship is with symbolIt indicates, is expressed as theorem formula 1:The corresponding relationship is considered as a kind of transformation, and direct transform is become by switch
Signal variable is changed in quantitative change, is expressed as with symbol " → " 0.5x→x；Inverse transformation changes to switch by signal variable contravariant
Variable is expressed as with symbol " ← "0.5X ← x,
What theorem 2: two series connection metal-oxide-semiconductor branches connected determines source transmission circuit x0.5y0.5[1] and0.5x0.5Y [0], point
The corresponding necessary condition for becoming source transmission circuit is not converted to, uses symbolIt indicates, is used in combinationIt indicates It indicatesIt is then theorem formula 2
Source transmission circuit is determined by what two metal-oxide-semiconductor branches of connecting connected, and the contravariant of one of metal-oxide-semiconductor control variable is made
To become source, to replace determining the metal-oxide-semiconductor in the transmission of source, change source transmission circuit is obtained；
The PMOS tube branch and NMOS tube branch of the y of transmission respectively (1) and y (0) of 3: two output end parallel connections of theorem, if its
It is mutually non-to control variable, then two input terminals can be connected in parallel y, obtain a cmos transmission gate branch, which can be with free of losses
Transmit signal variable y, i.e. theorem formula 3 in ground
When it is significant level that it, which controls variable, if input signal is 1, PMOS tube and NMOS tube transmit 1 He of signal respectively
1t is acted on its sys node, generates signal 1；Actual physical process [2,5] is, as sys node level Vout≥(VDD-
VTN) after, NMOS tube transmission 1t signal terminates, and PMOS tube transmits 1 signal of signal ability when sys node level is supply voltage
Terminate；If input signal is 0, NMOS tube and PMOS tube transmit signal 0 and ot respectively, act on its sys node, generate letter
Number 0；Actual physical process is, as sys node level Vout≤(-VPT) after, PMOS tube transmission ot signal terminates, and NMOS tube passes
Defeated 0 signal just terminates when sys node level is ground level (0V)；When it is inactive level that it, which controls variable, two MOS
Pipe is turned off, and output end is high-impedance state ф, violates constraint condition at this time, ф belongs to illegal state；
Theorem 4: the switch function of the PMOS sub-network and NMOS sub-network that set f is respectivelyWithThen to draw a conclusion
It is of equal value:
(1) the negative logic expression formula of the function is anti-, i.e. the negative logic expression formula of the function inverse function and the anti-letter of the function
Several positive logic expression formulas dual formula each other；
(2) switch function of the PMOS sub-network of the function and the switch function of NMOS sub-network dual function each other；
(3) the PMOS sub-network and NMOS sub-network of the function dual network each other；
(4) switch-level function expression (transfer function) of the function is
Theorem formula 4
Theorem 5: for the change source transmission series connection PMOS tube branch (x of function f0.5y0.5) [z], it enablesIt indicates
Product itemThe set of the level signal composition of contained function f=1,For product itemThe electricity of contained Z=0
Signal set is pressed, ifThen the branch can transmit without lossNo
U1 level signal can be generated；
Theorem 6: for function f change source transmission series connection NMOS branch (0.5x0.5Y) [z] is enabledIndicate product
?The set of the level signal composition of contained function f=0, { xy (z (1)) } are the voltage of Z=1 contained by product item (xy)
Signal set, if { xy (z (1)) } I { xyz (f (0)) }=empty set, the branch can transmit without lossNo
U2 level signal can be generated.
It is fixed in order to indicate interaction of the voltage signal transmitted on two branches of metal-oxide-semiconductor containing source on its sys node
" line or " operation of two input signals or controlled signal is formula 7 on adopted sys node:
g1[y1]+g2[y2]@max(g1[y1],g2[y2]),
Constraint condition: work as y1≠y2When,Otherwise, y1=y2When, g1+g2=U,
When constraint condition is unsatisfactory for, the state of two input signals on sys node will be clashed, and form low-resistance
State U is high-impedance state ф, and in both cases, the value of output signal variable not can determine that setting is forbidden.
Described to establish corresponding switching stage signal flow diagram model by cmos transmission gate logic circuit and refer to: cmos transmission gate is patrolled
The element legs for collecting circuit have PMOS tube branch, four class of NMOS tube branch, cmos transmission gate branch and line branch, wherein PMOS
Pipe and NMOS tube are single-groove road transmission gate, transmit 0 signal of 1 signal and transmission without loss respectively, cmos transmission gate branch is double
Channel pass door, transmits signal variable without loss, this three classes branch is controlled branch, and line branch is uncontrolled branch,
Switch-level function expression for direct transmission branch, four class component branches is respectively
f1=x0.5·[1],f2=0.5x·[0],f4=U [y]=[y],
By given cmos transmission gate logic circuit, the signal stream of element legs in cmos transmission gate logic circuit is utilized
Graph model obtains the switching stage signal flow diagram model of the circuit, and in switching stage signal flow diagram model, the arrow of branch road is indicated
The transmission direction of signal, switching variable or switch constant beside arrow are the control of the branch, left and right two ends of the branch
Point is known as the node of signal flow diagram, and the corresponding node signal of each node, wherein the node on the left side is known as source node or input
Node, connecting signal source, the node on the right are known as function node or output node, and connection loads, the output signal on the node
For controlled signal.
Embodiment 2
As shown in Figure 1, the element legs of cmos transmission gate circuit have four classes, i.e. PMOS tube branch, NMOS tube branch, CMOS
Transmission gate branch and line branch, wherein PMOS tube and NMOS tube are single-groove road transmission gate, can transmit 1 letter without loss respectively
Number and transmission 0 signal, cmos transmission gate branch be double channel transmission gate, signal variable can be transmitted without loss.The above three classes
Branch is controlled branch, and line branch is uncontrolled branch, i.e., directly transmits (straight-through) branch.The switch of four class component branches
Grade function expression be respectively
f1=x0.5·[1],f2=0.5x·[0],f4=U [y]=[y]
Its corresponding switching stage signal flow diagram model, as shown in Figure 2.Wherein the arrow of branch road indicates the transmission of signal
(flowing) direction, the switching variable (or switch constant) beside arrow are the control of the branch, and wherein U can be omitted.The branch
Left and right two endpoints (dot in figure), the referred to as node of signal flow diagram, the corresponding node signal of each node, wherein
The node on the left side is known as source node or input node, connecting signal source, and the node on the right is known as function node or output node, even
Load is connect, the signal (output signal) on the node is controlled signal.
By given cmos transmission gate circuit, using the signal flow diagram model of element legs in cmos transmission gate circuit,
The switching stage signal flow diagram model that can obtain the circuit, by the logical expression of the available circuit output function of the model.
Fig. 3 is the cmos transmission gate circuit designed using robust neural network method, the entitled EX1 of the circuit of the circuit, benefit
The logical expression of the circuit output function is sought with signal flow diagram modelling.By given cmos transmission gate circuit, establishing should
The switching stage signal flow diagram model of circuit, as shown in Figure 4.
By Fig. 4, using theorem formula 4, the switch-level function expression for obtaining the circuit is
Using theorem formula 1, by theorem formula 4 and above formula, the logical expression that can obtain the circuit output function is
Similarly, the logical expression that can obtain the circuit output function complementary function is
For seeking the logical expression of cmos circuit output function, switching stage signal flow diagram model can further be changed
Letter and transformation, obtain the equivalent signal flow graph model for seeking the circuit output function.For the circuit shown in Fig. 3, biography is drawn by Fig. 4
The signal flow diagram of defeated 1 signal converts the signal flow diagram of Fig. 5 to obtain the circuit output function as shown in figure 5, using theorem formula 1
Equivalent signal flow graph model, as shown in Figure 6.In the figure, the signal variable (power of the branch) beside each branch upward arrow
Operation between source node signal variable is AND operation；The operation between input signal on each point in parallel is "or" fortune
It calculates.By Fig. 6, abbreviation is carried out using above-mentioned operation, can must describe the logical expression of circuit output function shown in Fig. 3.Similarly, by
The signal flow diagram model of 0 signal is transmitted, and utilizes theorem formula 1, the equivalent signal flow graph mould of the convertible complementary function for obtaining it
Type.Thus model can find out the logical expression of complementary function.
Embodiment 3
As shown in fig. 7, full adder circuit (the electricity of the cmos transmission gate type obtained using switch-signal theory design method
The entitled EX2 in road).The logical function expression formula of the circuit is sought with equivalent signal flow graph modelling.
Step1 modeling.Full adder circuit as shown in Figure 7 draws the signal stream of the complementary function of the output function of the circuit
Graph model is as shown in Figure 8.In figure, C (0) indicates C=0,It indicatesEtc..By Fig. 8, utilizeWithTransmission
The signal flow diagram of 0 signal, is converted, and circuit output function s is obtainedi, ciWith equivalent signal flow graph model such as Fig. 9 institute of h
Show.
Step2 analysis.The output s of full adder can be directly acquired by Fig. 9iAnd ciFor
Utilize the logical expression after Boolean algebra (signal algebra) method progress abbreviation to get full adder.
Embodiment 4
Known definition is in variables collection { x1,x2,x3,x4On the minterm expressions of four variable logical functions be
F=∑ (2,3,4,5,7,10,11,14,15)
The cmos transmission gate logic circuit for realizing the function is designed using signal flow diagram method.This function is embodiment
The function that 2 circuits are realized.
The signal flow diagram method general step of design at switch level is as follows:
The minimum method of Step1 logical function by given function f andAbbreviation is the sum of simplified product (Reduced
Sum-of-products, RSOP) form.And check whether each long-pending item in the RSOP form of f has common factor.If so, then carrying out
Propose common factor processing.For this example, in the RSOP form of function f, product item x1x3,And x3x4There is common factor x3, mentioned
After common factor processing, then calculating formula 1 is obtained
Step2 draw respectively f andEquivalent signal flow diagram；The two is respectively converted into 0 letter of 1 signal of transmission and transmission
Number signal flow diagram, and the two is merged into the signal flow diagram of f.For this example, by calculating formula 1 function f andIt is equivalent
Signal flow diagram is as shown in Figure 10；The two is respectively converted into 1 signal of transmission and transmits the letter of 0 signal using theorem 1 by Figure 10
Number flow graph, and the two is merged into the signal flow diagram of the switching stage function of f, as shown in figure 11.
Step3 utilizes switching stage signal flow diagram model, writes out and determines source transmission circuit switching stage expression formula.By Figure 11, write out
Determine the switching stage expression formula of source transmission circuit, and is calculating formula 2 after abbreviation
Using theorem formula 2,3 and theorem 5,6, the switching stage expression formula of change source transmission circuit is acquired by calculating formula 2 to calculate
Formula 3
Step4 draws cmos transmission gate logic circuit to be designed.It is drawn by calculating formula 2 and designed determines source transmission circuit
(the entitled EX3A of circuit) as shown in figure 12, needs 20 metal-oxide-semiconductors altogether.Designed change source transmission circuit (circuit is drawn by calculating formula 3
Entitled EX3B) as shown in figure 13,18 metal-oxide-semiconductors are needed altogether.Analog simulation through HSPICE software, it was demonstrated that they, which have, correctly patrols
Collect function.
Embodiment 5
Utilize the CMOS full adder circuit of the Boolean algebra method design transmission gate of extension.
(1) the cmos transmission gate type full adder design with driving output
In order to improve the performance of full adder, the full adder circuit structure with driving output can be used, due to driving output tool
There is inverter functionality, therefore be considered as the design at switch level of inverse function, design procedure is as follows:
Step1 finds out S using Boolean algebra (signal algebra) methodi-, Si+, Ci-, Ci+And the h of exclusive or function-, h+'s
RSOP form is respectively calculating formula 4
Step2 utilizes calculating formula 3 and calculating formula 4, finds out and determines source transmission circuit switch-level function expression for calculating formula 5
Step3 utilizes theorem formula 2,3 and theorem 5,6, and the switching stage function representation of change source transmission circuit is acquired by calculating formula 5
Formula is calculating formula 6
It is as shown in figure 14 to draw change source transmission full adder circuit (the entitled EX4A of circuit) by calculating formula 6 by Step4.Through
The analog simulation of HSPICE software, it was demonstrated that the full adder circuit has correct logic function.
(2) without the cmos transmission gate type full adder design of driving output, it is considered as opening for full adder output function at this time
Grade design is closed, design procedure is as follows:
Step1 is found out using Boolean algebra (signal algebra) methodh-, h+'s
RSOP form is respectively calculating formula 7
Step2 utilizes calculating formula 2 and calculating formula 7, finds out and determines source transmission circuit switch-level function expression for calculating formula 8
Step3 acquires the switching stage expression formula of change source transmission circuit by calculating formula 8 using theorem 2,3 as calculating formula 9
It is as shown in figure 15 to draw change source transmission full adder circuit (the entitled EX4B of circuit) by calculating formula 9 by Step4.Through
The analog simulation of HSPICE software, it was demonstrated that the full adder circuit has correct logic function.
Gained circuit in above-described embodiment is compared, comparison sheet is as follows:
Wherein, the load capacitance of the output end connection of each circuit is 10fF.Power consumption (Power) in table is average function
Consumption, takes the average value in 100 periods；Delay time (Delay) is that input voltage becomes when being changed to (Vdd/2) to output voltage
Time interval when changing to (Vdd/2), takes its maximum value.
By table as it can be seen that the performance for the circuit that the Boolean algebra method of extension proposed by the present invention designs, hence it is evident that better than opening
The performance of the homogeneous circuit of pass-signal theory method and the design of robust neural network method.This also illustrates for switching stage circuit
The design of structure, there are the circuit structures of a variety of relatively optimizations.As using the optimization gate level circuit design of Boolean algebra method,
Optimize switching stage circuit design using EBAM, there is also the circuit structures of the relatively optimization of plurality of optional.It is switched using EBAM
Grade design actually and optimizes Boolean expression, is allowed to be suitable for full swing cmos transmission gate circuit structure design.It can reach
To defined design objective, is tested and determined by emulation experiment.If not being able to satisfy design objective, then carries out the optimization of circuit structure and set
Meter, or the breadth length ratio of each metal-oxide-semiconductor of optimization, then carry out emulation experiment test.In fact, this is that a design is answered with simulation interactive
Cyclic process, this process until reaching defined design objective, or think the index of the cmos circuit of design reach compared with
Until excellent.
Compared with prior art, the present invention realizing two kinds of innovations.
One, theory innovation
(1) two-value Boolean algebra has had over one hundred year history, has become digital circuit and patrol with system since 19th century proposed
Collect design (gate level design) strong tool.But with the development of design at switch level theory, Boolean algebra theory seems bright
It is inadequate.It is considered that can still be carried out under the frame of Boolean algebra, Boolean algebra theory needs to send out for design at switch level
Exhibition.The Boolean algebra for proposing extension is theoretical (switching stage is theoretical), establishes the boolean of the extension of cmos transmission gate logic circuit
Five kinds of arithmetic expressions (formula 1- formula 5) of algebra system and six theorems (theorem 1- theorem 6).Propose cmos transmission gate logic circuit
A kind of switching stage mathematical model --- switching stage expression formula, it is one-to-one with cmos transmission gate logic circuit.
(2) Boolean algebra theoretical (switching stage is theoretical) of extension and the connection of Boolean algebra theoretical (logic level is theoretical) are established
System, the mutual conversion established between the switching stage expression formula of cmos transmission gate logic circuit and Boolean algebra logical expression are closed
System.
(3) the signal flow diagram model for proposing cmos transmission gate logic circuit indicates；And signal flow diagram model indicate and
Mutual transformational relation between switching stage expression formula；The logic function that the model is applied to cmos transmission gate logic circuit is extracted
And switch level analysis.
(4) the signal flow diagram method of cmos transmission gate switching logic circuit grade design is derived using above-mentioned theory and method
And algebraic method.
Two, practical value
By the above-mentioned theory and method provided, set by embodiment and the simulation experiment result, and with other switching stages
The comparison of meter method.Show that method proposed by the present invention is effective；Utilize the cmos transmission gate logic electricity of context of methods design
Road, required metal-oxide-semiconductor number is less, and required session number is less, can reduce power consumption and save chip area.Moreover, set
The switching stage cmos transmission gate logic circuit of meter is full swing, the design suitable for Low Power Digital Circuit.
Current CMOS IC design has entered deep-submicron field.After CMOS technology develops to the deep-submicron stage,
The requirement of all technical such as area, speed and power consumption to cmos circuit design etc. has played the variation of essence, and high speed is low
It is even more important that power dissipation ratio saves area.But in CMOS IC design, it is desirable that the number of contained metal-oxide-semiconductor is minimum in circuit,
The optimization aim for circuit design of still can yet be regarded as.Because the number of contained metal-oxide-semiconductor can not only reflect in chip indirectly in chip
Device occupied area, and the power consumption of shared area and chip is routed in chip, also the number with metal-oxide-semiconductor in chip has
It closes.The design at switch level of full swing cmos transmission gate logic circuit disclosed by the invention, optimization aim are to make institute in the circuit
With the number of metal-oxide-semiconductor up to minimum or smaller, it is based on what the requirement of deep-submicron CMOS process proposed.Emulation experiment shows
Cmos circuit designed by the present invention has preferable level quality, lower power consumption lagged product.
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, those skilled in the art can make various deformations or amendments within the scope of the claims, this not shadow
Ring substantive content of the invention.
Claims (7)
1. a kind of logical expression of cmos transmission gate logic circuit extracts and design at switch level method, it is characterised in that: by cloth
You are extended algebra system, the Boolean algebra system being expanded；Corresponding switch is established by cmos transmission gate logic circuit
Grade signal flow diagram model, thus model extraction goes out the equivalent signal flow graph model of the circuit output function, and by switching stage signal
The Boolean algebra system of flow graph models coupling extension obtains the switch-level function expression of the circuit, to obtain cmos transmission gate
Logic circuit.
2. the logical expression of cmos transmission gate logic circuit according to claim 1 extracts and design at switch level method,
It is characterized by: described be extended Boolean algebra system, the Boolean algebra system being expanded refers to: logic value set V
={ ф, 0,1, U }, variable are signal variable and switching variable, and signal variable and switching variable are two-valued variable, value set
Respectively subclass { 0,1 } and { ф, U }；
Signal variable logical value 1 and 0 respectively indicates the size of physical quantity related with signal properties；
Switching variable logical value U and ф indicate the size of physical quantity related with network element or node property；
Establish Boolean algebra system respectively in set { 0,1 } and { ф, U }, the Boolean algebra established on set { 0,1 } is letter
Number algebra, the Boolean algebra established on set { ф, U } are switching algebra, the formula and theorem of their available Boolean algebras
Carry out operation and abbreviation.
3. the logical expression of cmos transmission gate logic circuit according to claim 2 extracts and design at switch level method,
It is characterized by: constituting a four value cloth by the logic value set V and "AND", "or", " non-" three kinds of basic logic operations
That algebra system, four value variable ξ, η ∈ V, three kinds of basic logic operations are respectively defined as
1: ξ η@min (ξ, η) of formula,
2: ξ+η@max (ξ, η) of formula,
Formula 3:
For subclass { 0,1 } and { ф, U }, there are ordering relation 1 > 0 and U > ф, signal algebraical sum switching algebra difference respectively
It is the subalgebra of four value Boolean algebras on subclass { 0,1 } and { ф, U }；Increase a logical value threshold value 0.5 as 1 and 0
Cut off value, ordering relation are 1 >, 0.5 > 0, and threshold comparison operation is divided into low threshold comparison operation and high threshold comparison operation, defines respectively
For
Formula 4:
Formula 5:
Signal realizes that transistor unit is logical to the control action of signal to the control action of transistor unit by threshold comparison operation
AND operation realization is crossed, the controlled signal value collection of generation is combined into { ф, 0,1 }, and wherein signal variable value collection is combined into { 0,1 }；
It is defined on set { ф, U }n× { 0,1 }nOn operation be " line or " operation, reflect n controlled signal on its sys node
Interaction, on sys node, signal value collection is combined into { ф, 0,1, U }, and wherein signal variable value collection is combined into { 0,1 },
Logic value set V and five arithmetic expressions constitute the Boolean algebra system of an extension.
4. the logical expression of cmos transmission gate logic circuit according to claim 3 extracts and design at switch level method,
It is characterized by: the transistor unit refers to the control action of signal by AND operation realization: the switch state of metal-oxide-semiconductor
To the control action of input signal, indicates " to control " operation with AND operation, be defined as
Formula 6:
G is switching variable or switch function in formula, indicates the control action of metal-oxide-semiconductor, g ∈ { ф, U }；Symbol " [] " indicates input
Exciting signal source, y are input signal, y ∈ { 0,1 }；The output signal that the operation obtains after executing is controlled signal, value
Collection is combined into { ф, 0,1 }, and wherein ф is high-impedance state.
5. the logical expression of cmos transmission gate logic circuit according to claim 3 extracts and design at switch level method,
It is characterized by: the corresponding relationship of the end value of the threshold comparison operation and the signal variable value, corresponding relationship is with symbolIt indicates, is expressed as theorem formula 1:The corresponding relationship is considered as a kind of transformation, and direct transform is become by switch
Signal variable is changed in quantitative change, is expressed as with symbol " → " 0.5x→x；Inverse transformation changes to switch by signal variable contravariant
Variable is expressed as with symbol " ← "0.5X ← x,
What two series connection metal-oxide-semiconductor branches connected determines source transmission circuit x0.5y0.5[1] and0.5x0.5Y [0], is respectively converted into phase
The necessary condition for the change source transmission circuit answered, uses symbolIt indicates, is used in combinationIt indicates It indicatesThen it is
Theorem formula 2
Source transmission circuit is determined by what two metal-oxide-semiconductor branches of connecting connected, and the contravariant of one of metal-oxide-semiconductor control variable is as change
Source obtains change source transmission circuit to replace determining the metal-oxide-semiconductor in the transmission of source；
The PMOS tube branch and NMOS tube branch of the y of transmission respectively (1) and y (0) of two output end parallel connections, if its control variable is mutual
It is non-, then two input terminals can be connected in parallel y, obtain a cmos transmission gate branch, which can transmit signal without loss
Variable y, i.e. theorem formula 3
When it is significant level that it, which controls variable, if input signal is 1, PMOS tube and NMOS tube transmit signal 1 and 1t respectively,
It is acted on its sys node, generates signal 1；Actual physical process [2,5] is, as sys node level Vout≥(VDD-VTN)
Afterwards, NMOS tube transmission 1t signal terminates, and PMOS tube transmits 1 signal of signal until sys node level is supply voltage Shi Caijie
Beam；If input signal is 0, NMOS tube and PMOS tube transmit signal 0 and ot respectively, act on its sys node, generate signal
0；Actual physical process is, as sys node level Vout≤(-VPT) after, PMOS tube transmission ot signal terminates, NMOS tube transmission
0 signal just terminates when sys node level is ground level (0V)；When it is inactive level that it, which controls variable, two metal-oxide-semiconductors
It is turned off, output end is high-impedance state ф, violates constraint condition at this time, ф belongs to illegal state；
If the PMOS sub-network of f and the switch function of NMOS sub-network are respectivelyWithThen with equivalence of drawing a conclusion:
(1) the negative logic expression formula of the function is anti-, i.e. the negative logic expression formula of the function inverse function and the function inverse function
Positive logic expression formula dual formula each other；
(2) switch function of the PMOS sub-network of the function and the switch function of NMOS sub-network dual function each other；
(3) the PMOS sub-network and NMOS sub-network of the function dual network each other；
(4) switch-level function expression of the function is
Theorem formula 4
For the change source transmission series connection PMOS tube branch (x of function f0.5y0.5) [z], it enablesIndicate product item
The set of the level signal composition of contained function f=1,For product itemThe voltage signal collection of contained Z=0
It closes, ifThen the branch can transmit without lossU1 will not be generated
Level signal；
For function f change source transmission series connection NMOS branch (0.5x0.5Y) [z] is enabledIndicate product itemInstitute
The set of the level signal composition of the f=0 containing the function, { xy (z (1)) } are the voltage signal set of Z=1 contained by product item (xy),
If { xy (z (1)) } I { xyz (f (0)) }=empty set, the branch can transmit without lossU2 will not be generated
Level signal.
6. the logical expression of cmos transmission gate logic circuit according to claim 5 extracts and design at switch level method,
It is characterized by: in order to indicate interaction of the voltage signal transmitted on two branches of metal-oxide-semiconductor containing source on its sys node,
" line or " operation for defining two input signals or controlled signal on sys node is formula 7:
g1[y1]+g2[y2]@max(g1[y1],g2[y2]),
Constraint condition: work as y1≠y2When,Otherwise, y1=y2When, g1+g2=U,
When constraint condition is unsatisfactory for, the state of two input signals on sys node will be clashed, and form low resistive state U
Or be high-impedance state ф, in both cases, the value of output signal variable not can determine that setting is forbidden.
7. the logical expression of cmos transmission gate logic circuit according to claim 1 extracts and design at switch level method,
Corresponding switching stage signal flow diagram model is established by cmos transmission gate logic circuit refer to it is characterized by: described: CMOS transmission
The element legs of gate logic have PMOS tube branch, four class of NMOS tube branch, cmos transmission gate branch and line branch, wherein
PMOS tube and NMOS tube are single-groove road transmission gate, transmit 0 signal of 1 signal and transmission, cmos transmission gate branch without loss respectively
For double channel transmission gate, signal variable is transmitted without loss, this three classes branch is controlled branch, and line branch is uncontrolled branch
Road, is direct transmission branch, and the switch-level function expression of four class component branches is respectively
By given cmos transmission gate logic circuit, the signal stream artwork of element legs in cmos transmission gate logic circuit is utilized
Type obtains the switching stage signal flow diagram model of the circuit, and in switching stage signal flow diagram model, the arrow of branch road indicates signal
Transmission direction, switching variable or switch constant beside arrow are the control of the branch, and left and right two endpoints of the branch claim
For the node of signal flow diagram, the corresponding node signal of each node, wherein the node on the left side is known as source node or input node,
Connecting signal source, the node on the right are known as function node or output node, and connection loads, and the output signal on the node is controlled
Signal.
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