CN112632879B - Automatic method for reconstructing circuit diagram by using high-level hardware description language - Google Patents
Automatic method for reconstructing circuit diagram by using high-level hardware description language Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/323—Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses an automatic method for reconstructing a circuit diagram by using a high-level hardware description language, which comprises the following steps: establishing a unit library of all basic units of the circuit, wherein the unit library describes logic expressions of all the basic units in the circuit by using a high-level hardware language, and comprises names of the basic units and logic expressions corresponding to the basic units; in a circuit module in a netlist form to be converted, finding all triggers and defining output ends of the module as starting signals, performing recursive search on the starting signals, and reconstructing a logic expression of a high-level language of the starting signals, wherein the left side of the expression is the starting signals, and the right side of the expression is a Boolean expression taking the output signals of the triggers or the input signals of the module as variables; boolean expressions are reduced. The invention converts the digital circuit diagram of the graphic expression into the equivalent form of high-level hardware language description with high readability, simplifies the logic and greatly reduces the workload and difficulty of analyzing the digital circuit.
Description
Technical Field
The invention belongs to the field of electronic circuits, and particularly relates to an automatic method for reconstructing a circuit diagram by using a high-level hardware description language.
Background
In the inverse analysis technique of integrated circuits, the analysis and sorting of digital circuits is an important branch. The analysis and arrangement of the digital circuit is more and more challenging due to the large scale and complex logic structure.
Digital designs of modern integrated circuits are designed based on hardware language (Verilog, vhdl, etc.). The use of high-level hardware languages has the great advantage of clear logic and easy understanding, so that digital circuit design in the world today is basically performed entirely by means of high-level hardware languages.
However, in the field of chip reverse analysis, engineers need to reconstruct the internal structure of the chip from the digital layout, and the obtained digital circuit exists in a netlist form, and from the view point of graphics, see the interconnection combination of various basic units shown in fig. 1.
This type of circuit diagram is very unfavorable for the reverse analysis engineer to understand the function, and no software is currently available in the industry that can automatically convert the above-described type of circuit diagram into code described in a high-level hardware language.
Disclosure of Invention
In view of the above technical problems, the present invention provides a method for converting a netlist circuit diagram form of a digital circuit network into a high-level hardware language, which automatically converts the netlist form of the digital circuit diagram into a high-level hardware language description, and logically simplifies the generated hardware language expression to obtain a high-level hardware language code with high readability.
In order to solve the technical problems, the invention adopts the following technical scheme:
s10, establishing a unit library of all basic units of the circuit, wherein the unit library describes logic expressions of all the basic units in the circuit by using a high-level hardware language, and comprises names of the basic units and logic expressions corresponding to the basic units;
s20, finding all triggers and module output ends in a circuit module in a netlist form which needs to be converted;
s30, defining all signals at the D end of the trigger and the output signals of the module as starting signals, carrying out recursive search on the starting signals, and reconstructing a logic expression of a high-level language of the starting signals, wherein the left side of the expression is the starting signals, and the right side of the expression is a Boolean expression taking the output signals of the trigger or the input signals of the module as variables;
s40, simplifying the Boolean expression.
Preferably, the recursive search comprises the steps of:
finding the driving device of the signal from the starting signal, searching the driving device by taking all input ends of the driving device as starting points,
and repeatedly performing recursive calling, and marking the device which is used as the driving device in the calling process, and marking the device as a marked device set.
Preferably, the recursion call encounters a preset condition and recursively returns.
Preferably, the preset condition includes a trigger as a driving means of the signal.
Preferably, the preset condition includes a driving device to which a module input signal is a signal.
Preferably, the preset condition includes a device in the marked device set as a driving device.
Preferably, no expression is generated when a device in the marked device set is encountered as a driving device.
Preferably, the simplifying the boolean expression includes the following steps:
acquiring all input variable lists in the Boolean expression, wherein N is used for representing the total number of input variables;
traversing each possible combination of the input variable values, carrying out operation in the original expression, if the operation result is 1, reserving the input combination, otherwise discarding the input combination, and defining a set formed by all input combinations with the result of 1 as an ONES set;
performing cyclic search on the ONES set, setting the states of M input variables to be determined values in each cyclic process, wherein M is less than or equal to N-1, searching the whole ONES set, and if the number of the searched table entries is equal to 2 on the premise that the M variables are determined values N-M Regardless of the variation of variables other than M input variables, the output of the logic expression is not affected, and irrelevant items which have no influence on the output are removed;
the previous step is repeated until all input states are traversed.
The invention has the following beneficial effects: the method fills the blank of the prior digital circuit netlist analyzing and understanding tool, the digital circuit netlist analyzing and understanding is carried out by arranging digital units into a graph form which is easy to understand on graph by means of a foreign large EDA tool in the prior art, the digital circuit is understood on the level of a circuit diagram essentially, and the digital circuit cannot rise to the level of high-level hardware languages, such as verilog, vhdl and the like. The method of the invention can be realized by an automatic method, can efficiently convert the digital circuit diagram of the graphic expression into an equivalent form of high-level hardware language description with high readability, and is logically simplified, thereby greatly reducing the workload and difficulty of analyzing the digital circuit. At least comprising the following advantages:
1. the netlist circuit is programmed to obtain an equivalent circuit form of high-level language description, so that the efficiency is high;
2. simplifying the circuit form of the high-level language description, so that the analysis personnel can understand the circuit form conveniently;
3. automatically discovering a combinational logic loop in a program;
4. and the automatic execution avoids the possibility of manual analysis errors.
Drawings
FIG. 1 is a diagram of the reconstruction result of a digital circuit diagram in the prior art;
FIG. 2 is a flow chart of steps of an automated method for reconstructing a circuit diagram in a high-level hardware description language in accordance with an embodiment of the present invention;
FIG. 3 is a schematic diagram of the basic unit logic expression of an automated method of reconstructing a circuit diagram in a high-level hardware description language, in accordance with one embodiment of the present invention;
FIG. 4 is a schematic diagram of a netlist representation of an automated method of reconstructing a circuit diagram in a high-level hardware description language in accordance with a further embodiment of the invention;
FIG. 5 is a schematic diagram of a high-level language logic representation corresponding to a netlist form of an automated method of reconstructing a circuit diagram in a high-level hardware description language in accordance with a further embodiment of the present invention;
FIG. 6 is a schematic diagram of an ONES set of logical expressions of an automated method of reconstructing a circuit diagram in a high-level hardware description language in accordance with another embodiment of the invention;
FIG. 7 is a diagram of ONES set search statistics for an automated method of reconstructing a circuit diagram in a high-level hardware description language, in accordance with another embodiment of the invention;
FIG. 8 is a schematic diagram of an ONES set of logical expressions of an automated method of reconstructing a circuit diagram in a high-level hardware description language in accordance with yet another embodiment of the invention;
FIG. 9 is a diagram of ONES set search statistics for an automated method of reconstructing a circuit diagram in a high-level hardware description language, in accordance with yet another embodiment of the invention;
fig. 10 is a diagram showing the re-search statistics of the ons set of an automated method of reconstructing a circuit diagram in a high-level hardware description language according to still another embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
Referring to fig. 2, the present invention discloses an automated method of reconstructing a circuit diagram in a high-level hardware description language,
the method comprises the following steps:
s10, establishing a unit library of all basic units of the circuit, wherein the unit library describes logic expressions of all the basic units in the circuit by using a high-level hardware language, and comprises names of the basic units and logic expressions corresponding to the basic units, and referring to FIG. 3, the names of the basic units are on the left side, and the logic expressions corresponding to the basic units are on the right side;
s20, finding all triggers and module output ends in a circuit module in a netlist form which needs to be converted; referring to fig. 4, 10 is a flip-flop, and 20 is a module output;
s30, defining all signals at the D end of the trigger and the output signals of the module as starting signals, carrying out recursive search on the starting signals, and reconstructing a logic expression of a high-level language of the starting signals, wherein the left side of the expression is the starting signals, and the right side of the expression is a Boolean expression taking the output signals of the trigger or the input signals of the module as variables; referring to FIG. 5, there is shown a high-level linguistic logic expression of the departure signal of the netlist-form circuit block shown in FIG. 4 after recursion of the block;
s40, simplifying the Boolean expression.
In a specific embodiment, the recursive search comprises the steps of:
finding the driving device of the signal from the starting signal, searching the driving device by taking all input ends of the driving device as starting points,
and repeatedly performing recursive calling, and marking the device which is used as the driving device in the calling process, and marking the device as a marked device set.
Recursion calling, namely recursion returning when a preset condition is met; the preset condition includes a trigger as a driving device of the signal, a module input signal as a driving device of the signal, and a device in the marked device set as a driving device.
Upon encountering a device in the marked device set as a driving device, no expression is generated. This corresponds to a combinational logic loop, which is also of great importance for the analysis of the circuit, from which all combinational logic loops in the circuit module can be automatically found.
Example 2
The logic expression obtained in S30 is obtained by recursively calling and reconstructing the original circuit diagram, so that the expression structure completely reflects the structural relation of the original circuit diagram. Such boolean expressions, while easier to understand than circuit diagrams, are not the simplest and most easily understood form. For a simplified understanding of boolean expressions, carnot (m.karnaugh) has proposed a well-known carnot reduction in 1953. However, the carnot reduction method has been very difficult when the expression for processing more than 6 variables is simplified. Therefore, the invention uses an automatic method, discards the Gray code idea in the Carnot reduction on the basis of the Carnot reduction, and directly uses the operation capability of a modern computer to carry out traversal operation to carry out logic expression reduction.
The formula basis on which this reduction depends is: ab+a to b=a
The simplification process is as follows:
get all input variable lists in boolean expression, in the specific embodiment, boolean expression Y in S30, input variable list is A, B, C, D:
Y＝
(A&B&～C&D)|(～A&B&～C&D)|(A&～B&～C&D)|(～A&～B&～C&D)|(～A&B&C&D)|(～A&～B&C&D)|(A&B&C&D)|(A&～B&C&D)|(A&B&～C&～D)|(A&B&C&～D)
is marked as a formula I;
for each possible combination of the input variable values, traversing, carrying out the operation in the original expression, and if the operation result is 1, reserving the input combination, otherwise discarding the input combination. For convenience of description, we define a set of all input combinations that make the result 1 as an ONES set, which can be understood as essentially a truth table of boolean expressions, and can be intuitively understood by expressing the ONES set as shown in fig. 6, ABCD represents a variable name, the preceding +number represents a value of 1, and the-number represents a value of 0. For example, taking the first line of fig. 6 as an example, when the D, C input variable takes 0 and the b, a input variable takes 1, the expression output is true. Fig. 6 is a set of ons generated by this expression.
In combination with the input variables, search statistics are performed on the ons set, which is the core of the whole reduction process: taking the expression of one such 4-variable input as an example for illustration, more variables can be analogized.
First, find out the situation that the single variable input is fixed to a certain definite value, how many table entries exist in ONES, if the number of table entries is 8, it means that the influence of this variable input to the logic result directly shields the influence of all other input variables, and the other variables can be eliminated, in FIG. 6, +D has 8 entries, which means that the output of the expression must be 1 as long as D is 1, so all ONES table entries containing +D entries can be combined to obtain the result shown in FIG. 7;
example 3
After the univariate lookup is completed (whether or not the ONES entries are merged), it starts to find bivariate, in a specific embodiment, boolean expression Y in S30,
Y＝
(～A&B&～C&D)|(A&～B&～C&D)|(～A&～B&～C&D)|(～A&B&C&D)|(～A&～B&C&D)|(A&B&C&D)|(A&～B&C&D)|(A&B&～C&～D)|(A&B&C&～D)
the second is marked as a second;
in the case of single variable, the search for double variable is started because no simplification term is searched, and in the case of searching double variable, it can be found that when both variable D and variable C take values of 1, there are 4 terms of ONES entry values of 1, which means that as long as D and C inputs are 1 at the same time, the expression output must be 1, irrespective of the values of other variables. The ONES entries are then as shown in FIG. 8, and can be reduced to the form shown in FIG. 9;
the search for the remaining partial inputs then continues to be entered at some determined value and eventually may continue to be reduced to the form shown in fig. 10.
Summarizing the above, simplifying the boolean expression comprises the following steps:
acquiring all input variable lists in the Boolean expression, wherein N is used for representing the total number of input variables;
traversing each possible combination of the input variable values, carrying out operation in the original expression, if the operation result is 1, reserving the input combination, otherwise discarding the input combination, and defining a set formed by all input combinations with the result of 1 as an ONES set;
performing cyclic search on the ONES set, setting the states of M input variables to be determined values in each cyclic process, wherein M is less than or equal to N-1, searching the whole ONES set, and if the number of the searched table entries is equal to 2 on the premise that the M variables are determined values N-M Regardless of the variation of variables other than M input variables, the output of the logic expression is not affected, and irrelevant items which have no influence on the output are removed;
the previous step is repeated until all input states are traversed.
After the above-described cyclic search, the ONES set is reduced to a simplest form, which corresponds to a reduced-node and-or expression equivalent structure of the reduced Boolean expression.
In a specific embodiment, for equation one, the final reduction result is denoted as assignment Y as:
assign Y＝(
(A&B&～C)|
(A&B&C)|
(D))；
for equation two, the final reduction result is denoted as assignment Y as:
assign Y＝(
(C&D)|
(～B&D)|
(～A&D)|
(A&B&～D))。
it should be understood that the exemplary embodiments described herein are illustrative and not limiting. Although one or more embodiments of the present invention have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.
Claims (7)
1. An automated method for reconstructing a circuit diagram in a high-level hardware description language, comprising the steps of:
s10, establishing a unit library of all basic units of the circuit, wherein the unit library describes logic expressions of all the basic units in the circuit by using a high-level hardware language, and comprises names of the basic units and logic expressions corresponding to the basic units;
s20, finding all triggers and module output ends in a circuit module in a netlist form which needs to be converted;
s30, defining all signals at the D end of the trigger and the output signals of the module as starting signals, carrying out recursive search on the starting signals, and reconstructing a logic expression of a high-level language of the starting signals, wherein the left side of the expression is the starting signals, and the right side of the expression is a Boolean expression taking the output signals of the trigger or the input signals of the module as variables;
s40, simplifying the Boolean expression;
the simplifying the Boolean expression comprises the following steps:
acquiring all input variable lists in the Boolean expression, wherein N is used for representing the total number of input variables;
traversing each possible combination of the input variable values, carrying out operation in the original expression, if the operation result is 1, reserving the input combination, otherwise discarding the input combination, and defining a set formed by all input combinations with the result of 1 as an ONES set;
performing cyclic search on the ONES set, setting the states of M input variables to be determined values in each cyclic process, wherein M is less than or equal to N-1, searching the whole ONES set, and if the number of the searched table entries is equal to 2 on the premise that the M variables are determined values N-M Regardless of the variation of variables other than M input variables, the output of the logic expression is not affected, and irrelevant items which have no influence on the output are removed;
the previous step is repeated until all input states are traversed.
2. An automated method of reconstructing a circuit diagram in a high-level hardware description language according to claim 1, wherein said recursive search comprises the steps of:
finding the driving device of the signal from the starting signal, searching the driving device by taking all input ends of the driving device as starting points,
and repeatedly performing recursive calling, and marking the device which is used as the driving device in the calling process, and marking the device as a marked device set.
3. An automated method of reconstructing a circuit diagram in a high-level hardware description language according to claim 2, wherein the recursive call encounters a preset condition and returns recursively.
4. An automated method of reconstructing a circuit diagram in a high-level hardware description language according to claim 3, wherein the predetermined condition comprises a trigger-driven device as a signal.
5. An automated method of reconstructing a circuit diagram in a high-level hardware description language according to claim 3, wherein the predetermined condition comprises a driving device of a module input signal as a signal.
6. An automated method of reconstructing a circuit diagram in a high-level hardware description language according to claim 3, wherein the preset condition comprises a device in the marked device set as a driving device.
7. An automated method of reconstructing a circuit diagram in a high-level hardware description language according to claim 6, wherein no expression is generated when a device in the marked device set is encountered as a driving device.
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