CN110263296B - Matrix vector multiplier based on photoelectric calculation array and operation method thereof - Google Patents
Matrix vector multiplier based on photoelectric calculation array and operation method thereof Download PDFInfo
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Abstract
The invention discloses a matrix vector multiplier based on a photoelectric calculation array and an operation method thereof. The multiplier comprises a photoelectric calculation array and an analog-to-digital converter, wherein the photoelectric calculation array is formed by periodically arranging m × n photoelectric calculation units; each photoelectric calculation unit comprises a light-emitting unit and a calculation unit, each calculation unit comprises a light input end and a result output end, and light emitted by the light-emitting unit is incident to the light input end of the corresponding calculation unit; the result output ends of the calculation units in each row are sequentially connected, and the current signals output by the calculation units in each row are respectively input into an analog-to-digital converter or the current signals output by the calculation units in multiple rows are input into the analog-to-digital converter together. The method of the invention can save a large amount of power consumption and area and greatly improve the precision of the calculation result.
Description
Technical Field
The invention relates to a matrix vector multiplier based on a photoelectric calculation array and an operation method thereof, belonging to the field of calculation and photoelectric detection.
Background
Most of the conventional computers adopt the von neumann architecture, however, because the von neumann architecture is separated from the memory unit, the great energy consumption is generated on the data transmission, and the operation speed is influenced. The photoelectric computing unit is a computing device which can carry out independent operation or operation in combination with the current electronic computing technology, and is characterized in that: the single device can realize the storage-computation integration function, has good integration level, high energy efficiency ratio and strong compatibility, and is very suitable for accelerating a series of algorithms represented by neural network algorithms and CT algorithms and requiring a large amount of operation matrix vector multiplication. If the photoelectric computing units are combined into a large photoelectric computing array, various complex operation acceleration functions can be realized.
For large-scale matrix vector operation, in the existing photoelectric calculation array, a corresponding analog-to-digital converter is needed for a read-out area of each column of calculation units. When the matrix size reaches a certain degree, the number of analog-to-digital converters is increased sharply, which leads to increased power consumption and reduced energy efficiency. And when the number of the analog-to-digital converters is too large, the difficulty of integration in a single chip is increased, and the cost and risk of tape-out are greatly increased. Meanwhile, for an application scenario with a high requirement on calculation accuracy, a matrix vector multiplier based on a photoelectric calculation unit brings a large operation error. One common method for reducing errors is to use an analog-to-digital converter with a higher bit number, but with the improvement of the conversion bit number and the conversion precision, the area and the power consumption of the analog-to-digital converter are doubled and increased, and the conversion bit number of the digital-to-analog converter in the current market is generally below 16 bits, which cannot meet the calculation requirements of the photoelectric calculation unit.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a matrix vector multiplier based on a photoelectric calculation array and an operation method thereof.
The technical scheme adopted by the invention is as follows:
a matrix vector multiplier based on a photoelectric calculation array comprises the photoelectric calculation array and an analog-to-digital converter, wherein the photoelectric calculation array is formed by periodically arranging m × n photoelectric calculation units, m is the number of rows, and n is the number of columns; each photoelectric calculation unit comprises a light-emitting unit and a calculation unit, each calculation unit comprises a light input end and a result output end, and light emitted by the light-emitting unit is incident to the light input end of the corresponding calculation unit; the result output ends of each column of calculating units are connected in sequence, and the current signals output by the plurality of columns of calculating units are input to an analog-to-digital converter together. Or the result output ends of the calculation units in each column are connected in sequence, and the current signals output by the calculation units in each column are respectively input into an analog-to-digital converter.
Further, the calculation unit comprises a carrier control region, a coupling region, a photogenerated carrier collecting region and a readout region; the carrier control region is used for controlling and modulating carriers in the photon-generated carrier collecting region and the reading region; the collecting regions in the photogenerated carrier collecting region and the reading region are used for absorbing photons emitted by the light emitting unit and collecting generated photogenerated carriers; the charge carrier control region or the photogenerated charge carrier collecting region and the reading region are connected with an electric signal, and the reading region is used for outputting charge carriers acted by the photogenerated charge carriers and the electric signal; the coupling region connects the collection region and the readout region.
Furthermore, in the photoelectric calculation array, the reading areas of the calculation units in each column are sequentially connected, and the carrier control areas of the calculation units in each row are sequentially connected.
The operation method of the matrix vector multiplier of the multiplexing analog-digital converter comprises the following steps:
(1) arranging m × n photoelectric computing units into a unit array with the same number of rows and columns as that of the matrix to be multiplied, wherein each computing unit comprises a carrier control area, a coupling area, a photo-generated carrier collecting area and a reading area; in the unit array, the photon-generated carrier collecting region of each column of computing units is connected with the output end of the reading region in sequence, and the carrier control regions of each row of computing units are connected in sequence;
(2) the light-emitting unit emits light signals which are set as data in a matrix to be multiplied, and the light signals are incident to the input ends of a photo-generated carrier collecting region and a reading region of the corresponding calculating unit and are used as matrix data input ends of a matrix vector multiplier; the carrier control region input of each row of computing units is the carrier set to represent each element in the vector, and is the vector data input end of the matrix vector multiplier; after the data of each element in the vector is converted into binary, serially inputting carriers representing the binary data into carrier control areas of each row according to bits;
(3) the output ends of the photogenerated carrier collecting region and the reading region of the computing unit output carriers which are subjected to the common action of matrix data and vector data and output the carriers in a current mode under the drive of fixed voltage, all current values of each column of the computing unit are converged to obtain an analog addition result, the analog addition results of a plurality of columns are input into an analog-to-digital converter together, analog-to-digital conversion is carried out on the analog addition result of each column through a control address, then shift operation is carried out according to input bits, and then accumulation is carried out to obtain a result vector.
The other block input operation method of the matrix vector multiplier is as follows:
(1) arranging m × n photoelectric computing units into a unit array with the same number of rows and columns as that of the matrix to be multiplied, wherein each computing unit comprises a carrier control area, a coupling area, a photo-generated carrier collecting area and a reading area; in the unit array, the photon-generated carrier collecting region of each column of computing units is connected with the output end of the reading region in sequence, and the carrier control regions of each row of computing units are connected in sequence;
(2) the light-emitting unit emits light signals which are set as data in a matrix to be multiplied, and the light signals are incident to the input ends of a photo-generated carrier collecting region and a reading region of the corresponding calculating unit and are used as matrix data input ends of a matrix vector multiplier; the carrier control region input of each row of computing units is the carrier set to represent each element in the vector, and is the vector data input end of the matrix vector multiplier; dividing the unit array into a plurality of block units, expanding according to bit positions and parallelly inputting carriers representing binarized data to each row of carrier control areas of each block unit in a time-sharing manner after data of each element in the vector is converted into binary; when vector data are input into a certain block unit, zero padding is carried out on other data in the vector to enable the length of the vector to be consistent with the length of an original vector;
(3) the output ends of the photo-generated carrier collecting region and the reading region of the calculating unit output carriers under the common action of matrix data and vector data and output the carriers in a current mode under the drive of fixed voltage, the current values of all the block units form intermediate results after analog-to-digital conversion, and the intermediate results are integrated into a final calculating result according to the division mode of the unit array.
The invention provides two improved matrix vector multipliers and operation methods thereof based on a photoelectric calculation array, and the matrix vector multipliers and the operation methods thereof respectively have the following advantages:
(1) by adopting an analog-digital conversion multiplexing method, at least half of resources of the analog-digital converter can be saved on the basis of completing the original calculation task, and the cost and the risk of the tape-out are reduced while the power consumption and the area are saved.
(2) The block calculation method improves the precision of intermediate calculation results by time-sharing control excitation input, thereby improving the calculation precision of final results.
Drawings
FIG. 1 is a multi-function region block diagram of a computing unit.
Fig. 2 is a schematic structural diagram of a photoelectric computing array.
Fig. 3 is (a) a sectional view and (b) a perspective view of the structure of the calculation unit of embodiment 1.
Fig. 4 is (a) a sectional view and (b) a perspective view of a calculation unit structure of embodiment 2.
FIG. 5 is (a) a schematic view of the structure and (b) a schematic view of the multi-functional area of the calculation unit of example 3.
Fig. 6 is an AD multiplexed serial matrix vector multiplier.
FIG. 7 is a block-wise input diagram of a high-precision matrix vector multiplier calculation.
FIG. 8 is a block diagram of a high precision matrix vector multiplier with block inputs.
In the figure: 1-light emitting array, 2-computational array.
Detailed Description
The calculating unit in the photoelectric calculating unit of the invention is a multifunctional area structure comprising three functional areas, as shown in fig. 1, the three functional areas are: the charge carrier control region, the coupling region, the photon-generated charge carrier collecting region and the reading region have the following specific functions:
carrier control region: the photoelectric calculating unit is used for controlling and modulating carriers in the photoelectric calculating unit, and is used as an electric input port of the calculating unit, and one of the operation quantities is input as an electric input quantity; or only the carriers in the calculating unit are controlled and modulated, and the electric input quantity is input through other areas.
A coupling region: the photoelectric calculating unit is used for connecting the photogenerated carrier collecting region and the reading region, so that photogenerated carriers generated by photon incidence act on carriers in the photoelectric calculating unit to form an operational relation.
Photocarrier collection region and readout region: the collecting region is used for absorbing incident photons and collecting generated photon-generated carriers, and is used as an optical input port of the calculating unit, and one of the operation quantities is input as an optical input quantity; the readout region can be used as an electrical input port of the calculation unit, inputs one of the operation quantities as an electrical input quantity, and is used as an output port of the calculation unit, and outputs carriers acted by the optical input quantity and the electrical input quantity as a unit output quantity; or the electric input quantity is input through other areas, the reading area is only used as an output port of the calculation unit, and the carriers acted by the optical input quantity and the electric input quantity are output as the unit output quantity.
The light emitted by the light-emitting unit is used as photons incident on the photon-generated carrier collecting and reading area of the calculating unit to participate in operation. The photoelectric calculation array comprises a light emitting array 1 and a calculation array 2, and the structure is shown in FIG. 2. The light emitting array 1 is composed of a plurality of light emitting units which are periodically arranged, and the calculating array 2 is composed of a plurality of calculating units which are periodically arranged.
Example 1
As shown in fig. 3, the calculation unit of the present embodiment includes: the photoelectric readout device comprises a control grid serving as a carrier control region, a charge coupling layer serving as a coupling region and a P-type substrate serving as a photon-generated carrier collecting region and a readout region, wherein the P-type substrate is divided into a left collecting region and a right readout region, and the right readout region comprises a shallow trench isolation, and an N-type source end and an N-type drain end which are formed by ion implantation. The shallow trench isolation is located in the middle of the semiconductor substrate, the collection region and the readout region, and is formed by etching and filling silicon dioxide so as to isolate electric signals of the collection region and the readout region. The N-type source end is positioned on one side, close to the bottom dielectric layer, in the reading area and is formed by doping through an ion implantation method. The N-type drain terminal is positioned on the other side, opposite to the N-type source terminal, of the semiconductor substrate close to the bottom layer dielectric layer, and is formed by a doping method through an ion implantation method. It should be understood that references herein to left, right, above and below merely represent relative positions as viewed through the viewing angles shown in the figures as a function of viewing angle and are not to be construed as limitations on the particular structure.
And applying a pulse with a negative voltage range or applying a pulse with a positive voltage range on the control gate on the substrate in the collecting region to generate a depletion layer for collecting photoelectrons in the substrate in the collecting region, and reading out the quantity of the collected photoelectrons through the right read-out region as the input quantity of the optical input end. When reading, a positive voltage is applied to the control grid electrode to form a conductive channel between the N-type source end and the N-type drain end of the collecting region, and then a bias pulse voltage is applied between the N-type source end and the N-type drain end to accelerate electrons in the conductive channel to form a current between the source and the drain. And current carriers are formed in a channel between the source and the drain and are acted by the control gate voltage, the source and the drain voltage and the number of photoelectrons collected by the collecting region together to serve as electrons acted by the light input quantity and the electric input quantity, and the electrons are output in a current form, wherein the control gate voltage and the source and the drain voltage can serve as the electric input quantity of the device, and the number of photoelectrons serves as the light input quantity of the device.
The charge coupling layer of the coupling region is used for connecting the collecting region and the reading region, so that the surface potential of the collecting region substrate can be influenced by the quantity of collected photoelectrons after the depletion region in the collecting region substrate starts to collect the photoelectrons; through the connection of the charge coupling layer, the surface potential of the semiconductor substrate in the reading region is influenced by the surface potential of the semiconductor substrate in the collecting region, so that the magnitude of the current between the source and the drain of the reading region is influenced, and the quantity of photoelectrons collected in the collecting region is read by judging the current between the source and the drain of the reading region;
and the control gate of the carrier control region is used for applying a pulse voltage to the control gate so as to generate a depletion region for exciting photoelectrons in the P-type semiconductor substrate readout region, and can also be used as an electrical input end for inputting one bit of operand.
In addition, a bottom dielectric layer for isolation is arranged between the P-type semiconductor substrate and the charge coupling layer; a top dielectric layer for isolation is also present between the charge coupling layer and the control gate.
Example 2
As shown in fig. 4, the calculation unit of the present embodiment includes: the semiconductor device comprises a control grid serving as a carrier control area, a charge coupling layer serving as a coupling area, and a P-type semiconductor substrate serving as a photon-generated carrier collecting area and a readout area, wherein the P-type semiconductor substrate comprises an N-type source end and a drain end which are formed through ion implantation. The P-type semiconductor substrate can simultaneously undertake the tasks of sensitization and readout. The N-type source end is positioned on one side, close to the bottom dielectric layer, in the reading area and is formed by doping through an ion implantation method. The N-type drain terminal is positioned on the other side, opposite to the N-type source terminal, of the semiconductor substrate close to the bottom layer dielectric layer, and is formed by a doping method through an ion implantation method.
When the light is sensed, a pulse with a negative voltage range is applied to the P-type semiconductor substrate, and a pulse with a positive voltage range is applied to the control grid serving as a carrier control region, so that a depletion layer for collecting photoelectrons is generated in the P-type substrate, electrons generated in the depletion region are accelerated under the action of an electric field between the control grid and two ends of the P-type substrate, and when the electrons reach the state of obtaining enough high energy, the electrons penetrate through a bottom dielectric layer barrier between the P-type substrate and a charge coupling layer, enter the charge coupling layer and are stored in the charge coupling layer, the quantity of the charges in the charge coupling layer can influence the threshold value when the device is started, and further influence the magnitude of the current between a source and a drain during reading; during reading, a pulse voltage is applied to the control gate to form a conducting channel between the N-type source end and the N-type drain end, and then a pulse voltage is applied between the N-type source end and the N-type drain end to accelerate electrons in the conducting channel to form a current between the source and the drain. The current between the source and the drain is acted by the control grid pulse voltage, the source and the drain voltage and the number of electrons stored in the charge coupling layer together, and is used as electrons acted by the light input quantity and the electric input quantity to be output in the form of current, wherein the control grid voltage and the source and drain voltage can be used as the electric input quantity of the device, and the number of photoelectrons stored in the charge coupling layer is used as the light input quantity of the device.
The charge coupling layer of the coupling region is used for storing photoelectrons entering the charge coupling layer, and the threshold value of the device during reading is changed, so that the current between the source and the drain of the reading region is influenced, and the quantity of the photoelectrons which are generated during sensitization and enter the charge coupling layer is read by judging the current between the source and the drain of the reading region.
And the control gate of the carrier control region is used for applying a pulse voltage to the control gate so as to generate a depletion region for exciting photoelectrons in the P-type semiconductor substrate readout region, and can also be used as an electrical input end for inputting one bit of operand.
In addition, a bottom dielectric layer for isolation is arranged between the P-type semiconductor substrate and the charge coupling layer; a top dielectric layer for isolation is also present between the charge coupling layer and the control gate.
Example 3
As shown in fig. 5, the calculation unit of the present embodiment includes: photodiodes and readout tubes as photogenerated carrier collection and readout regions, wherein the photodiodes are formed by ion doping and are responsible for the photosensitization. The N region of the photodiode is connected to the control grid of the read-out tube and the source end of the reset tube through a photoelectron coupling lead wire as a coupling region, and a positive voltage pulse is applied to the drain end of the read-out tube to be used as the driving voltage of the read-out current; before exposure, the reset tube is opened, the voltage of the drain end of the reset tube is applied to the photodiode, so that the photodiode serving as a collecting region is in a reverse bias state, and a depletion layer is generated; during exposure, the reset tube is turned off, the photodiode is electrically isolated, photons are incident on the depletion region of the photodiode to generate photoelectrons which are accumulated in the diode, and the N region of the diode and a read tube electrically connected with the N region through a photoelectron coupling lead serving as a coupling region control the gate potential to start to fall, thereby influencing the electron concentration in the channel of the read tube. The reading tube is responsible for reading, a positive pulse voltage is applied to the drain terminal of the reading tube, the source terminal is connected with the drain terminal of the addressing tube, the addressing tube is opened during reading, current is generated in the reading tube, the current is influenced by the voltage of the drain terminal of the resetting tube, the voltage of the drain terminal of the reading tube and the number of incident photons, electrons in a channel of the reading tube are output in a current mode as electrons acted by the light input quantity and the electric input quantity, wherein the voltage of the drain terminal of the resetting tube and the voltage of the drain terminal of the reading tube can be used as the electric input quantity of a device, and the number of the incident photons is the light input quantity of the device.
The opto-electronic coupling lead of the coupling region is used to connect the photodiode as a collection region in the photogenerated carrier collection and readout region and the readout tube as a readout region, with a photodiode N-region potential applied to the readout tube control gate.
The reset tube as carrier control area inputs a positive voltage to act on the photodiode through its drain terminal, when the reset tube is opened, the positive voltage acts on the photodiode to make the photodiode produce depletion area and sense light, and at the same time, it can also be used as electric input terminal to input one bit of operation quantity.
In addition, the addressing pipe is used for controlling the output of the output current of the whole operation device as an output quantity, and can be used for row and column addressing when the photoelectric calculation units form an array.
Example 4
In this embodiment, an AD multiplexing serial matrix vector multiplier is formed by using a plurality of light emitting units and the calculating unit in embodiment 1, so as to implement multiplication of one matrix and one vector, whose dimensions conform to the matrix vector multiplication rule.
Take the example of computing the multiplication operation a × W of vector a and matrix W, where a is 1 × 8 vector and each data bit in the vector is 8 bits wide. W is an 8 × 8 matrix, as shown in formula (1), the calculation diagram is shown in fig. 6, and a box unit marked with a character V in the diagram represents an adopted photoelectric calculation unit, wherein elements in the vector a are input through an electric input end, and elements in the matrix W are input through an optical input end.
Firstly, the elements of each of a are binary-transformed in the control system:
arranging the computing units into an array in the form shown in fig. 6, wherein the number of rows of the array is 8, the number of columns of the array is 8, and connecting the control gates of all the computing units in the same row of the array as a carrier control region, and inputting the same electrical input data; the output ends of the P-type substrates of all the calculation units in the same column of the array, which are used as a carrier collecting area and a reading-out area, are connected, so that the output currents are gathered and added.
When in input, 8 × 8 data in the matrix are sequentially input into 8 × 8 computing units through the optical input end; serially inputting elements in the vector from control gates connected with the same row unit, sequentially inputting binary data of different bits of the same element in a time-sharing mode, and multiplying the elements in the matrix and the binary data of the lowest bit of the elements in the vector by corresponding bits when the data of the lowest bit is input on the control gates, namely performing operation (1):
before current convergence, 8 × 8 computing unit arrays respectively obtain the computing results of each unit:
and then, the output current circuit connected with the output end of each row is equal to the output current circuit which is subjected to addition operation according to the rows, and after the result (4) is subjected to convergence addition, the output of the lowest matrix vector multiplication output end is as follows:
the result is the operation result of equation (4), and the matrix-vector multiplication of the lowest bit of the vector and the matrix is completed. In this case, the 8 intermediate aggregated current results need to be subjected to analog-to-digital AD conversion, as shown in fig. 6, 8 columns of current multiplex one multi-input selection AD converter (or one AD converter may be shared by every 2, 3, and 4 … … 7 columns), addr _ sel in the figure is an address selection signal, and the AD conversion is performed on the 8 intermediate calculation results through address selection of the control system, so as to obtain digital quantities.
Inputting the result after AD conversion into a control system, shifting the result to the left by 0 bit because the result is the lowest bit, then inputting the second lowest bit of the vector into a control grid as the data of an electrical input end to obtain the matrix vector multiplication result of the second highest bit of the vector and the matrix, shifting the result to the left by 1 bit after inputting the result into the control system, and carrying out vector addition with the previous matrix multiplication result and the previous lowest bit of the vector, and so on, serially inputting all the binary data of the bits of the vector, and sequentially shifting and accumulating the binary data in the control system to obtain the middle matrix vector operation result, which is equivalent to carrying out the following operations:
the final matrix vector multiplication calculation result is obtained.
The control system can adopt a digital circuit, and also can adopt various logic control units such as a computer, a singlechip, an FPGA and the like.
Example 5
The present embodiment uses a plurality of light emitting units and the calculating unit of embodiment 1 to form a high-precision matrix vector multiplier with block inputs, so as to realize multiplication of one matrix and one vector, the dimensions of which conform to the matrix vector multiplication rule.
The calculation units are arranged in an array in the form shown in fig. 7, and basically the same as the structure of embodiment 4 except that one AD converter is used for each column of calculation units. Of course, the block input method of the present embodiment can also be implemented using the structure of fig. 6.
Take the example of computing the multiplication operation a × W of vector a and matrix W, where a is 1 × 8 vector and each data bit in the vector is 8 bits wide. When in input, 8 × 8 data in the matrix are sequentially input into 8 × 8 computing units through the optical input end; the elements in the vector are serially input from the control gates connected with the same row unit, the binary data of different bits of the same element are sequentially input in a time-sharing mode, and when the data of the lowest bit is input to the control gates, the elements in the matrix and the binary data of the lowest bit of the elements in the vector are multiplied by the corresponding bit, namely, the operation of the formula (1) is performed.
Before current convergence, the calculation result of each unit is respectively formula (4) through an output current circuit with the output ends of each column connected, namely, column-by-column addition operation is performed, after the result (4) is converged and added, the output end of the lowest matrix vector multiplication is formula (5), the result is the operation result of formula (4), and the matrix vector multiplication operation of the lowest bit of the vector and the matrix is completed. If the current convergence values of the respective columns obtained at this time are directly subjected to AD conversion, since the bit width of each element in the W matrix is 6 bits, and the final result of addition of 8 elements of 6 bits per column is 9 bits, a certain accuracy is lost when conversion is performed using an 8-bit AD converter. So in the formula (3)Input vector excitation [ A ]11A21…A81]In the process, a block input method is adopted, and the operation of the formula (3) is split into the following formulas (7) and (8):
at the moment, the 8-number accumulation is split into two times of 4-number accumulation operations, 4 6-bit numbers are accumulated into 8 bits, and the precision can not be lost after the 8-bit AD converter is used for conversion.
The result of each bit is calculated in blocks, and then accumulated to obtain the final calculation result of the bit, as shown in fig. 8. Where T0 and T1 represent two portions of the time-shared input excitation vector.
Inputting the result after AD conversion into a control system, shifting the result to the left by 0 bit because the result is the lowest bit, then using the second lowest bit of the vector as the data of an electrical input end to input into a control grid to obtain the matrix vector multiplication result of the second highest bit of the vector and the matrix, shifting the result to the left by 1 bit after inputting into the control system, and carrying out vector addition with the previous vector lowest bit and the matrix multiplication result, and so on, serially inputting all the binary data of the bits of the vector, and finally after the addition of the block calculation results of all the bits is finished, sequentially shifting and accumulating in the control system to obtain the middle matrix vector operation result, which is equivalent to carrying out the following operations:
the final matrix vector multiplication calculation result is obtained.
The control system can adopt a digital circuit, and also can adopt various logic control units such as a computer, a singlechip, an FPGA and the like.
Claims (4)
1. A matrix vector multiplier based on a photoelectric calculation array comprises the photoelectric calculation array and an analog-to-digital converter, and is characterized in that the photoelectric calculation array is formed by periodically arranging m × n photoelectric calculation units, wherein m is the number of rows and n is the number of columns; each photoelectric calculation unit comprises a light-emitting unit and a calculation unit, each calculation unit comprises a light input end and a result output end, and light emitted by the light-emitting unit is incident to the light input end of the corresponding calculation unit; the result output ends of each row of computing units are connected in sequence, and current signals output by the multiple rows of computing units are input to an analog-to-digital converter together; the calculation unit comprises a carrier control region, a coupling region, a photon-generated carrier collecting region and a readout region; the carrier control region is used for controlling and modulating carriers in the photon-generated carrier collecting region and the reading region; the collecting regions in the photogenerated carrier collecting region and the reading region are used for absorbing photons emitted by the light emitting unit and collecting generated photogenerated carriers; the charge carrier control region or the photogenerated charge carrier collecting region and the reading region are connected with an electric signal, and the reading region is used for outputting charge carriers acted by the photogenerated charge carriers and the electric signal; the coupling region connects the collection region and the readout region.
2. The matrix vector multiplier based on photoelectric calculation array of claim 1, wherein in the photoelectric calculation array, the readout regions of each column of calculation units are connected in sequence, and the carrier control regions of each row of calculation units are connected in sequence.
3. The method according to claim 1, wherein the specific process comprises:
(1) arranging m × n photoelectric computing units into a unit array with the same number of rows and columns as that of the matrix to be multiplied, wherein each computing unit comprises a carrier control area, a coupling area, a photo-generated carrier collecting area and a reading area; in the unit array, the photon-generated carrier collecting region of each column of computing units is connected with the output end of the reading region in sequence, and the carrier control regions of each row of computing units are connected in sequence;
(2) the light-emitting unit emits light signals which are set as data in a matrix to be multiplied, and the light signals are incident to the input ends of a photo-generated carrier collecting region and a reading region of the corresponding calculating unit and are used as matrix data input ends of a matrix vector multiplier; the carrier control region input of each row of computing units is the carrier set to represent each element in the vector, and is the vector data input end of the matrix vector multiplier; after the data of each element in the vector is converted into binary, serially inputting carriers representing the binary data into carrier control areas of each row according to bits;
(3) the output ends of the photogenerated carrier collecting region and the reading region of the computing unit output carriers which are subjected to the common action of matrix data and vector data and output the carriers in a current mode under the drive of fixed voltage, all current values of each column of the computing unit are converged to obtain an analog addition result, the analog addition results of a plurality of columns are input into an analog-to-digital converter together, analog-to-digital conversion is carried out on the analog addition result of each column through a control address, then shift operation is carried out according to input bits, and then accumulation is carried out to obtain a result vector.
4. The method according to claim 1, wherein the specific process comprises:
(1) arranging m × n photoelectric computing units into a unit array with the same number of rows and columns as that of the matrix to be multiplied, wherein each computing unit comprises a carrier control area, a coupling area, a photo-generated carrier collecting area and a reading area; in the unit array, the photon-generated carrier collecting region of each column of computing units is connected with the output end of the reading region in sequence, and the carrier control regions of each row of computing units are connected in sequence;
(2) the light-emitting unit emits light signals which are set as data in a matrix to be multiplied, and the light signals are incident to the input ends of a photo-generated carrier collecting region and a reading region of the corresponding calculating unit and are used as matrix data input ends of a matrix vector multiplier; the carrier control region input of each row of computing units is the carrier set to represent each element in the vector, and is the vector data input end of the matrix vector multiplier; dividing the unit array into a plurality of block units, expanding according to bit positions and parallelly inputting carriers representing binarized data to each row of carrier control areas of each block unit in a time-sharing manner after data of each element in the vector is converted into binary; when vector data are input into a certain block unit, zero padding is carried out on other data in the vector to enable the length of the vector to be consistent with the length of an original vector;
(3) the output ends of the photo-generated carrier collecting region and the reading region of the calculating unit output carriers under the common action of matrix data and vector data and output the carriers in a current mode under the drive of fixed voltage, the current values of all the block units form intermediate results after analog-to-digital conversion, and the intermediate results are integrated into a final calculating result according to the division mode of the unit array.
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