CN110263296A - A kind of matrix-vector multiplier and its operation method based on photoelectricity computing array - Google Patents
A kind of matrix-vector multiplier and its operation method based on photoelectricity computing array Download PDFInfo
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Abstract
The invention discloses a kind of matrix-vector multiplier and its operation method based on photoelectricity computing array.Multiplier includes photoelectricity computing array and analog-digital converter, and photoelectricity computing array is made of m*n photoelectricity computing unit periodic arrangement；Each photoelectricity computing unit includes luminescence unit and computing unit, and each computing unit includes light input end and result output end, and the light that luminescence unit issues is incident on the light input end of corresponding computing unit；The result output end of each column count unit is sequentially connected, and the current signal of each column count unit output is separately input to an analog-digital converter or the current signal of multiple row computing unit output is input to an analog-digital converter jointly.Method of the invention can save a large amount of power consumptions and area, and greatly improve the precision of calculated result.
Description
Technical field
The present invention relates to a kind of matrix-vector multiplier and its operation method based on photoelectricity computing array belongs to calculating neck
Domain and photodetection field.
Background technique
Traditional computer takes von Neumann framework mostly, however, because von Neumann framework storage unit and operation
Unit it is discrete, result in and produce great energy consumption in data transmission, and influence arithmetic speed.Photoelectricity calculates single
Member can combine to carry out the calculating device of operation, feature for one kind with operation independent or with current electronic computation technology
Are as follows: single device can be realized that " depositing-calculate a body function ", integrated level is good, Energy Efficiency Ratio is high, compatible strong, therefore be very suitable to accelerate
Using neural network algorithm, CT algorithm as a series of algorithm of a large amount of operation matrix vector multiplication of needs of representative.If by photoelectricity
Computing unit group is combined into large-scale photoelectricity computing array, and the operation acceleration function of various complexity may be implemented.
For large-scale matrix-vector operation, in existing photoelectricity computing array, the read-out area of each column count unit
Require a corresponding analog-to-digital conversion device.After matrix size reaches a certain level, the number of analog-digital converter can be sharply
Increase, brings the reduction of power consumption increased with efficiency.And after the quantity of analog-digital converter is excessive, single Embedded is difficult
Degree rises, and the cost and risk of flow can greatly increase.Meanwhile relatively high application scenarios are required for computational accuracy, it is based on
The matrix-vector multiplier of photoelectricity computing unit can bring biggish arithmetic eror.A common method for reducing error is to use
The analog-digital converter of high bit number, but with the raising of conversion digit and conversion accuracy, the area and function of analog-digital converter
The double rising of consumption meeting, and the conversion digit of current digital analog converter on the market is not generally at 16 hereinafter, be able to satisfy photoelectricity
The calculating demand of computing unit.
Summary of the invention
In order to overcome the above defect existing in the prior art, the present invention provides a kind of matrix based on photoelectricity computing array
Vector multiplier and its operation method.
The technical solution adopted by the invention is as follows:
A kind of matrix-vector multiplier based on photoelectricity computing array, including photoelectricity computing array and analog-digital converter, light
Electric computing array is made of m*n photoelectricity computing unit periodic arrangement, and wherein m is line number, and n is columns；Each photoelectricity calculates
Unit includes luminescence unit and computing unit, and each computing unit includes light input end and result output end, and luminescence unit issues
Light be incident on the light input end of corresponding computing unit；The result output end of each column count unit is sequentially connected, multiple row meter
The current signal for calculating unit output is input to an analog-digital converter jointly.Or the result output end of each column count unit according to
Secondary to be connected, the current signal of each column count unit output is separately input to an analog-digital converter.
Further, the computing unit includes carrier control zone, coupled zone and photo-generated carrier collecting region and reading
Area out；The carrier control zone is for controlling and modulating the carrier in photoproduction carrier collection area and read-out area；The light
Collecting region in raw carrier collection area and read-out area is used to absorb the photon of luminescence unit transmitting and collects the photoproduction load of generation
Stream；Read-out area in the carrier control zone or photo-generated carrier collecting region and read-out area is connect with electric signal, is read
Area is used to export by the carrier after the photo-generated carrier and electric signal effect；The coupled zone connection collecting region and reading
Area out.
Further, in photoelectricity computing array, the read-out area of each column count unit is sequentially connected, and every a line calculates single
The carrier control zone of member is sequentially connected.
The operation method of the matrix-vector multiplier of multiplexing analog to digital converter of the present invention is specific as follows:
(1) m*n photoelectricity computing unit is arranged in cell array identical with row matrix columns to be multiplied, the calculating is single
Member includes carrier control zone, coupled zone and photo-generated carrier collecting region and read-out area；In cell array, each column count
The photo-generated carrier collecting region of unit and the output end of read-out area are sequentially connected, the carrier control zone of every a line computing unit
It is sequentially connected；
(2) luminescence unit issues the optical signal being arranged to wait multiply data in matrix, and is incident on corresponding calculating
The photo-generated carrier collecting region of unit and the input terminal of read-out area are the matrix data input terminal of matrix-vector multiplier；It is each
The carrier control zone input of row computing unit is arranged to the carrier of each element in representation vector, is matrix-vector multiplication
The vector data input terminal of device；Wherein, after the data of each element are converted into binary system in the vector, according to bit bit string
The carrier for representing data after binaryzation is input in the carrier control zone of each row by row ground；
(3) the photo-generated carrier collecting region of computing unit and the output of the output end of read-out area are by matrix data and vector data
Carrier after collective effect, and exported in the form of electric current under the driving of fixed voltage, each column count unit owns
Current value converge to obtain analog addition as a result, multiple row simulation addition results be input to jointly in an analog-digital converter again, pass through
It controls address and analog-to-digital conversion is carried out to the analog addition result of each column, then carry out shifting function by the bit of input and tire out again
Add, obtains result vector.
Another piecemeal input operation method of matrix-vector multiplier of the present invention is specific as follows:
(1) m*n photoelectricity computing unit is arranged in cell array identical with row matrix columns to be multiplied, the calculating is single
Member includes carrier control zone, coupled zone and photo-generated carrier collecting region and read-out area；In cell array, each column count
The photo-generated carrier collecting region of unit and the output end of read-out area are sequentially connected, the carrier control zone of every a line computing unit
It is sequentially connected；
(2) luminescence unit issues the optical signal being arranged to wait multiply data in matrix, and is incident on corresponding calculating
The photo-generated carrier collecting region of unit and the input terminal of read-out area are the matrix data input terminal of matrix-vector multiplier；It is each
The carrier control zone input of row computing unit is arranged to the carrier of each element in representation vector, is matrix-vector multiplication
The vector data input terminal of device；Cell array is divided into multiple blocking units, the data of each element are turned in the vector
After turning to binary system, it is unfolded according to bit and the carrier timesharing for representing data after binaryzation is concurrently input to each point
Each row carrier control zone of module unit；When a certain blocking unit input vector data, in vector other data paddings make to
The length of amount is consistent with former vector length；
(3) the photo-generated carrier collecting region of computing unit and the output of the output end of read-out area are by matrix data and vector data
Carrier after collective effect, and exported in the form of electric current under the driving of fixed voltage, the current value of each blocking unit is logical
Intermediate result is formed after crossing analog-to-digital conversion, the intermediate result is integrated into final calculate according still further to the zoned format of cell array and ties
Fruit.
The present invention is based on photoelectricity computing arrays to propose two kinds of improved matrix-vector multipliers and its operation method, respectively
It has the advantage that
(1) method is multiplexed using analog-to-digital conversion, under the basis for completing original calculating task, at least half of modulus can be saved
The resource of converter reduces the cost and risk of flow while saving power consumption and area.
(2) piecemeal calculating method is motivated by Time-sharing control and is inputted, and improves the precision of results of intermediate calculations, to improve most
The computational accuracy of termination fruit.
Detailed description of the invention
Fig. 1 is the multi-functional-area block diagram of computing unit.
Fig. 2 is the structural schematic diagram of photoelectricity computing array.
Fig. 3 is 1 computing unit structure (a) sectional view of embodiment and (b) perspective view.
Fig. 4 is 2 computing unit structure (a) sectional view of embodiment and (b) perspective view.
Fig. 5 is 3 computing unit (a) structural schematic diagram of embodiment and the multi-functional-area (b) schematic diagram.
Fig. 6 is that AD is multiplexed serial matrix-vector multiplier.
Fig. 7 is that the high-precision matrix-vector multiplier of piecemeal input calculates schematic diagram.
Fig. 8 is the method for partition schematic diagram of the high-precision matrix-vector multiplier of piecemeal input.
In figure: 1- light emitting array, 2- computing array.
Specific embodiment
Computing unit in photoelectricity computing unit of the present invention is the multi-functional-area structure for including three zones area, such as Fig. 1 institute
Show, three zones area are as follows: carrier control zone, coupled zone, photo-generated carrier collecting region and read-out area, concrete function is respectively such as
Under:
Carrier control zone: it is responsible for controlling and modulates the carrier in photoelectricity computing unit, and as computing unit
Electrical input mouth inputs one of operand as electric input quantity；Or the carrier in computing unit is only controlled and modulates,
Electric input quantity is inputted by other regions.
Coupled zone: being responsible for connection photo-generated carrier collecting region and read-out area, so that the photo-generated carrier that photon incidence generates
The carrier in photoelectricity computing unit is acted on, operation relation is formed.
Photo-generated carrier collecting region and read-out area: wherein collecting region is responsible for absorbing incident photon and collects the photoproduction of generation
Carrier, and the light input port as computing unit input one of operand as light input quantity；Read-out area can be with
As the electrical input mouth of computing unit, one of operand is inputted as electric input quantity, and as the defeated of computing unit
Exit port, output is by the carrier after light input quantity and electric input quantity effect as unit output quantity；Or pass through other regions
Electric input quantity is inputted, read-out area is only used as the output port of computing unit, and output is by after light input quantity and electric input quantity effect
Carrier, as unit output quantity.
The light that luminescence unit issues is collected as incident computing unit photo-generated carrier and the photon of read-out area, participates in fortune
It calculates.Photoelectricity computing array includes light emitting array 1 and computing array 2, and structure is as shown in Figure 2.Light emitting array 1 is by multiple luminescence units
Periodic arrangement composition, computing array 2 are made of multiple computing unit periodic arrangements.
Embodiment 1
As shown in figure 3, the computing unit of the present embodiment includes: as the control grid of carrier control zone, as coupling
The Charged Couple floor in area, and as the P type substrate of photo-generated carrier collecting region and read-out area, left side is divided into P type substrate and is received
Ji Qu and right side read-out area, wherein including shallow-trench isolation in the read-out area of right side, by the N-type source and N-type of ion implanting formation
Drain terminal.Shallow-trench isolation is located at the centre at semiconductor substrate middle part, collecting region and read-out area, and shallow-trench isolation is by etching and being packed into
Silica is formed, with the electric signal for collecting region and read-out area to be isolated.N-type source is located in read-out area and is situated between by near-bottom
The side of matter layer is adulterated by ion implantation and is formed.N-type drain terminal is located in semiconductor substrate close to underlying dielectric layer and N
The opposite other side of type source is equally doped method by ion implantation and is formed.It should be understood that left side mentioned in this article,
Right side, top and lower section, which are only represented, is changing change with observation visual angle by the relative position under view as shown in the figure
Change, and is not understood to the limitation to specific structure.
Apply the pulse that a voltage range is negative pressure on the substrate of collecting region, or applies a voltage on the control gate
Range is the pulse of positive pressure, so that generating the depletion layer collected for photoelectron in collecting region substrate, and passes through right side read-out area
Read the photoelectron quantity collected, the input quantity as light input end.When reading, applies a positive voltage on the control gate, make N
Conducting channel is formed between type source and collecting region N-type drain terminal, then by applying a biasing arteries and veins between N-type source and N-type drain terminal
Voltage is rushed, so that the electronics in conducting channel accelerates to be formed the electric current between source and drain.The load of electric current is formed between source and drain in channel
Stream is controlled the photoelectron quantity collective effect that gate voltage, source-drain voltage and collecting region are collected, as by light input quantity
Electronics with after electric input quantity collective effect, is exported in the form of electric current, and wherein control-grid voltage, source-drain voltage can be with
As the electric input quantity of device, photoelectron quantity is then the light input quantity of device.
The Charged Couple layer of coupled zone makes depletion region in collecting region substrate start to collect for connecting collecting region and read-out area
After photoelectron, the photoelectron quantity that collecting region substrate surface gesture just will receive collection influences；By the connection of Charged Couple layer,
So that read-out area semiconductor substrate surface gesture is influenced by collecting region semiconductor substrate surface gesture, and then between influence read-out area source and drain
Size of current, to read the photoelectron quantity of collecting region collection by judging electric current between read-out area source and drain；
The control gate of carrier control zone, to apply a pulse voltage on it, so that being read in P-type semiconductor substrate
It generates in area for exciting photoelectronic depletion region out, while can also be used as electrical input, input a wherein bit arithmetic amount.
In addition, there is the underlying dielectric layer for isolation between P-type semiconductor substrate and Charged Couple layer；Charged Couple layer
Also there is the top layer dielectric layer for isolation between control gate.
Embodiment 2
As shown in figure 4, the computing unit of the present embodiment includes: as the control grid of carrier control zone, as coupling
The Charged Couple floor in area, and as the P-type semiconductor substrate of photo-generated carrier collecting region and read-out area, wherein in P type substrate
Include the N-type source formed by ion implanting and drain terminal.P-type semiconductor substrate can undertake work that is photosensitive and reading simultaneously
Make.N-type source is located at the side in read-out area close to underlying dielectric layer, is adulterated and is formed by ion implantation.N-type drain terminal position
It is same to be carried out by ion implantation close to the underlying dielectric layer other side opposite with the N-type source in semiconductor substrate
Doping method is formed.
When photosensitive, apply the pulse that a voltage range is negative pressure on P-type semiconductor substrate, while as carrier
Apply the pulse that a voltage range is positive pressure on the control grid of control zone, is received so that being generated in P type substrate for photoelectron
The depletion layer of collection is generated and is accelerated under the electric field action in the electronics in depletion region between control grid and P type substrate both ends,
And sufficiently high energy is obtained reaching, the underlying dielectric layer potential barrier across P type substrate and Charged Couple layer, into charge
Coupling layer is simultaneously stored in this, the amount of charge in Charged Couple layer, when will affect threshold value when device is opened, and then influencing to read
Source and drain between size of current；When reading, apply a pulse voltage on the control gate, makes to be formed between N-type source and N-type drain terminal and lead
Electric channel, then by applying a pulse voltage between N-type source and N-type drain terminal, so that the electronics in conducting channel accelerates shape
At the electric current between source and drain.Electric current between source and drain is controlled in gate pulse voltage, source-drain voltage and Charged Couple layer and deposits
The electron amount collective effect of storage, as by the electronics after light input quantity and electric input quantity collective effect, in the form of electric current into
Row output, wherein control-grid voltage, source-drain voltage can be used as the electric input quantity of device, the photoelectricity stored in Charged Couple layer
Subnumber amount is then the light input quantity of device.
The Charged Couple layer of coupled zone enters photoelectron therein for storing, and device threshold size when changing reading,
And then electric current between read-out area source and drain is influenced, thus by judge between read-out area source and drain electric current come generation when reading photosensitive and entering
Photoelectron quantity in Charged Couple layer.
The control gate of carrier control zone, to apply a pulse voltage on it, so that being read in P-type semiconductor substrate
It generates in area for exciting photoelectronic depletion region out, while can also be used as electrical input, input a wherein bit arithmetic amount.
In addition, there are one layer of underlying dielectric layers for isolation between P-type semiconductor substrate and Charged Couple layer；Charge coupling
It closes and also there is one layer of top layer dielectric layer for isolation between layer and control gate.
Embodiment 3
As shown in figure 5, the computing unit of the present embodiment includes: two pole of photoelectricity collected as photo-generated carrier with read-out area
Pipe and readout tube, wherein photodiode is formed by ion doping, is responsible for photosensitive.The area N of photodiode passes through as coupling
The photoelectron coupling lead for closing area is connected on the control gate of readout tube and the source of reset transistor, and the drain terminal of readout tube is applying one just
Voltage pulse, the driving voltage as read current；Before exposure, reset transistor is opened, and reset transistor drain terminal voltage is applied to photoelectricity two
In pole pipe, the photodiode as collecting region is made to be in reverse-biased, generates depletion layer；When exposure, reset transistor shutdown, photoelectricity
Diode is electrically isolating, and photoelectron is generated behind photon incidence photodiode depletion region, and accumulate in the diode, two poles
The area N of pipe with electrically by as coupled zone photoelectron couple lead connect with the area N readout tube control gate potential opening
Begin decline, and then the electron concentration in influence readout tube channel.Readout tube is responsible for reading, and drain terminal applies a positive pulse voltage,
Source is connected with addressing pipe drain terminal, when reading, is opened addressing pipe, is generated circuit current in readout tube, size of current is resetted
Pipe drain terminal voltage, readout tube drain terminal voltage and incident light subnumber joint effect, the electronics in readout tube channel, input as by light
Electronics after amount and electric input quantity collective effect, exports in the form of electric current, wherein reset transistor drain terminal voltage, readout tube drain terminal electricity
Pressure can be used as the electric input quantity of device, and electric incident light subnumber is then the light input quantity of device.
The photoelectron coupling lead of coupled zone is used to be connected to the light of collecting region in photo-generated carrier collection and read-out area
Electric diode and readout tube as read-out area, the area photodiode N potential is applied on readout tube control gate.
As the reset transistor of carrier control zone, a positive voltage is inputted by its drain terminal and acts on photodiode, when
When reset transistor is opened, positive voltage can be acted on the photodiode, and photodiode is made to generate depletion region and photosensitive, while
It can be used as electrical input, input a wherein bit arithmetic amount.
In addition, addressing pipe is used to control output of the entire arithmetic unit as the output electric current of output quantity, it can be in photoelectricity
Ranks addressing uses when computing unit forms array.
Embodiment 4
The present embodiment is multiplexed serial matrix-vector multiplication using multiple luminescence units and the computing unit of embodiment 1 composition AD
Device, Lai Shixian dimension meet the multiplying of a matrix and a vector of matrix-vector multiplication rule.
For calculating the multiplying A*W of vector A and matrix W, wherein A is 1*8 vector, each data bit width in vector
For 8bit.W is 8*8 matrix, such as formula (1), calculates schematic diagram as shown in fig. 6, the box unit for indicating V character in figure is represented and adopted
Photoelectricity computing unit, wherein the element in vector A is inputted by electrical input, and the element in matrix W passes through light input end
Input.
Firstly, each element carries out binary system conversion in the controls by A:
Computing unit is arranged in array according to form as shown in FIG. 6, wherein the line number of array is 8, columns 8, and
And the control grid as carrier control zone of the computing unit of all same a line of array is all connected, input same electricity
Input data；By the computing unit of all same rows of array as the defeated of the P type substrate of carrier collection area and read-out area
Outlet is all connected, so that the current remittance rephasing of output adds.
When input, 8*8 data in matrix are sequentially inputted in 8*8 computing unit by light input end；It will be to
Element in amount is from serial input, the two-value data timesharing of identity element difference bit on the connected control grid of colleague's unit
It sequentially inputs, when what is inputted on control gate is the data of lowest bit position, element is minimum in the element and vector in matrix
The two-value data of bit carries out the multiplication of corresponding position, that is, is equal to and has carried out operation (1):
Before electric current convergence, the computing unit array of 8*8, the calculated result of each unit is respectively as follows:
The all connected output current circuit of output end again through each column, that is, be equal to and carried out by column sum operation, as a result
(4) after convergence is added, the matrix-vector multiplication output end of bottom is exported are as follows:
This result is the operation result of formula (4), completes the matrix-vector multiplication fortune of vector lowest bit position and matrix
It calculates.There are 8 intermediate results of weak current converged to need to carry out modulus AD conversion at this time, as shown in fig. 6,8 column current multiplexings are more than one
Input selection converter (is also possible to every 2,3,4 ... 7 column and shares a converter), and addr_sel is address choosing in figure
Signal is selected, 8 results of intermediate calculations are AD converted respectively by control system addressing, obtain digital quantity.
By the result input control system after AD conversion, because it is lowest bit position so moving to left 0, then by vector
Secondary low bit position obtains the matrix-vector multiplication of vector time higher bit position and matrix as electrical input data input control grid
As a result, moving to left 1 after input control system, and vector is carried out with foregoing description vector lowest bit position and matrix multiplication result and is added
Method, and so on, all bit two-value datas of the complete vector of serial input, after successively shifting in the controls and be cumulative,
Intermediate matrix-vector operation result is obtained, is equal to and has carried out following operation:
Final matrix-vector multiplication calculated result is obtained.
Control system can use digital circuit, can also be using a variety of logic control lists such as computer, single-chip microcontroller, FPGA
Member.
Embodiment 5
The present embodiment using the computing unit group component block input of multiple luminescence units and embodiment 1 high-precision matrix to
Multiplier is measured, Lai Shixian dimension meets the multiplying of a matrix and a vector of matrix-vector multiplication rule.
Computing unit is arranged in array according to form as shown in Figure 7, difference essentially identical with the structure of embodiment 4
It is that each column count unit uses a converter respectively.Certainly, the piecemeal input method of the present embodiment uses the knot of Fig. 6
Structure also may be implemented.
For calculating the multiplying A*W of vector A and matrix W, wherein A is 1*8 vector, each data bit width in vector
For 8bit.When input, 8*8 data in matrix are sequentially inputted in 8*8 computing unit by light input end；It will be to
Element in amount is from serial input, the two-value data timesharing of identity element difference bit on the connected control grid of colleague's unit
It sequentially inputs, when what is inputted on control gate is the data of lowest bit position, element is minimum in the element and vector in matrix
The two-value data of bit carries out the multiplication of corresponding position, that is, is equal to the operation for having carried out formula (1).
Before electric current convergence, the computing unit array of 8*8, the calculated result of each unit is respectively formula (4), then through every
The all connected output current circuit of the output end of one column, that is, be equal to and carried out by column sum operation, as a result (4) are added through convergence
Afterwards, bottom matrix-vector multiplication output end output be formula (5), this result is the operation result of formula (4), complete to
Measure the matrix-vector multiplication operation of lowest bit position and matrix.Turn if each column current remittance cluster value obtained at this time directly carries out AD
It changes, because element bit wide each in W matrix is 6bit, it is 9bit that the element of 8 6bit of each column, which is added final result, uses 8bit
Converter will lose certain precision when being converted.So input vector motivates [A in formula (3)11A21…A81]
When, using piecemeal input method, the operation of formula (3) is split as shown in formula (7) and (8):
8 numbers are cumulative at this time is split as the operation that 4 numbers are cumulative twice, and 4 6bit numbers are accumulated as 8bit, pass through 8bit's
Precision can not be lost after converter conversion.
The result piecemeal operation of each bit, then complete to add up, the final calculation result of the bit is obtained, such as Fig. 8 institute
Show.Wherein T0 and T1 indicates two parts in timesharing input stimulus vector.
By the result input control system after AD conversion, because it is lowest bit position so moving to left 0, then by vector
Secondary low bit position obtains the matrix-vector multiplication of vector time higher bit position and matrix as electrical input data input control grid
As a result, moving to left 1 after input control system, and vector is carried out with foregoing description vector lowest bit position and matrix multiplication result and is added
Method, and so on, the piecemeal calculated result of all bit two-value datas of the complete vector of serial input, final each bit mutually adds
Cheng Hou, after successively shifting in the controls and be cumulative to get to intermediate matrix-vector operation result, be equal to carried out as
Lower operation:
Final matrix-vector multiplication calculated result is obtained.
Control system can use digital circuit, can also be using a variety of logic control lists such as computer, single-chip microcontroller, FPGA
Member.
Claims (6)
1. a kind of matrix-vector multiplier based on photoelectricity computing array, including photoelectricity computing array and analog-digital converter, special
Sign is that photoelectricity computing array is made of m*n photoelectricity computing unit periodic arrangement, and wherein m is line number, and n is columns；Each
Photoelectricity computing unit includes luminescence unit and computing unit, and each computing unit includes light input end and result output end, is shone
The light that unit issues is incident on the light input end of corresponding computing unit；The result output end of each column count unit successively phase
Even, the current signal of multiple row computing unit output is input to an analog-digital converter jointly.
2. a kind of matrix-vector multiplier based on photoelectricity computing array, including photoelectricity computing array and analog-digital converter, special
Sign is that photoelectricity computing array is made of m*n photoelectricity computing unit periodic arrangement, and wherein m is line number, and n is columns；Each
Photoelectricity computing unit includes luminescence unit and computing unit, and each computing unit includes light input end and result output end, is shone
The light that unit issues is incident on the light input end of corresponding computing unit；The result output end of each column count unit successively phase
Even, the current signal of each column count unit output is separately input to an analog-digital converter.
3. a kind of matrix-vector multiplier based on photoelectricity computing array according to claim 1 or 2, which is characterized in that
The computing unit includes carrier control zone, coupled zone and photo-generated carrier collecting region and read-out area；The carrier control
Area processed is for controlling and modulating the carrier in photoproduction carrier collection area and read-out area；The photo-generated carrier collecting region and reading
The collecting region in area is used to absorb the photon of luminescence unit transmitting and collects the photo-generated carrier of generation out；The carrier control
Read-out area in area or photo-generated carrier collecting region and read-out area is connect with electric signal, and read-out area is for exporting by the photoproduction
Carrier after carrier and electric signal effect；The coupled zone connection collecting region and read-out area.
4. a kind of matrix-vector multiplier based on photoelectricity computing array according to claim 3, which is characterized in that in light
In electric computing array, the read-out area of each column count unit is sequentially connected, and the carrier control zone of every a line computing unit is successively
It is connected.
5. a kind of operation method of the matrix-vector multiplier based on photoelectricity computing array as described in claim 1, feature exist
In detailed process is as follows:
(1) m*n photoelectricity computing unit is arranged in cell array identical with row matrix columns to be multiplied, the computing unit packet
Include carrier control zone, coupled zone and photo-generated carrier collecting region and read-out area；In cell array, each column count unit
Photo-generated carrier collecting region and the output end of read-out area be sequentially connected, the carrier control zone of every a line computing unit is successively
It is connected；
(2) luminescence unit issues the optical signal being arranged to wait multiply data in matrix, and is incident on corresponding computing unit
Photo-generated carrier collecting region and read-out area input terminal, be matrix-vector multiplier matrix data input terminal；Every a line meter
The carrier control zone input for calculating unit is arranged to the carrier of each element in representation vector, is matrix-vector multiplier
Vector data input terminal；Wherein, after the data of each element are converted into binary system in the vector, serially according to bit
The carrier for representing data after binaryzation is input in the carrier control zone of each row；
(3) the photo-generated carrier collecting region of computing unit and the output of the output end of read-out area are common by matrix data and vector data
Carrier after effect, and exported in the form of electric current under the driving of fixed voltage, all electric currents of each column count unit
Value convergence obtain analog addition as a result, multiple row simulation addition results be input to jointly in an analog-digital converter again, pass through control
Address carries out analog-to-digital conversion to the analog addition result of each column, then carries out shifting function by the bit of input and adds up again, obtains
To result vector.
6. a kind of operation method of the matrix-vector multiplier based on photoelectricity computing array as claimed in claim 1 or 2, feature
It is, detailed process is as follows:
(1) m*n photoelectricity computing unit is arranged in cell array identical with row matrix columns to be multiplied, the computing unit packet
Include carrier control zone, coupled zone and photo-generated carrier collecting region and read-out area；In cell array, each column count unit
Photo-generated carrier collecting region and the output end of read-out area be sequentially connected, the carrier control zone of every a line computing unit is successively
It is connected；
(2) luminescence unit issues the optical signal being arranged to wait multiply data in matrix, and is incident on corresponding computing unit
Photo-generated carrier collecting region and read-out area input terminal, be matrix-vector multiplier matrix data input terminal；Every a line meter
The carrier control zone input for calculating unit is arranged to the carrier of each element in representation vector, is matrix-vector multiplier
Vector data input terminal；Cell array is divided into multiple blocking units, the data of each element are converted into the vector
After binary system, it is unfolded according to bit and the carrier timesharing for representing data after binaryzation is concurrently input to each piecemeal list
Each row carrier control zone of member；When a certain blocking unit input vector data, other data paddings make vector in vector
Length is consistent with former vector length；
(3) the photo-generated carrier collecting region of computing unit and the output of the output end of read-out area are common by matrix data and vector data
Carrier after effect, and exported in the form of electric current under the driving of fixed voltage, the current value of each blocking unit passes through mould
Intermediate result is formed after number conversion, the intermediate result is integrated into final calculation result according still further to the zoned format of cell array.
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