CN110275569B - Control method for working state of photoelectric calculation unit - Google Patents

Control method for working state of photoelectric calculation unit Download PDF

Info

Publication number
CN110275569B
CN110275569B CN201910442809.2A CN201910442809A CN110275569B CN 110275569 B CN110275569 B CN 110275569B CN 201910442809 A CN201910442809 A CN 201910442809A CN 110275569 B CN110275569 B CN 110275569B
Authority
CN
China
Prior art keywords
light input
input
stage
light
photoelectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910442809.2A
Other languages
Chinese (zh)
Other versions
CN110275569A (en
Inventor
王瑶
李张南
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanjing Jixiang Sensing Imaging Technology Research Institute Co ltd
Original Assignee
Nanjing Weixin Photoelectric System Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanjing Weixin Photoelectric System Co ltd filed Critical Nanjing Weixin Photoelectric System Co ltd
Priority to CN201910442809.2A priority Critical patent/CN110275569B/en
Publication of CN110275569A publication Critical patent/CN110275569A/en
Application granted granted Critical
Publication of CN110275569B publication Critical patent/CN110275569B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06EOPTICAL COMPUTING DEVICES; COMPUTING DEVICES USING OTHER RADIATIONS WITH SIMILAR PROPERTIES
    • G06E3/00Devices not provided for in group G06E1/00, e.g. for processing analogue or hybrid data
    • G06E3/001Analogue devices in which mathematical operations are carried out with the aid of optical or electro-optical elements
    • G06E3/005Analogue devices in which mathematical operations are carried out with the aid of optical or electro-optical elements using electro-optical or opto-electronic means
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/04Architecture, e.g. interconnection topology
    • G06N3/045Combinations of networks
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Molecular Biology (AREA)
  • General Health & Medical Sciences (AREA)
  • Evolutionary Computation (AREA)
  • Data Mining & Analysis (AREA)
  • Computational Linguistics (AREA)
  • Software Systems (AREA)
  • Artificial Intelligence (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Neurology (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Optics & Photonics (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Light Receiving Elements (AREA)

Abstract

The invention discloses a control method for the working state of a photoelectric computing unit. The photoelectric calculation unit comprises a light-emitting unit and a calculation unit, wherein the calculation unit comprises three parts: a P-type semiconductor substrate as a photogenerated carrier collection and readout region, a charge-coupled layer as a coupling region, and a control gate as a carrier control region; the control method specifically comprises the following steps: by applying different electrical conditions to the control gate, the P-type semiconductor substrate, the N-type source electrode and the N-type drain electrode, the electrical state in the computing unit is changed, so that the computing unit is in different working phases, wherein the working phases comprise: a light input stage that receives photons and generates photogenerated carriers; an electric input stage for receiving electrons and generating an operational relationship between the electrons and the photo-generated carriers; a readout phase in which the output is co-acted by the photogenerated carriers and the electrical input electrons; and a light input reset phase for erasing the light input data. The invention can realize high-precision optical input and greatly improve the accuracy of device calculation.

Description

Control method for working state of photoelectric calculation unit
Technical Field
The invention relates to a control method of the working state of a photoelectric computing unit, belonging to the fields of optics and semiconductor devices.
Background
The photoelectric computing unit is a computing device which can be operated independently or combined with the current electronic computing technology, and is characterized in that: the memory-calculation integrated function can be realized by a single device, the integration level is good, the energy efficiency ratio is high, and the compatibility is strong.
When the photoelectric calculation units are combined into a large photoelectric calculation array, the photoelectric calculation unit can be used for realizing various complex operation acceleration functions, such as convolution operation in a convolution neural network algorithm. If the photoelectric computing array is used as a convolution arithmetic unit, the characteristic that convolution kernel data is unchanged in multiple convolution operations can be well exerted, and the high-performance convolution operation can be realized by utilizing the characteristic that optical input data of the photoelectric computing unit is stored. But this problem becomes particularly critical how to control and make accurate light input to each cell in a large-scale convolutional operator array through limited wiring.
Disclosure of Invention
The invention aims to provide a control method for the working state of a photoelectric computing unit.
The technical scheme adopted by the invention is as follows:
the control method of the working state of the photoelectric computing unit comprises a light emitting unit and a computing unit, wherein light emitted by the light emitting unit is incident into the computing unit, and the computing unit comprises three parts: a P-type semiconductor substrate as a photogenerated carrier collection and readout region; a charge coupled layer as a coupling region; a control gate as a carrier control region; the P-type semiconductor substrate is divided into a collecting area and a reading area, wherein shallow trench isolation, an N-type source end and an N-type drain end are arranged in the reading area, and the shallow trench isolation is positioned between the collecting area and the reading area;
the control method specifically comprises the following steps: by applying different electrical conditions to the control gate, the P-type semiconductor substrate, the N-type source electrode and the N-type drain electrode, the electrical state in the computing unit is changed, so that the computing unit is in different working stages, wherein the working stages comprise: a light input stage that receives photons and generates photogenerated carriers; an electric input stage for receiving electrons and generating an operational relationship between the electrons and the photo-generated carriers; a readout phase in which the output is co-acted by the photogenerated carriers and the electrical input electrons; and a light input reset phase for erasing the light input data.
Further, the control method of the light input stage specifically includes: applying positive pressure on the control grid electrode, applying negative pressure on the P-type semiconductor substrate, and floating the N-type drain end and the N-type source end at the same time, so that a depletion layer capable of absorbing incident photons is generated at the bottom of the P-type semiconductor substrate, the condition of light input is achieved, and a computing unit enters a light input stage; the calculation unit is separated from the light input stage by removing or reducing the positive pressure on the control grid or removing or lifting the negative pressure on the P-type semiconductor substrate;
the control method of the light input reset stage specifically comprises the following steps: by applying a negative voltage on the control gate and a positive or zero bias on the P-type semiconductor substrate; or negative pressure or zero bias voltage is applied to the control grid electrode, positive pressure is applied to the P-type semiconductor substrate, so that photo-generated carriers collected by the collecting area are pumped out of the P-type semiconductor substrate and are combined with holes in the P-type semiconductor substrate, and the computing unit enters a light input reset stage and completes reset of light input quantity;
the control method of the electric input stage specifically comprises the following steps: inputting an electrical input into the control gate in the form of a carrier by applying a positive bias on the control gate representing the magnitude of the electrical input; or by applying a bias voltage representing the magnitude of the electric input quantity between the N-type drain electrode and the N-type source electrode of the P-type semiconductor substrate, the electric input quantity is input into a photo-generated carrier collecting and reading area of the calculating unit in the form of carriers, and the calculating unit enters an electric input stage and inputs the electric input quantity;
the control method of the reading stage comprises the following steps: when the carrier representing the electric input quantity is input into the calculating unit through the control grid electrode, a constant bias voltage is applied between the N-type source electrode and the N-type drain electrode of the P-type semiconductor substrate, so that the carrier under the combined action of the optical input quantity and the electric input quantity in the channel of the reading area is output in the form of current, and the calculating unit enters a reading stage and finishes reading work; or when the carrier representing the electric input quantity is input into the photoelectric calculation unit through the N-type source electrode and the N-type drain electrode, a constant bias voltage is applied to the control grid electrode, so that a channel is generated on the surface of the reading area, the carrier in the channel is output in the form of current after the combined action of the optical input quantity and the electric input quantity, and the calculation unit enters a reading stage and completes reading work.
Further, the photoelectric calculation units are arranged into an array with the size of a convolution kernel in convolution operation, and the output ends of the photo-generated carrier collection and readout areas of all calculation units in the array are connected with each other and are summarized into one output end; the control method specifically comprises the following steps: the light-emitting unit adopts a single uniform-field light source light input method, and realizes independent accurate light input by controlling the time length of each calculation unit in a light input stage; all the calculation units enter the light input stage according to different time lengths of the light input stage, but end the light input stage at the same time; applying constant electric input quantity to all photoelectric calculation units in the array, and controlling a single photoelectric calculation unit with light input to enter a reading stage, while other photoelectric calculation units do not enter the reading stage; judging the accuracy of the value of the current unit light input quantity through the read-out result; recording the deviation after the deviation of the read result, and then reading the result of the next calculation unit and recording the deviation until the light input quantity verification of all calculation units is completed; and resetting and re-inputting the light input quantity of all the calculation units, correcting the light input stage duration of the calculation units with deviation of the light input quantity, and finally enabling all the calculation units to obtain the ideal light input quantity.
The invention can accurately lead each photoelectric calculation unit to enter an optical input stage, an electrical input stage, a reading stage or an optical input reset stage by means of the electrical conditions applied to different functional areas of the photoelectric calculation unit. When a plurality of photoelectric calculation units form an array to carry out convolution operation, the working state of each photoelectric calculation unit is controlled, so that high-precision light input of the array can be realized, and the accuracy of device calculation is greatly improved.
Drawings
FIG. 1 is a block diagram of a multi-functional region of a computing unit.
Fig. 2 is a schematic diagram of the structure of the calculation unit in embodiment 1.
Fig. 3 is an electrical model diagram of the calculation unit in embodiment 1.
Fig. 4 is a schematic diagram of the structure of a convolution operator composed of the photoelectric calculation unit in embodiment 2.
Detailed Description
The invention provides a working state control method of a photoelectric calculation unit, a convolution operator composed of the photoelectric calculation unit and a control method.
As shown in fig. 1, the calculation unit in the photoelectric calculation unit is a multi-functional area structure including three functional areas, wherein the three functional areas are: the specific functions of the carrier control region, the coupling region and the photogenerated carrier collecting and reading region are as follows:
carrier control region: the photoelectric calculation unit is responsible for controlling and modulating carriers in the photoelectric calculation unit, and is used as an electric input port of the photoelectric calculation unit, and one of the calculation quantities is input as an electric input quantity; or only control and modulate the carriers in the photoelectric calculation unit, and input the electric input quantity through other areas.
Coupling region: and the collecting area and the reading area in the photo-generated carrier collecting and reading area are connected, so that photo-generated carriers generated by photon incidence act on carriers in the photoelectric calculation unit to form an operation relation.
Photogenerated carrier collection and readout region: the photoelectric calculation unit comprises a collection area and a readout area, wherein the collection area is responsible for absorbing incident photons and collecting generated photon-generated carriers, and is used as a light input port of the photoelectric calculation unit to input one of calculation quantities as a light input quantity; the readout area can be used as an electric input port of the photoelectric calculation unit, inputs one of the operation amounts as an electric input amount, and is used as an output port of the photoelectric calculation unit, and outputs carriers acted by the optical input amount and the electric input amount as a unit output amount; or the electric input quantity is input through other areas, the read-out area is only used as an output port of the photoelectric calculation unit, and carriers acted by the electric input quantity and the optical input quantity are output as unit output quantity.
The single calculation unit and one light-emitting unit are combined into a complete photoelectric calculation unit, and light emitted by the light-emitting unit is used as photons of a photon-generated carrier collection and readout area of the incident photoelectric calculation unit to participate in operation.
Example 1
As shown in fig. 2, the calculation unit of the present embodiment includes: the semiconductor device comprises a control gate as a carrier control region, a charge coupling layer as a coupling region, and a P-type substrate as a photo-generated carrier collecting region and a readout region, wherein the P-type substrate is divided into a left collecting region and a right readout region, and the right readout region comprises a shallow trench isolation, an N-type source end and an N-type drain end which are formed by ion implantation. Shallow trench isolation is located in the middle of the semiconductor substrate, in the middle of the collection region and the readout region, and is formed by etching and filling silicon dioxide for isolating the electrical signals of the collection region and the readout region. The N-type source end is positioned at one side of the readout area close to the bottom dielectric layer and is formed by doping through an ion implantation method. The N-type drain terminal is positioned on the other side of the semiconductor substrate, which is close to the bottom dielectric layer and is opposite to the N-type source terminal, and is formed by an ion implantation method. It should be understood that references herein to left, right, above, and below are merely representative of the relative positions under viewing through the viewing angles shown in the figures as a function of viewing angle, and are not to be construed as limiting the particular structure.
A pulse with a negative voltage range is applied to the substrate of the collection area, or a pulse with a positive voltage range is applied to the control gate, so that a depletion layer for photoelectron collection is generated in the substrate of the collection area, and the quantity of the collected photoelectrons is read out through the right readout area as an input quantity of the light input end. During reading, a positive voltage is applied to the control grid electrode to form a conducting channel between the N-type source end and the N-type drain end of the collecting area, and then a bias pulse voltage is applied between the N-type source end and the N-type drain end to enable electrons in the conducting channel to accelerate to form current between the source and the drain. The current carriers formed in the channels between the source and the drain are subjected to the combined action of the control gate voltage, the voltage between the source and the drain and the quantity of photoelectrons collected by the collecting area, and are taken as electrons subjected to the combined action of the light input quantity and the electric input quantity to be output in a current mode, wherein the control gate voltage and the voltage between the source and the drain can be taken as the electric input quantity of the device, and the quantity of photoelectrons is the light input quantity of the device.
The charge coupling layer of the coupling region is used for connecting the collecting region and the reading region, so that after the depletion region in the substrate of the collecting region begins to collect photoelectrons, the surface potential of the substrate of the collecting region is affected by the quantity of the collected photoelectrons; the surface potential of the semiconductor substrate of the reading area is influenced by the surface potential of the semiconductor substrate of the collecting area through the connection of the charge coupling layer, so that the current between the source and the drain of the reading area is influenced, and the quantity of photoelectrons collected by the collecting area is read through judging the current between the source and the drain of the reading area;
the control grid of the carrier control area is used for applying a pulse voltage to the control grid so as to generate a depletion area for exciting photoelectrons in the read-out area of the P-type semiconductor substrate, and the depletion area can also be used as an electric input end to input one-bit operand.
In addition, a bottom dielectric layer for isolation is arranged between the P-type semiconductor substrate and the charge coupling layer; there is also a top dielectric layer between the charge coupled layer and the control gate for isolation.
The technical idea of controlling a single computing unit to be in various states is as follows: by applying different electrical conditions to the control gate and the P-type substrate and to the N-type source and drain, the electrical state within the computing cell is changed, thereby enabling the device to be in different phases of operation. The working phase comprises four total steps: a light input stage for receiving photons and generating photogenerated carriers; an electric input stage for receiving electrons and generating an operational relationship between the electrons and the photo-generated carriers; the reading stage is used for outputting electrons which are used as a photoelectric operation result reading area and are acted by the photo-generated carriers and the electric input electrons together; in a light input reset phase of erasing light input data. The specific control method of each stage is as follows:
1. the method for controlling the single computing unit to be in the light input stage comprises the following steps: by applying positive pressure on the control grid electrode and negative pressure on the P-type substrate and floating the N-type source electrode and the N-type drain electrode, a depletion layer capable of absorbing incident photons is generated at the bottom of the P-type substrate, the condition of light input is achieved, and the photoelectric calculation unit enters a light input stage. The detailed deduction about the above operation mode is as follows:
as shown in fig. 3, the left collecting region is equivalent to a capacitor of
Figure BDA0002072616830000041
The right readout region is equivalent to a standard floating gate MOS transistor. Due to design, capacitor C 2 Far less than C 1 Therefore, the influence of the read-out area on the photosensitive area is negligible when the device is in operation.
The potential in a MOS-capacitor Si can be obtained by solving the poisson equation:
Figure BDA0002072616830000051
wherein ε SI Is the dielectric constant of silicon, ρ is the bulk charge density of the P-type substrate.
When a negative pulse is applied to the P substrate as a carrier collection and readout region, or a positive pulse is applied to the control gate as a carrier control region, the substrate will be in a depleted state, beginning to collect photons as an optical input signal and produce photoelectrons, ρ=qn for the depleted region A Wherein N is A Is the doping concentration.
Solving the poisson equation can result in:
Figure BDA0002072616830000052
wherein the x direction is the downward direction perpendicular to the bottom dielectric layer, x d For depletion region depth, q is the electron charge amount and V is the potential at depth x. For MOS, P-type substrate surface potential V S I.e. the value of the potential V at x=0 is thus available:
Figure BDA0002072616830000053
the formula is derived to obtain:
Figure BDA0002072616830000054
wherein E is S For the surface electric field strength, let the substrate voltage be set to 0V, so the control gate potential during the photosensitizing process is:
Figure BDA0002072616830000055
wherein V is G To control gate potential, the depletion region depth x is solved d The method comprises the following steps:
Figure BDA0002072616830000056
/>
when there is photon incidence device, in the depletion regionGenerating photoelectrons and collecting in the channel of the collecting region under the action of the gate electric field, controlling the total charge quantity Q on the gate CG =N A +Q, Q is the signal charge (e-/cm) 2 ) Because the signal charge is collected in the collecting region under the action of the electric field between the control gate and the P-type substrate, and because the recombination of the carriers in the semiconductor substrate requires a certain time, and the thermally excited carriers exist in the depletion region, the signal charge is still stored in the operation unit within a long time after light interruption, and the function of memory-calculation integration is realized.
At this time, the liquid crystal display device,
Figure BDA0002072616830000061
wherein V is Q Sum of potentials generated for signal charges:
Figure BDA0002072616830000062
from the above equation, it can be seen that x increases with the amount of signal charge Q d Gradually decrease when the value of Q is such that V Q X when=0 d I.e. 0, at which point the surface potential V s =0, the channel potential no longer changes, at which point the device reaches the full well.
For the right-hand sense region floating gate MOSFET, its channel current I d Can be expressed as:
Figure BDA0002072616830000063
wherein W and L are respectively the gate width and gate length, V DS For the voltage between source and drain, V FG Is a charge coupled layer potential of which the magnitude is controlled by the control gate potential V G And P-type substrate surface potential V s The impact of (2) can be expressed as:
Figure BDA0002072616830000064
when the doping concentration of the P-type substrate is low (such as 2E15 per cubic centimeter), the partial pressure of the depletion region is far greater than the capacitance C 1 And C 3 And therefore equation (6) can be reduced to:
Figure BDA0002072616830000065
carrying out the reaction in the formula (11) and (3) to obtain the surface potential V of the P-type substrate S And control gate potential V G Sum of potentials V generated by signal charges Q Is approximately equal, namely:
V s ≈V Q (12)
and (3) carrying out formulas (12) and (8) into (10) and then carrying out step (9), thus obtaining the compound:
Figure BDA0002072616830000066
by the number X of incident photons photon To represent the magnitude of the signal charge Q:
Q=X photon tη (14)
wherein t is exposure time, X photon The number of photons incident per unit time, eta is the quantum efficiency of the device.
Thus, an expression is obtained that the device can operate as a multiplier:
Figure BDA0002072616830000071
as can be readily seen from equation (15), the readout region source-drain current I as output d At the same time receive X as light input photon V as an electrical input G And V DS By using such an operational relationship, the photoelectric calculation unit can realize various operation functions.
From the above derivation, if it is desired to have the device in the light input state, it is necessary to be in the P-typeDepletion layer is generated in the collecting region of the photogenerated carrier collecting and readout region of the substrate, i.e. in the photosensitive region on the left side of the P-type substrate, except for applying positive voltage V to the re-control gate as described in the derivation G The depletion layer can also be generated by applying negative pressure on the substrate, and according to the principle of relativity of electric potential, because the N-type source electrode and the N-type drain electrode are both floating when the photoelectric computing unit is in the light input state, the electric port only comprises the control grid electrode and the substrate, so that the depletion layer can be generated enough to collect incident photons as the light input quantity as long as the control grid electrode generates enough positive potential difference relative to the substrate. According to equation (11), as long as a positive potential difference between the control gate and the substrate is generated, a depletion layer is generated in the photosensitive region on the left side, and thus the condition for the photoelectric calculation unit to enter the light input stage is:
V G -V B >0
wherein V is B Is a P-type substrate potential.
2. The method for controlling the single computing unit to be in the light input reset stage comprises the following steps: by applying a negative voltage on the control gate and a positive or zero bias on the P-type substrate, or by applying a negative or zero bias on the control gate and a positive voltage on the P-type substrate. According to the above analysis, the left photosensitive region will enter the light input stage after the depletion layer is generated and collect the photo-generated carriers, the photo-generated carriers will be collected to the surface of the left photosensitive region under the action of the electric field and stored therein, the storage amount as "integrated into one storage" is stored therein for a long time relative to the calculation time, so when a voltage drop opposite to the light input stage is applied to the P-type substrate and the control gate, electrons will be pumped away from the P-type substrate under the action of the electric field to complete the reset of the light input amount, and in addition, after the electrical conditions applied to the substrate and the control gate are completely removed, the light input amount will also be self-composited to complete the reset after a long time due to the composite action of the carriers, so the condition of the light input amount reset can be considered as follows:
V G -V B ≤0。
3. the method for controlling the single photoelectric computing unit to be in the electric input stage comprises the following steps: by applying a positive bias voltage representing the magnitude of an electric input quantity on the control gate, the electric input quantity is input into a carrier control region of the photoelectric operation unit in the form of a carrier; or a bias voltage representing the magnitude of the electric input quantity is applied between the N-type drain electrode and the N-type source electrode of the P-type substrate, so that the electric input quantity is input into a carrier collecting and reading area of the photoelectric operation unit in the form of carriers, and the photoelectric operation unit enters an electric input stage and inputs the electric input quantity.
According to equation (15), if a control gate is used as an input port for the electrical input quantity, the relationship between the electrical input quantity and the source-drain current finally output as a result is an addition relationship, and the optical input quantity and the output current are both addition relationships, then the function realized by the photoelectric calculation unit can be regarded as addition operation; or the electrical input amount is input with a binarized value fixed to 0 or 1, the operation performed by the photoelectric calculation unit at this time may also be considered as a multiplication operation of 0×q or 1×q, where Q is the optical input amount. If the N-type source electrode and the N-type drain electrode of the readout region in the carrier collection and readout region are used as input ports for the electric input quantity, the relation between the electric input quantity and the electric current between the source and drain outputted as a result finally is a multiplication relation, and the photoelectric calculation unit performs multiplication operation. Since the voltage of the control gate must be greater than the threshold of the sense-area MOSFET, otherwise the result of the operation will not be sensed by the sense-area current, there is a lower limit to the voltage when the control gate is used as an electrical input.
Since the electric input quantity does not have a "store" function, if it is necessary to have the electric input quantity input into the unit to participate in the operation, it is necessary to have the photoelectric calculation unit in the electric input stage for a long period of time. Thus, the conditions for putting the photo-electric calculation unit in the electric input phase are:
Figure BDA0002072616830000081
and V is G Representing the electrical input, or V DS There is a voltage representing the electrical input. />
4. The method for controlling the single photoelectric calculation unit to be in a reading phase is as follows: when carriers representing the electric input quantity are input into the photoelectric calculation unit through the control grid electrode, a constant bias voltage is applied between an N-type source electrode and an N-type drain electrode in the P-type substrate, so that the carriers under the combined action of the optical input quantity and the electric input quantity in a channel of a reading area on the right side of the P-type substrate are output in a current mode, and the photoelectric calculation unit enters a reading stage and finishes reading work; or when the carrier representing the electric input quantity is input into the photoelectric calculation unit through the source electrode and the drain electrode in the P-type substrate, a constant bias voltage is applied to the control grid electrode, so that a channel is generated on the surface of the reading area on the right side of the P-type substrate, and the carrier in the channel under the combined action of the optical input quantity and the electric input quantity is output in the form of current, so that the photoelectric calculation unit enters a reading stage and finishes reading work.
According to the analysis, when electric input is carried out through the control grid electrode, the photoelectric calculation unit realizes addition or binary multiplication operation, and constant bias voltage is required to be applied between the source electrode and the drain electrode of the reading area on the right side of the P-type substrate at the moment, so that current can be generated by driving carriers under the combined action of the optical input quantity and the electric input quantity in the channel and can be read; also, when the electric input is performed through the source electrode and the drain electrode, the photoelectric calculation unit performs multiplication operation, and at this time, a constant positive voltage larger than the threshold value of the MOSFET needs to be applied to the control gate electrode, so that the current generated by the carriers in the channel under the combined action of the optical input amount and the electric input amount can be driven and read out. Thus, the conditions for putting the photo-calculation unit in the readout phase are:
Figure BDA0002072616830000082
or V DS There is a constant voltage.
Example 2
The photo-electric calculation unit of example 1 can be used to form a convolution operator as shown in fig. 4, in which a convolution kernel is a convolution operator of 3*3 size, each of which has a V box, that is, represents a photo-electric calculation unit using example 1, one lead out from the long side represents a control gate lead, two leads from the short side represent leads from the source and the drain, and 9 photo-electric calculation units share an interface of a P-type substrate. The working principle of the convolution operator is as follows:
taking the convolution operation of matrix a for convolution kernel a as an example, the process of lower convolution operation is briefly introduced, where a is 10×10 matrix, a is the convolution kernel of 3*3, and the step size is 1, as shown in formula (17):
Figure BDA0002072616830000091
the rule of convolution operation is that the elements of the matrix to be convolved act on the convolution kernel one by one under the mapping of the convolution kernel, and then the convolution kernel is moved according to the corresponding step length to carry out the next mapping. To solve the convolution operation in (17), the following steps are required:
1) Zero padding operation:
extending the matrix A to be convolved from a 10 x 10 matrix to a 12 x 12 matrix, namely adding one row/column above 0 row, around 0 column, below 10 row and in 10 column, wherein the elements in the added row/column are all 0, thus zero padding is performed, and after the matrix A is changed into the matrix A 0 As shown in formula (18):
Figure BDA0002072616830000092
2) Determining an initial convolution kernel position:
the initial position of the convolution kernel coincides with the leftmost upper corner of the matrix A, i.e. 3 rows and 3 columns of the convolution kernel a respectively correspond to the matrix A 0 Rows 0, 1, 2 and columns 0, 1, 2, and then combining the elements in the convolution kernel with matrix a in the corresponding positions to the convolution kernel 0 The elements in the convolution kernel are multiplied one by one, as shown in formula (19), and become 9 multiplication results, and the 9 multiplication results are all accumulated to obtain a convolution operation result of the current convolution kernel position, which is called R 00 To complete (20) the operation:
Figure BDA0002072616830000093
(a 00 *0)+(a 01 *0)+(a 02 *0)+(a 10 *0)+(a 11 *A 00 )+(a 12 *A 01 )+(a 20 *0)+(a 21 *A 10 )+(a 22 * 11 )=R 00 (20)
3) The position of the convolution kernel is moved:
since the step length of the convolution operation is defined as 1 in advance, the position of the convolution kernel is shifted left by 1 column, namely 3 rows and 3 columns of the convolution kernel a after being shifted left by 1 column respectively correspond to the matrix A 0 Lines 0, 1, 2 and columns 1, 2, 3, and then performing convolution operation at the current position, the convolution operation result being called R 01
4) Traversing the entire matrix A with a convolution kernel 0 After that, a total of (10+2-2) 2 And (3) arranging the convolution results into a matrix according to the corresponding convolution kernel positions to obtain (21)
Figure BDA0002072616830000101
The matrix R is the tape coil matrix a, and the convolution operation with the step length of 1 is performed under the action of the convolution kernel a.
The convolution operation is the operation of multiplying the elements corresponding to the two matrices for two times and then accumulating, wherein one matrix is a convolution kernel, the other matrix is an element corresponding to the position of the convolution kernel and the convolution matrix is a variable quantity in the multiple operations, so that the advantage of storing data by utilizing optical input can be utilized, the convolution kernel data is input by adopting an optical input end, and the convolution operation is performed by inputting the data with the convolution matrix through an electric input end, and the energy efficiency ratio and the operation speed can be greatly improved. Thus, the electrical input of the cell is the data input of the matrix to be convolved of the convolution operator and the optical input is the convolution kernel input.
The convolution arithmetic unit can be divided into serial input and parallel input, and the main difference is the mode of using the number of units and the data input of the electric input end, and the serial input scheme is as follows: according to the convolution operation mode, photoelectric calculation units with the same number as the elements in the convolution kernel and adopting the first scheme are used, the units are arranged into an array with the same dimension as the convolution kernel, the output ends of the reading area in the carrier collecting and reading area are all connected, and the addition is completed through convergence.
Firstly, convolution kernel data are input into a calculation unit one by one through an optical input end, then data of a corresponding position of a current convolution kernel in a matrix are converted into binary, then the binary is input into an array on a control grid in series, the output results are converged and added and then enter a control system through AD conversion, then the convolution operation result of the current convolution kernel position is obtained through shifting and adding, then the pre-stored convolution kernel data are input in the moving convolution kernel, the electric input data are directly input again by utilizing the previous optical input, the convolution operation result corresponding to the next convolution kernel position can be obtained, and the like until the convolution kernel facilitates the whole matrix to be convolved, and then the output convolution results are recombined into a result matrix, so that all convolution operations are completed.
The following details how to control the individual optical-electrical computing units in various operating states and to perform accurate optical inputs in a convolution operator of a 3*3 convolution kernel.
The total 9 data representing 3*3 convolution kernels are respectively input into nine photoelectric calculation units through light, and the advantage of 'integrated storage and calculation' of the photoelectric calculation units is exerted by utilizing the characteristic that the convolution kernel data is unchanged in multiple convolution operations; the data in the convolved matrix is input sequentially from 9 control gate leads.
If any one of 9 photoelectric calculation units in the convolution arithmetic unit needs to enter the optical input stage, a voltage of-3V needs to be applied to the P-type substrate, 0V needs to be applied to the control grid of a device needing to enter the optical input stage, a depletion layer with a potential difference of 3V is generated, and the world-3V is arranged on the control grid of the device which does not need to enter the optical input stage, so that the up-down potential difference is 0.
If any one of 9 photoelectric calculation units in the convolution arithmetic unit needs to enter the optical input data resetting stage, a voltage of-3V needs to be kept on the P-type substrate to ensure that optical input data obtained under the condition that the photoelectric calculation unit which does not need to be reset adopts the substrate of-3V cannot be destroyed, and the optical input data resetting of a single photoelectric calculation unit can be completed by applying-4V on the control grid of a device which needs to enter the optical input resetting stage and keeping 0V on the control grid of other devices which do not need to enter the optical input resetting stage.
If any one of the 9 photoelectric calculation units in the convolution operator needs to enter the electric input stage, a voltage representing the electric input amount needs to be applied to the control gate of the unit, and 0V needs to be applied to other units, because the convolution operator is wired in such a way that the source terminals and the drain terminals of all the units are connected, the voltage between the source terminals and the drain terminals cannot be used as the electric input terminal to perform electric input on a certain unit alone.
If any one of the 9 photoelectric calculation units in the convolution operator needs to enter the readout phase, a bias voltage of 0.5V needs to be applied to the drain terminals of all the interconnected units, and 0V needs to be applied to the source terminal, because the control gate is 0V for the photoelectric calculation units which do not perform electrical input, the MOSFET of the readout area on the right side is in the off-state, and the current read from the source terminal is only the output current of the single photoelectric calculation unit which performs electrical input, so that only the unit can be considered to enter the readout phase.
If the light-emitting unit adopts a single uniform-field light source light input method, the independent accurate light input is realized by controlling the time length of each calculation unit in the light input stage; all the calculation units enter the light input stage at different time according to the duration of the light input stage, but end the light input stage at the same time. The convolution kernel matrix that needs to be input is
Figure BDA0002072616830000111
The specific steps are as follows:
1. and turning on the uniform field light source to irradiate the convolution operator.
2. Starting with the moment when the light source is turned on as 0ms, the first row of three photoelectric computing units enters the light input stage at 0ms, the second row of three photoelectric computing units does not enter the light input stage, the third row of three photoelectric computing units enters the light input stage at 10ms, all 9 photoelectric computing units are separated from the light input stage at 20ms, and the uniform field light source is turned off, wherein 2000 electrons are input to the photoelectric computing units when the representative light input quantity is 2, and if the light input is 100% accurate, 2000 electrons are precisely input to the photoelectric computing units when the uniform field light source irradiates for 20 ms.
3. V in FIG. 4 d The constant voltage value is 0.5V, and the lower end read-out terminal is 0V. And a 3V voltage is applied to the control gate lead of the upper left corner photo-calculation cell, and 0V is applied to the control gates of the other cells, so that only the upper left corner photo-calculation cell enters the readout phase and outputs current.
4. If the cell's sense current should be 10uA when the light input is exactly equal to 2000 electrons, but the cell's sense current in the upper left hand corner is actually 9uA, the cell's light input is deemed to be insufficient and the light input time of the photo-electric calculation cell is modified from 20ms to 22ms and the change is recorded. And judging and recording the light input deviation values of all the photoelectric calculation units by the same method.
5. Resetting all photoelectric calculation units, and re-inputting light according to the previously recorded corrected light input time length to obtain accurate light input quantity.
Because the convolution kernel data is unchanged in the convolution operation for multiple times, the convolution operation for multiple times can be completed after one-time accurate light input is performed.

Claims (3)

1. The control method of the working state of the photoelectric computing unit is characterized in that the photoelectric computing unit comprises a light emitting unit and a computing unit, light emitted by the light emitting unit is incident into the computing unit, and the computing unit comprises three parts: a P-type semiconductor substrate as a photogenerated carrier collection and readout region; a charge coupled layer as a coupling region; a control gate as a carrier control region; the P-type semiconductor substrate is divided into a collecting area and a reading area, wherein shallow trench isolation, an N-type source end and an N-type drain end are arranged in the reading area, and the shallow trench isolation is positioned between the collecting area and the reading area;
the control method specifically comprises the following steps: by applying different electrical conditions to the control gate, the P-type semiconductor substrate, the N-type source terminal and the N-type drain terminal, the electrical state in the computing unit is changed, so that the computing unit is in different working stages, wherein the working stages comprise: a light input stage that receives photons and generates photogenerated carriers; an electric input stage for receiving electrons and generating an operational relationship between the electrons and the photo-generated carriers; a readout phase in which the output is co-acted by the photogenerated carriers and the electrical input electrons; and a light input reset phase for erasing the light input data.
2. The method for controlling the operation state of an optoelectronic computing unit according to claim 1, wherein the method for controlling the light input stage specifically comprises: applying positive pressure on the control grid electrode, applying negative pressure on the P-type semiconductor substrate, and floating the N-type drain end and the N-type source end at the same time, so that a depletion layer capable of absorbing incident photons is generated at the bottom of the P-type semiconductor substrate, the condition of light input is achieved, and a computing unit enters a light input stage; the calculation unit is separated from the light input stage by removing or reducing the positive pressure on the control grid or removing or lifting the negative pressure on the P-type semiconductor substrate;
the control method of the light input reset stage specifically comprises the following steps: by applying a negative voltage on the control gate and a positive or zero bias on the P-type semiconductor substrate; or negative pressure or zero bias voltage is applied to the control grid electrode, positive pressure is applied to the P-type semiconductor substrate, so that photo-generated carriers collected by the collecting area are pumped out of the P-type semiconductor substrate and are combined with holes in the P-type semiconductor substrate, and the computing unit enters a light input reset stage and completes reset of light input quantity;
the control method of the electric input stage specifically comprises the following steps: inputting an electrical input into the control gate in the form of a carrier by applying a positive bias on the control gate representing the magnitude of the electrical input; or by applying a bias voltage representing the magnitude of the electric input quantity between the N-type drain terminal and the N-type source terminal of the P-type semiconductor substrate, the electric input quantity is input into a photo-generated carrier collecting and reading area of the calculating unit in the form of carriers, and the calculating unit enters an electric input stage and inputs the electric input quantity;
the control method of the reading stage comprises the following steps: when the carrier representing the electric input quantity is input into the calculating unit through the control grid electrode, a constant bias voltage is applied between the N-type source end and the N-type drain end of the P-type semiconductor substrate, so that the carrier under the combined action of the optical input quantity and the electric input quantity in the channel of the reading area is output in the form of current, and the calculating unit enters a reading stage and finishes reading work; or when the carrier representing the electric input quantity is input into the photoelectric calculation unit through the N-type source end and the N-type drain end, a constant bias voltage is applied to the control grid electrode, so that a channel is generated on the surface of the reading area, the carrier in the channel is output in the form of current after the combined action of the optical input quantity and the electric input quantity, and the calculation unit enters a reading stage and finishes the reading work.
3. The method for controlling the operation state of the photoelectric computing units according to claim 1, wherein a plurality of the photoelectric computing units are arranged in an array of a convolution kernel size in a convolution operation, and the output ends of the photo-generated carrier collecting and reading areas of all the computing units in the array are connected with each other and are summarized into one output end; the control method specifically comprises the following steps:
the light-emitting unit adopts a single uniform-field light source light input method, and realizes independent accurate light input by controlling the time length of each calculation unit in a light input stage; all the calculation units enter the light input stage according to different time lengths of the light input stage, but end the light input stage at the same time;
applying constant electric input quantity to all photoelectric calculation units in the array, and controlling a single photoelectric calculation unit with light input to enter a reading stage, while other photoelectric calculation units do not enter the reading stage; judging the accuracy of the value of the current unit light input quantity through the read-out result; recording the deviation after the deviation of the read result, and then reading the result of the next calculation unit and recording the deviation until the light input quantity verification of all calculation units is completed; and resetting and re-inputting the light input quantity of all the calculation units, correcting the light input stage duration of the calculation units with deviation of the light input quantity, and finally enabling all the calculation units to obtain the ideal light input quantity.
CN201910442809.2A 2019-05-25 2019-05-25 Control method for working state of photoelectric calculation unit Active CN110275569B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910442809.2A CN110275569B (en) 2019-05-25 2019-05-25 Control method for working state of photoelectric calculation unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910442809.2A CN110275569B (en) 2019-05-25 2019-05-25 Control method for working state of photoelectric calculation unit

Publications (2)

Publication Number Publication Date
CN110275569A CN110275569A (en) 2019-09-24
CN110275569B true CN110275569B (en) 2023-05-02

Family

ID=67960094

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910442809.2A Active CN110275569B (en) 2019-05-25 2019-05-25 Control method for working state of photoelectric calculation unit

Country Status (1)

Country Link
CN (1) CN110275569B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111208865B (en) * 2018-11-22 2021-10-08 南京大学 Photoelectric calculation unit, photoelectric calculation array and photoelectric calculation method
CN113190208B (en) * 2021-05-07 2022-12-27 电子科技大学 Storage and calculation integrated unit, state control method, integrated module, processor and equipment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0593936A (en) * 1991-10-03 1993-04-16 Mitsubishi Electric Corp Photodetector and sum of products operating device using this photodetector
CN1317761A (en) * 2000-04-12 2001-10-17 卡西欧计算机株式会社 Photoelectric sensor array and method for mfg. same
CN1337119A (en) * 1999-11-10 2002-02-20 卡西欧计算机株式会计 Photosensor system and drive control method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0593936A (en) * 1991-10-03 1993-04-16 Mitsubishi Electric Corp Photodetector and sum of products operating device using this photodetector
CN1337119A (en) * 1999-11-10 2002-02-20 卡西欧计算机株式会计 Photosensor system and drive control method thereof
CN1317761A (en) * 2000-04-12 2001-10-17 卡西欧计算机株式会社 Photoelectric sensor array and method for mfg. same

Also Published As

Publication number Publication date
CN110275569A (en) 2019-09-24

Similar Documents

Publication Publication Date Title
TWI750541B (en) Optoelectronic computing unit, optoelectronic computing array, and optoelectronic computing method
CN110276046B (en) Control method of photoelectric calculation unit
US10868075B2 (en) Dual-device photosensitive detection unit based on composite dielectric gate, detector and method thereof
CN110263296B (en) Matrix vector multiplier based on photoelectric calculation array and operation method thereof
CN102938409B (en) Based on pair transistor light-sensitive detector and the signal-obtaining way thereof of compound medium grid MOSFET
CN110275569B (en) Control method for working state of photoelectric calculation unit
CN102544039B (en) Source leak floating programming method based on composite medium gate metal-oxide-semiconductor field-effect transistor (MOSFET) photosensitive detector
CN110263295B (en) Operation optimization method of matrix vector multiplier based on photoelectric calculation array
US8248498B2 (en) Photosensitive microelectronic device with avalanche multipliers
CN103165628A (en) Multifunctional exposure imaging method based on composite dielectric grating metal-oxide-semiconductor field-effect transistor (MOSFET) light-sensitive detector
CN110009102B (en) Depth residual error network acceleration method based on photoelectric computing array
CN110244817A (en) A kind of Solving Partial Differential Equations device and its method based on photoelectricity computing array
CN110263297B (en) Control method for working state of matrix vector multiplier
CN110276048B (en) Control method for matrix vector multiplication array
CN109993283B (en) Deep convolution generation type countermeasure network acceleration method based on photoelectric calculation array
CN103165726A (en) PN junction thin film transistor non-volatilisation photoelectric detector
CN110262774B (en) Calculation method of photoelectric multiplier
CN103873792A (en) Pixel unit read-out device and method, and pixel array read-out device and method
CN110288078B (en) Accelerator and method for GoogLeNet model
CN110276047A (en) A method of matrix-vector multiplication is carried out using photoelectricity computing array
CN110045781B (en) Photoelectric calculation array input by optical structure
CN109976441A (en) A kind of photoelectricity computing device of achievable high-precision light input
CN114115801A (en) Storage-calculation integrated unit and method for realizing multiplication function
WO2021225036A1 (en) Light detection device and method for driving light sensor
CN114843295A (en) Photoelectric integrated device, array and method based on composite dielectric gate structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20240409

Address after: 210000 two, B unit 300, Zhihui Road, Kirin science and Technology Innovation Park, Jiangning District, Nanjing, Jiangsu.

Patentee after: NANJING JIXIANG SENSING IMAGING TECHNOLOGY RESEARCH INSTITUTE Co.,Ltd.

Country or region after: China

Address before: 9/F, Building B, No. 100, Tianjiao Road, Qilin Hi-tech Industrial Development Zone, Jiangning District, Nanjing, Jiangsu, 210000

Patentee before: Nanjing Weixin Photoelectric System Co.,Ltd.

Country or region before: China