CN110246766A - A kind of fan-out packaging structure and its manufacturing method - Google Patents
A kind of fan-out packaging structure and its manufacturing method Download PDFInfo
- Publication number
- CN110246766A CN110246766A CN201910506072.6A CN201910506072A CN110246766A CN 110246766 A CN110246766 A CN 110246766A CN 201910506072 A CN201910506072 A CN 201910506072A CN 110246766 A CN110246766 A CN 110246766A
- Authority
- CN
- China
- Prior art keywords
- layer
- hole
- interconnection line
- fan
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000011521 glass Substances 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims description 48
- 238000002955 isolation Methods 0.000 claims description 31
- 238000003466 welding Methods 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 239000010949 copper Substances 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 239000005360 phosphosilicate glass Substances 0.000 claims description 10
- 239000005368 silicate glass Substances 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 238000001465 metallisation Methods 0.000 claims description 6
- 229920002577 polybenzoxazole Polymers 0.000 claims description 6
- 239000004642 Polyimide Substances 0.000 claims description 5
- UBMXAAKAFOKSPA-UHFFFAOYSA-N [N].[O].[Si] Chemical compound [N].[O].[Si] UBMXAAKAFOKSPA-UHFFFAOYSA-N 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000005388 borosilicate glass Substances 0.000 claims description 5
- 229920001721 polyimide Polymers 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 4
- 239000005383 fluoride glass Substances 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 3
- VWAGSGYWIGYIIZ-UHFFFAOYSA-N [Si](O)(O)(O)O.[P].[B] Chemical compound [Si](O)(O)(O)O.[P].[B] VWAGSGYWIGYIIZ-UHFFFAOYSA-N 0.000 claims 1
- 239000005380 borophosphosilicate glass Substances 0.000 claims 1
- 150000003839 salts Chemical class 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 8
- 239000011368 organic material Substances 0.000 description 6
- 229910010272 inorganic material Inorganic materials 0.000 description 5
- 239000011147 inorganic material Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 230000008014 freezing Effects 0.000 description 2
- 238000007710 freezing Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 239000011135 tin Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000003682 fluorination reaction Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a kind of manufacturing methods of fan-out packaging structure, comprising: interim bonded layer and insulating medium layer are sequentially formed on slide glass；First is formed on insulating medium layer reroutes layer；The first chip package layer is formed on the first rewiring layer；And the second chip package layer is formed on the first chip package layer.
Description
Technical field
The present invention relates to integrated antenna package technical fields, more particularly it relates to a kind of fan-out packaging structure
And its manufacturing method.
Background technique
With the fast development of integrated circuit technique, the number of chips of unit area wafer constantly increases, the feature of chip
Size is gradually minimized to meet the requirement of Moore's Law.Although chip feature sizes reduce, the electronic component in chip
Quantity is but continuously increased (comprising resistance, capacitor, diode, transistor etc.).In order to realize chip functions answering in Product Terminal
With.The encapsulation technology that package dimension is compact, there are more outlet terminal I/O quantity is needed in encapsulation field.Traditional upside-down mounting core
I/O connection terminal is dispersed within chip surface area in wafer grade encapsulation scheme, to limit I/O linking number.Fan
Type wafer-level packaging can solve this problem out, simultaneously because it has miniaturization, low cost and high integration etc. excellent
Point, therefore rapidly becoming the selection of novel chip and Wafer level packaging.
The back side of bare chip is usually embedded in the epoxy, then in the front of bare chip by existing fan-out package
It forms dielectric layer and reroutes layer, and formed and be electrically connected between the positive pad of bare chip and rewiring layer, rerouting layer can
Again it plans the route for being connected to peripheral epoxy regions from the I/O on bare chip, then is formed on the pad for rerouting layer
Fan-out package structure is consequently formed in soldered ball raised structures.
The density that fan-out-type wafer-level packaging can be realized three-dimensional stacking is maximum, and outer dimension is minimum, and significantly
Improve chip performance and low-power consumption.However, existing fan-out package is commonly used in the same type of chip of encapsulation, Wu Fashi
Existing multichip interconnection.
Summary of the invention
Aiming at the problems existing in the prior art, according to an aspect of the present invention, a kind of fan-out packaging structure is provided
Manufacturing method, comprising:
Interim bonded layer and insulating medium layer are sequentially formed on slide glass；
First is formed on insulating medium layer reroutes layer；
The first chip package layer is formed on the first rewiring layer；And
The second chip package layer is formed on the first chip package layer.
In one embodiment of the invention, the manufacturing method of the fan-out packaging structure further includes to the interim bonded layer
It carries out solution bonding and forms soldered ball on the insulating medium layer, the soldered ball is electrically connected with the first rewiring layer formation.
In one embodiment of the invention, the first rewiring layer is formed on insulating medium layer includes:
The first transfer interconnection line is formed on insulating medium layer；
Deposit the first isolation material layer；
One or more first through hole and one or more second through-holes are formed in the first insulating layer material layers, it is described
First through hole and the second through-hole are directly contacted with the first transfer interconnection line；And
The conductive metal deposition in first through hole and the second through-hole.
In one embodiment of the invention, forming the first chip package layer on the first rewiring layer includes:
Welding structure is formed in one or more of first through hole；
One or more first chips are welded to one or more of first through hole by welding structure；
On the first isolation material layer and the second through-hole formed second transfer interconnection line, it is described second transfer interconnection line with it is right
The second through-hole answered forms electrical connection；
Deposit the second isolation material layer；
One or more third through-holes are formed in second insulating layer material layers, the third through-hole and the second transfer interconnect
Line directly contacts；And
The conductive metal deposition in third through-hole.
In one embodiment of the invention, the second chip package layer is formed on the first chip package layer includes:
Welding structure is formed on the third through-hole；
One or more second chips are welded to the third through-hole by welding structure；And
Deposit third isolation material layer.
According to another embodiment of the invention, a kind of fan-out packaging structure is provided, comprising:
Insulating medium layer；
First be formed on the insulating medium layer reroutes layer, and the first rewiring layer is described exhausted including being formed in
First transfer interconnection line of edge dielectric layer；It is formed on the first transfer interconnection line and the one or more first being electrically connected is led
Electric through-hole and one or more second through-holes；And surround the first transfer interconnection line, one or more first conductive through hole with
And the first isolation material layer of one or more second through-holes；
The first chip package layer being formed on the first rewiring layer, the first chip package layer include and one or more
The first chip of one or more of a first conductive through hole electrical connection, second be electrically connected with one or more second conductive through holes
Shift interconnection line；It is formed in the third conductive through hole on the second transfer interconnection line and being electrically connected；And the first chip of encirclement,
Second isolation material layer of the second transfer interconnection line and third conductive through hole；And
The second chip package layer being formed on the first chip package layer, the second chip package layer includes leading with third
Second chip of electric through-hole electrical connection；And surround the third isolation material layer of the second chip.
In another embodiment of the present invention, which further includes the weldering being formed on insulating medium layer
Ball, the soldered ball are electrically connected with the first transfer interconnection line formation.
In another embodiment of the present invention, which further includes being formed in the first conduction of one or more
Welding structure on through-hole and third conductive through hole, the welding structure realize that electricity connects with the interconnection structure of corresponding chip front side
Touching.
In another embodiment of the present invention, the welding structure is copper post or convex block.
In another embodiment of the present invention, the first isolation material layer, the second isolation material layer and third isolation material
The material of layer is selected from: silica, nitrogen-oxygen-silicon, borosilicate glass, phospho-silicate glass PSG, boron phosphorus silicate glass BPSG, fluorination
One of glassy silicate glass FSG, low-K medium, polyimides PI, polybenzoxazoles PBO or a variety of.
Detailed description of the invention
For the above and other advantages and features for each embodiment that the present invention is furture elucidated, will be presented with reference to attached drawing
The more specific description of various embodiments of the present invention.It is appreciated that these attached drawings only describe exemplary embodiments of the invention, therefore
It is not to be regarded as being restriction on its scope.In the accompanying drawings, in order to cheer and bright, identical or corresponding component will use identical or class
As mark indicate.Feature size in display diagram does not represent size in practice, is intended merely to apparent statement.
Fig. 1 to Fig. 5 shows the sectional view of the manufacturing process of fan-out packaging structure according to an embodiment of the invention.
Specific embodiment
In the following description, with reference to each embodiment, present invention is described.However, those skilled in the art will recognize
Know can in the case where none or multiple specific details or with other replacements and/or addition method, material or component
Implement each embodiment together.In other situations, well known structure, material or operation are not shown or are not described in detail in order to avoid making this
The aspects of each embodiment of invention is obscure.Similarly, for purposes of explanation, specific quantity, material and configuration are elaborated, with
Comprehensive understanding to the embodiment of the present invention is just provided.However, the present invention can be implemented in the case where no specific detail.This
Outside, it should be understood that each embodiment shown in the accompanying drawings is illustrative expression and is not drawn necessarily to scale.
In the present specification, the reference of " one embodiment " or " embodiment " is meaned to combine embodiment description
A particular feature, structure, or characteristic is included at least one embodiment of the invention.Occur in everywhere in this specification short
Language " in one embodiment " is not necessarily all referring to the same embodiment.
In the various embodiments of the invention, a kind of novel fan-out packaging structure is provided, it can by the fan-out packaging structure
Realize multichip interconnection.
The manufacture of fan-out packaging structure according to an embodiment of the invention is described in detail below with reference to Fig. 1 to Fig. 5
Journey.
Firstly, as shown in Figure 1, sequentially forming interim bonded layer 101 and insulating medium layer 102 on slide glass 100.In this hair
In bright specific embodiment, slide glass 100 may include diversified semiconductor material, such as silicon, germanium, GaAs, indium phosphide, carbonization
Silicon etc..Alternatively, slide glass 100 can also be made of electricity non-conducting material, such as glass, plastics or sapphire wafer.Ephemeral key
Closing layer 101 can be thermoplastic or heat curing type organic material, be also possible to the inorganic material containing ingredients such as Cu, Ni, Cr, Co, should
Interim bonded layer 101 can be bonded by the modes solution such as heating, machinery, chemistry, laser, freezing.The material of insulating medium layer 102
It can be silica, polybenzoxazoles PBO or other photosensitive classes or non-photosensitivity material.
Next, as shown in Fig. 2, forming first on insulating medium layer 102 reroutes layer.First rewiring layer includes shape
At the transfer interconnection line 111,112,113 on insulating medium layer 102；Be formed in transfer interconnection line 111,112,113 on and with
Electrical connection conductive through hole 120,121,123,124,125；And encirclement transfer interconnection line 111,112,113 and conduction are led to
The isolation material layer 110 in hole 120,121,123,124,125.
In one particular embodiment of the present invention, transfer interconnection line 111,112,113 can pass through PVD metal deposit, light
The techniques such as quarter, plating, metal erosion are formed.Transfer interconnection line 111,112,113 can be metallic copper.However the technology of this field
Personnel will be apparent to the skilled artisan that the scope of protection of the present invention is not limited to this.Shifting interconnection line 111,112,113 can also be suitable using other
Technology mode (such as metal plasma etching) deposited metal aluminium, titanium as transfer interconnection line.
After completing interconnection line manufacture, the deposition of isolation material layer 110 is carried out, isolation material layer 110 can be silica, nitrogen
Oxygen silicon, borosilicate glass, phospho-silicate glass (PSG), boron phosphorus silicate glass (BPSG), fluoride glass silicate glass
(FSG), the inorganic material such as low-K medium；Or the organic materials such as polyimides PI, polybenzoxazoles PBO.According to insulation
The difference of material forms through-hole structure 120,121,123,124,125 using mode appropriate.For example, for such as silica-based
Inorganic through-hole structure can be formed by photoetching, plasma etching mode；The organic material of PI class can be passed through
Photoetching process directly forms through-hole structure.Then, the conductive metal deposition in through-hole structure, such as copper, titanium, tungsten etc..
Isolation material layer 110 can be the dielectric sedimentary containing two layers or two layers or more.
Next, as shown in figure 3, forming the first chip package layer on the first rewiring layer.First chip package layer packet
It includes the first chip 201 being electrically connected with conductive through hole 125, the second chip 202 being electrically connected with conductive through hole 120, lead to conduction
The transfer interconnection line 211,212,213 that hole 121,123,124 is electrically connected；Be formed in transfer interconnection line 211,212,213 on and with
Electrical connection conductive through hole 220,221,222；And surround the first chip 201, the second chip 202, transfer interconnection line 211,
212,213 and conductive through hole 220,221,222 isolation material layer 200.
In a specific embodiment of the present invention, the first chip 201 and the second chip 202 can be function element.First core
Piece 201 and the second chip 202 are electrically connected with the realization of conductive through hole 120,125, therefore in order to ensure the electricity of chip and conductive through hole
Connection needs to form welding structure (not shown) on conductive through hole 120,125 in advance, which can be copper
The shapes such as column, convex block, material can be the metals such as copper, nickel, tin, silver, gold.The welding structure and the first chip 201 and the second core
The positive interconnection structure of piece 202 realizes electrical contact.
In one particular embodiment of the present invention, transfer interconnection line 211,212,213 can pass through PVD metal deposit, light
The techniques such as quarter, plating, metal erosion are formed.Transfer interconnection line 211,212,213 can be metallic copper.However the technology of this field
Personnel will be apparent to the skilled artisan that the scope of protection of the present invention is not limited to this.Shifting interconnection line 211,212,213 can also be suitable using other
Technology mode (such as metal plasma etching) deposited metal aluminium, titanium as transfer interconnection line.
After completing interconnection line manufacture, the deposition of isolation material layer 200 is carried out, isolation material layer 200 can be silica, nitrogen
Oxygen silicon, borosilicate glass, phospho-silicate glass (PSG), boron phosphorus silicate glass (BPSG), fluoride glass silicate glass
(FSG), the inorganic material such as low-K medium；Or the organic materials such as polyimides PI, polybenzoxazoles PBO.According to insulation
The difference of material forms through-hole structure 220,221,222 using mode appropriate.For example, for such as silica-based inorganic material
Matter can form through-hole structure by photoetching, plasma etching mode；Photoetching process can be passed through for the organic material of PI class
Directly form through-hole structure.Then, the conductive metal deposition in through-hole structure, such as copper, titanium, tungsten etc..
Isolation material layer 200 can be the dielectric sedimentary containing two layers or two layers or more.
Next, as shown in figure 4, forming the second chip package layer on the first chip package layer.Second chip package layer
Including the third chip 301 being electrically connected with conductive through hole 220,221,222；And surround the isolation material layer of third chip 301
300。
In a specific embodiment of the present invention, third chip 301 can be logic circuit.Third chip 301 and conduction are logical
Electrical connection, therefore being electrically connected in order to ensure chip and conductive through hole are realized in hole 220,221,222, need in advance in conductive through hole
220, welding structure (not shown) is formed on 221,222, which can for shapes, materials such as copper post, convex blocks
Think the metals such as copper, nickel, tin, silver, gold.The welding structure and the positive interconnection structure of third chip 301, which are realized, to be in electrical contact.
After the welding for completing third chip 301, the deposition of isolation material layer 300 is carried out, isolation material layer 300 can be oxygen
SiClx, nitrogen-oxygen-silicon, borosilicate glass, phospho-silicate glass (PSG), boron phosphorus silicate glass (BPSG), fluoride glass silicate
The inorganic material such as glass (FSG), low-K medium；Or the organic materials such as polyimides PI, polybenzoxazoles PBO.
Next, as shown in figure 5, carry out solution bonding, formed on 102 face of insulating medium layer soldered ball and with line of transference 111,
112,113 electrical connection is realized.In an embodiment of the present invention, can be according to the material of the interim bonded layer 101 of selection, it is suitable to select
Solution bonding method.For example, can be bonded by the modes solution such as heating, machinery, chemistry, laser, freezing.Complete solution bonding
Afterwards, the part of the surface of exposed line of transference 111,112,113 is performed etching to insulating medium layer 102, and is formed and welded in expose portion
Ball.
Although described above is various embodiments of the present invention, however, it is to be understood that they are intended only as example to present
, and without limitation.For those skilled in the relevant art it is readily apparent that various combinations, modification can be made to it
Without departing from the spirit and scope of the invention with change.Therefore, the width of the invention disclosed herein and range should not be upper
It states disclosed exemplary embodiment to be limited, and should be defined according only to the appended claims and its equivalent replacement.
Claims (10)
1. a kind of manufacturing method of fan-out packaging structure, comprising:
Interim bonded layer and insulating medium layer are sequentially formed on slide glass；
First is formed on insulating medium layer reroutes layer；
The first chip package layer is formed on the first rewiring layer；And
The second chip package layer is formed on the first chip package layer.
2. the manufacturing method of fan-out packaging structure as described in claim 1, which is characterized in that further include to the interim bonding
Layer carries out solution bonding and forms soldered ball on the insulating medium layer, and the soldered ball is electrically connected with the first rewiring layer formation.
3. the manufacturing method of fan-out packaging structure as described in claim 1, which is characterized in that form on insulating medium layer
One, which reroutes layer, includes:
The first transfer interconnection line is formed on insulating medium layer；
Deposit the first isolation material layer；
The one or more first through hole of formation and one or more second through-holes in the first insulating layer material layers, described first
Through-hole and the second through-hole are directly contacted with the first transfer interconnection line；And
The conductive metal deposition in first through hole and the second through-hole.
4. the manufacturing method of fan-out packaging structure as claimed in claim 3, which is characterized in that formed on the first rewiring layer
First chip package layer includes:
Welding structure is formed in one or more of first through hole；
One or more first chips are welded to one or more of first through hole by welding structure；
On the first isolation material layer and the second through-hole formed second transfer interconnection line, it is described second transfer interconnection line with it is corresponding
Second through-hole forms electrical connection；
Deposit the second isolation material layer；
One or more third through-holes are formed in second insulating layer material layers, the third through-hole and the second transfer interconnection line are straight
Contact；And
The conductive metal deposition in third through-hole.
5. the manufacturing method of fan-out packaging structure as claimed in claim 4, which is characterized in that the shape on the first chip package layer
Include: at the second chip package layer
Welding structure is formed on the third through-hole；
One or more second chips are welded to the third through-hole by welding structure；And
Deposit third isolation material layer.
6. a kind of fan-out packaging structure, comprising:
Insulating medium layer；
First be formed on the insulating medium layer reroutes layer, and the first rewiring layer includes being formed in the insulation to be situated between
First transfer interconnection line of matter layer；It is conductive logical to be formed in the one or more first on the first transfer interconnection line and being electrically connected
Hole and one or more second through-holes；And surround the first transfer interconnection line, one or more first conductive through holes and one
First isolation material layer of a or multiple second through-holes；
The first chip package layer being formed on the first rewiring layer, the first chip package layer include and one or more the
The first chip of one or more of one conductive through hole electrical connection, the second transfer being electrically connected with one or more second conductive through holes
Interconnection line；It is formed in the third conductive through hole on the second transfer interconnection line and being electrically connected；And surround the first chip, second
Shift the second isolation material layer of interconnection line and third conductive through hole；And
The second chip package layer being formed on the first chip package layer, the second chip package layer include logical with third conduction
Second chip of hole electrical connection；And surround the third isolation material layer of the second chip.
7. fan-out packaging structure as claimed in claim 6, which is characterized in that further include the weldering being formed on insulating medium layer
Ball, the soldered ball are electrically connected with the first transfer interconnection line formation.
8. fan-out packaging structure as claimed in claim 6, which is characterized in that further include being formed in the first conduction of one or more
Welding structure on through-hole and third conductive through hole, the welding structure realize that electricity connects with the interconnection structure of corresponding chip front side
Touching.
9. fan-out packaging structure as claimed in claim 8, which is characterized in that the welding structure is copper post or convex block.
10. fan-out packaging structure as claimed in claim 6, which is characterized in that the first isolation material layer, the second isolation material layer
It is selected from the material of third isolation material layer: silica, nitrogen-oxygen-silicon, borosilicate glass, phospho-silicate glass PSG, boron phosphorus silicic acid
One of salt glass BPSG, fluoride glass silicate glass FSG, low-K medium, polyimides PI, polybenzoxazoles PBO or
It is a variety of.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910506072.6A CN110246766A (en) | 2019-06-12 | 2019-06-12 | A kind of fan-out packaging structure and its manufacturing method |
| PCT/CN2020/094536 WO2020248902A1 (en) | 2019-06-12 | 2020-06-05 | Fan-out packaging structure and fabrication method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910506072.6A CN110246766A (en) | 2019-06-12 | 2019-06-12 | A kind of fan-out packaging structure and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110246766A true CN110246766A (en) | 2019-09-17 |
Family
ID=67886724
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910506072.6A Pending CN110246766A (en) | 2019-06-12 | 2019-06-12 | A kind of fan-out packaging structure and its manufacturing method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110246766A (en) |
| WO (1) | WO2020248902A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020248902A1 (en) * | 2019-06-12 | 2020-12-17 | 上海先方半导体有限公司 | Fan-out packaging structure and fabrication method therefor |
| CN113594152A (en) * | 2021-07-12 | 2021-11-02 | 南京国博电子股份有限公司 | Three-dimensional integrated module of heavy current PMOS pipe and driver |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160322288A1 (en) * | 2012-10-19 | 2016-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-Out Wafer Level Package Structure |
| CN107758604A (en) * | 2017-11-03 | 2018-03-06 | 纽威仕微电子（无锡）有限公司 | The fan-out package structure and method of MEMS hydrophone chips |
| CN207760033U (en) * | 2017-11-03 | 2018-08-24 | 纽威仕微电子（无锡）有限公司 | The fan-out package structure of MEMS hydrophone chips |
| CN109037080A (en) * | 2018-06-29 | 2018-12-18 | 华进半导体封装先导技术研发中心有限公司 | A kind of integrated IPD encapsulating structure and its manufacturing method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108109928A (en) * | 2017-12-29 | 2018-06-01 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure and method for packing of semiconductor chip |
| CN109801883A (en) * | 2018-12-29 | 2019-05-24 | 华进半导体封装先导技术研发中心有限公司 | A kind of fan-out-type stacking encapsulation method and structure |
| CN110246766A (en) * | 2019-06-12 | 2019-09-17 | 上海先方半导体有限公司 | A kind of fan-out packaging structure and its manufacturing method |
-
2019
- 2019-06-12 CN CN201910506072.6A patent/CN110246766A/en active Pending
-
2020
- 2020-06-05 WO PCT/CN2020/094536 patent/WO2020248902A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160322288A1 (en) * | 2012-10-19 | 2016-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-Out Wafer Level Package Structure |
| CN107758604A (en) * | 2017-11-03 | 2018-03-06 | 纽威仕微电子（无锡）有限公司 | The fan-out package structure and method of MEMS hydrophone chips |
| CN207760033U (en) * | 2017-11-03 | 2018-08-24 | 纽威仕微电子（无锡）有限公司 | The fan-out package structure of MEMS hydrophone chips |
| CN109037080A (en) * | 2018-06-29 | 2018-12-18 | 华进半导体封装先导技术研发中心有限公司 | A kind of integrated IPD encapsulating structure and its manufacturing method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020248902A1 (en) * | 2019-06-12 | 2020-12-17 | 上海先方半导体有限公司 | Fan-out packaging structure and fabrication method therefor |
| CN113594152A (en) * | 2021-07-12 | 2021-11-02 | 南京国博电子股份有限公司 | Three-dimensional integrated module of heavy current PMOS pipe and driver |
| CN113594152B (en) * | 2021-07-12 | 2024-03-19 | 南京国博电子股份有限公司 | Three-dimensional integrated module of heavy-current PMOS tube and driver |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020248902A1 (en) | 2020-12-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10134711B2 (en) | Thermally enhanced semiconductor assembly with three dimensional integration and method of making the same | |
| KR100766028B1 (en) | Light Emitting Diode Package And Process Of Making The Same | |
| CN110504247A (en) | Ic package and forming method thereof | |
| CN106469701B (en) | Semiconductor device structure and forming method thereof | |
| US20070290300A1 (en) | Semiconductor device and method for manufacturing same | |
| CN103779297A (en) | Metal bump joint structure | |
| CN102983109A (en) | Thermally enhanced structure for multi-chip device | |
| CN102024684A (en) | Semiconductor device and method of forming integrated passive device | |
| CN102412197A (en) | Semiconductor device and method of forming conductive tsv with insulating annular ring | |
| CN104900782A (en) | Method of making thermally enhanced wiring board having isolator incorporated therein | |
| CN101626056A (en) | Semiconductor device and fabrication methods thereof | |
| CN103258803A (en) | Semiconductor device and method for manufacturing same | |
| CN106031315A (en) | Circuit board and circuit board assembly | |
| CN102820259A (en) | Semiconductor device and method of forming a power MOSFET | |
| CN110246766A (en) | A kind of fan-out packaging structure and its manufacturing method | |
| CN102160197A (en) | Optoelectronic device submount | |
| CN208271901U (en) | OLED display module and OLED show equipment | |
| CN102456634A (en) | Packaging board and manufacturing method thereof | |
| CN104037145B (en) | For wafer-class encapsulation by padding the contact limited | |
| US20110291155A1 (en) | Light-Emitting Diode Chip Package Body and Method for Manufacturing Same | |
| CN110246816A (en) | A kind of three-dimensional stacked fluid channel radiator structure of wafer scale and its manufacturing method | |
| CN110211888A (en) | A kind of embedded fan-out packaging structure and its manufacturing method | |
| CN106935517B (en) | Framework encapsulation structure of integrated passive devices and preparation method thereof | |
| CN101814569B (en) | Light emitting device package | |
| CN110400781A (en) | Three-dimensionally integrated encapsulation pinboard based on glass substrate and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190917 |