CN110221644B - Chip and external RSET resistance open circuit monitoring circuit thereof - Google Patents
Chip and external RSET resistance open circuit monitoring circuit thereof Download PDFInfo
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- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
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Abstract
The invention provides an external RSET resistance open circuit monitoring circuit of a chip, which takes the current smaller than a preset value as a detection current, and because the current smaller than the preset value has little influence on the input bias current, the external RSET resistance open circuit monitoring circuit can output the detection current to a bias port of the chip through a detection current injection branch circuit in the whole operation process of the chip, detect the voltage of the bias port or the output end voltage of an operational amplifier through a voltage detection branch circuit, further judge the voltage of the bias port or the output end voltage of the operational amplifier through a logic judgment branch circuit, and output a monitoring result hanging outside the bias port if the voltage of the bias port is high level or the output end voltage of the operational amplifier is low level; therefore, the problem that whether the chip bias port is in a suspended state or not can not be judged and monitored when the chip is in a normal operation state in the prior art is solved.
Description
Technical Field
The invention relates to the technical field of circuit protection, in particular to a chip and an external RSET (resistor-resistor open circuit) monitoring circuit thereof.
Background
Usually, the method of externally arranging the RSET resistor on the chip is adopted to realize the requirement of the client on adjusting the input bias current IBIAS. After the method is adopted, a client can adjust the input bias current IBIAS by adjusting the resistance value of the external RSET resistor, and the operation is very convenient.
However, the method for adjusting the input bias current IBIAS has the problem that the port of the chip connected with the RSET resistor is suspended due to cold solder joint or open circuit damage of the RSET resistor, and when the port of the chip connected with the RSET resistor is suspended, the whole chip cannot work normally and the reason of the fault is difficult to judge. Therefore, at present, whether a port of the chip connected with the RSET resistor is in a floating state or not is judged and monitored by transmitting detection current to a bias circuit and the RSET resistor of the chip, wherein the port of the chip connected with the RSET resistor is a bias port of the chip.
However, the method can only determine and monitor whether the outside of the offset port is in a suspended state within a short time after the chip is started, and when the chip is in a normal operation state, the method cannot determine and monitor whether the outside of the offset port is in a suspended state.
Disclosure of Invention
In view of this, embodiments of the present invention provide a chip and an external RSET resistor open circuit monitoring circuit thereof, so as to solve the problem that whether a bias port is in a floating state or not cannot be determined and monitored when the chip is in a normal operation state.
In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions:
one aspect of the present invention provides an external RSET resistor open circuit monitoring circuit for a chip, including: the device comprises a detection current injection branch, a voltage detection branch and a logic judgment branch; wherein:
the detection current injection branch, the voltage detection branch and the logic judgment branch are all arranged in a chip;
the output end of the detection current injection branch circuit, the output end of the bias circuit in the chip and the inverting input end of the operational amplifier in the chip are connected, a connection point is used as a bias port of the chip, and the bias port is used for being grounded through an external RSET resistor;
the detection current injection branch circuit is used for outputting detection current to the bias port, and the detection current is smaller than a preset value;
the input end of the voltage detection branch circuit is connected with the bias port or the output end of the operational amplifier; the voltage detection branch circuit is used for detecting the voltage of the bias port or the voltage of the output end of the operational amplifier;
the input end of the logic judgment branch is connected with the output end of the voltage detection branch, and the logic judgment branch is used for judging the voltage of the bias port or the voltage of the output end of the operational amplifier and generating a monitoring result that the bias port is suspended outside when the voltage of the bias port is at a high level or the voltage of the output end of the operational amplifier is at a low level.
Optionally, the detection current injection branch comprises a first current source; the output end of the first current source is the output end of the detection current injection branch, and the input end of the first current source is the input end of the detection current injection branch.
Optionally, the preset value is less than 1 μ a.
Optionally, the detection circuit further comprises a pull-down current leading-out branch, which is used for leading out a pull-down current from the bias circuit, wherein the pull-down current is less than or equal to the detection current; the output end of the pull-down current leading-out branch circuit is grounded, and the input end of the pull-down current leading-out branch circuit is connected with the input end of the bias circuit.
Optionally, the pull-down current is equal to the detection current.
Optionally, the pull-down current leading-out branch includes a second current source; the output end of the second current source is the output end of the pull-down current leading-out branch, and the input end of the second current source is the input end of the pull-down current leading-out branch.
Another aspect of the present invention provides a chip, including: the chip comprises a bias circuit, an operational amplifier and an external RSET (resistor-resistor open circuit) monitoring circuit of any one of the chips; wherein:
the non-inverting input end of the operational amplifier receives a reference voltage;
the inverting input end of the operational amplifier is connected with the output end of the bias circuit;
the output end of the operational amplifier is connected with the control end of the bias circuit;
the bias port of the chip is externally connected with a grounded RSET resistor.
Compared with the prior art, the current smaller than the preset value is used as the detection current, and the current smaller than the preset value has little influence on the input bias current, so that the detection current can be injected into the branch circuit through the detection current to output the detection current to the bias port of the chip in the whole operation process of the chip, the voltage of the bias port or the output end voltage of the operational amplifier is detected through the voltage detection branch circuit, the voltage of the bias port or the output end voltage of the operational amplifier is further judged through the logic judgment branch circuit, and if the voltage of the bias port is in a high level or the output end voltage of the operational amplifier is in a low level, a monitoring result which is suspended outside the bias port is output; therefore, the problem that whether the chip bias port is in an external suspension state or not can not be judged and monitored when the chip is in a normal operation state in the prior art is solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a diagram of a prior art chip according to the present invention;
FIG. 2 is a schematic diagram of a monitoring circuit according to the prior art;
fig. 3 is an external RSET resistor open circuit monitoring circuit of the chip according to the embodiment of the present invention;
fig. 4 is a circuit for monitoring an open circuit of a chip and an external RSET resistor of the chip according to another embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
In this application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In the prior art, in order to conveniently adjust an input bias current, an RSET chip is usually required to be externally connected to a bias port of the chip, and the specific structure is shown in fig. 1.
The chip comprises an operational amplifier AMP, wherein the non-inverting input end of the operational amplifier AMP receives a reference voltage VREF, the output end of the operational amplifier AMP is connected with the control end of a bias circuit (comprising a switching tube M), the inverting input end of the operational amplifier AMP is connected with the output end of the bias circuit, and a connection point A is connected with a bias port of the chip, namely the bias port is a concrete representation form of the connection point A to the outside of the chip; the input end of the bias circuit receives input bias current; the bias port is grounded through an external RSET resistor.
Since the output terminal of the operational amplifier AMP forms negative feedback with its inverting input terminal through the bias circuit, the voltage at the bias port of the chip is made equal to the reference voltage VREF, and the input bias current IBIAS becomes VREF/RSET.
However, when the external RSET resistor of the chip is in a floating state, that is, the RSET resistor and the chip are in an open circuit, the RSET resistor is infinite, the input bias current IBIAS is almost zero, and in order to be able to timely determine and monitor whether the bias port of the chip is in an external floating state, the prior art generally adopts a mode of outputting the detection current IOPEN to the bias port, and the specific structure is as shown in fig. 2.
After the detection current IOPEN is output to a connection point A in the chip, the voltage of the bias port or the voltage of the output end of the operational amplifier is detected and judged, if the voltage of the bias port is high level or the voltage of the output end of the operational amplifier is low level, the bias port of the chip is in an external suspension state, otherwise, the bias port of the chip is not in the external suspension state.
However, in this method, after a period of time, usually tens of microseconds, the output of the detection current IOPEN to the bias port is stopped to avoid the influence on the input bias current IBIAS, so that the prior art cannot determine and monitor whether the bias port is in a floating state when the chip is in a normal operating state.
In order to solve the problem that whether a bias port is in a suspended state or not cannot be judged and monitored when a chip is in a normal operation state, an embodiment of the present invention provides an external RSET resistor open circuit monitoring circuit for a chip, as shown in fig. 3, which has a specific structure including: a sense current injection branch 110, a voltage sense branch 120, and a logic decision branch 130.
The RSET resistor is arranged outside the chip, one end of the RSET resistor is grounded, and the other end of the RSET resistor is connected with a bias port of the chip.
The detection current injection branch 110, the voltage detection branch 120 and the logic judgment branch 130 are all disposed inside the chip.
The output end of the detection current injection branch circuit 110, the output end of a bias circuit (including a switching tube M) in the chip interior, and the inverting input end of an operational amplifier AMP in the chip are all connected, the connection point a is used as a bias port of the chip, the circuit is realized in a manner that the connection point a is led out to the edge of the chip in a port form through a connection line, that is, the bias port is a specific representation form of the connection point a to the outside of the chip, and further, the detection current injection branch circuit 110 outputs the detection current IOPEN to the bias port through the output end thereof, and the detection current IOPEN is smaller than a preset value.
Optionally, the preset value is smaller than 1 μ a, where the preset value is smaller than 1 μ a to reduce the influence of the detection current IOPEN on the input bias current IBIAS in the bias circuit, and if the chip has a higher requirement on the precision of the input bias current IBIAS, the preset value needs to be set lower, so as to improve the precision of the input bias current IBIAS; therefore, the preset value is determined according to the precision requirement of the chip on the input bias current IBIAS; however, if the detection current IOPEN is too small, the monitoring result may be incorrect, and thus the preset value is usually tens or hundreds of nanoamperes.
The input end of the voltage detecting branch 120 is connected to the bias port or the output end of the operational amplifier (shown in fig. 3 by being connected to the bias port as an example), and is used for detecting the voltage of the bias port or the voltage of the output end of the budget amplifier.
The input end of the logic judgment branch 130 is connected to the output end of the voltage detection branch 120, so that the logic judgment branch 130 judges the voltage of the bias port or the voltage of the output end of the operational amplifier AMP; if the voltage of the bias port is high level or the voltage of the output end of the operational amplifier AMP is low level, the logic judgment branch 130 generates a monitoring result of the bias port hanging outside, and outputs the monitoring result through the output end of the logic judgment branch; otherwise, the logic determining branch 130 outputs the monitoring result that the external part of the offset terminal is not suspended through its output terminal or has no output.
It should be noted that, in this embodiment, although the detection current IOPEN is output to the bias port in the whole operation process of the chip, that is, the input bias current IBIAS is equal to VREF/RSET-IOPEN at this time, since the detection current IOPEN is smaller than the preset value, and the preset value is smaller than 1 μ a, that is, the detection current IOPEN has little influence on the input bias current IBIAS, the input bias current IBIAS is approximately equal to VREF/RSET.
Compared with the prior art, the current smaller than the preset value is used as the detection current, and the influence of the current smaller than the preset value on the input bias current IBIAS is very small, so that the detection current can be output to the bias port of the chip through the detection current injection branch circuit 110 in the whole operation process of the chip, the voltage of the bias port or the output end voltage of the operational amplifier is detected through the voltage detection branch circuit 120, the voltage of the bias port or the output end voltage of the operational amplifier is further judged through the logic judgment branch circuit 130, and if the voltage of the bias port is high level or the output end voltage of the operational amplifier is low level, a suspended monitoring result outside the bias port is output; therefore, the problem that whether the chip bias port is in an external suspension state or not can not be judged and monitored when the chip is in a normal operation state in the prior art is solved.
In practical applications, one embodiment of the detection current injection branch 110, as shown in fig. 3, includes the following specific structure: a first current source 111; the output end of the first current source 111 is the output end of the detection current injection branch circuit 110, and the input end thereof is the input end of the detection current injection branch circuit 110, and is used for providing the detection current IOPEN required by the monitoring circuit of the present invention when detecting the connection state of the RSET resistor in real time.
It should be noted that, in practical applications, the detection current IOPEN may be provided by not only a current source, but also other chips or circuits, and is not specifically limited herein, depending on the specific application environment, and is within the protection scope of the present application.
When the requirement on the accuracy of the input bias current IBIAS is low, the current smaller than the preset value is output to the bias port as the detection current IOPEN in the above embodiment, and the manner of detecting whether the bias port is in a floating state may be satisfied, but when the requirement on the accuracy of the input bias current IBIAS is high, the manner in the above embodiment is no longer applicable, so that another embodiment of the present invention provides an external RSET resistor open-circuit monitoring circuit for a chip, as shown in fig. 4, on the basis of the above embodiment and fig. 3, further including: the pull-down current draws branch 140.
The output end of the pull-down current drawing branch 140 is grounded, the input end of the pull-down current drawing branch 140 is connected to the input end of the bias circuit, and the pull-down current drawing branch 140 draws a pull-down current IOPEN _ offset from the bias circuit, and the drawn pull-down current IOPEN _ offset is less than or equal to the detection current IOPEN.
It should be noted that, at this time, the input offset current IBIAS is equal to VREF/RSET-IOPEN + IOPEN _ offset, and since IOPEN _ offset is equal to IOPEN, the input offset current IBIAS in this embodiment is closer to VREF/RSET, i.e., the true input offset current, on the premise that the detected current IOPEN is the same as in the above embodiment.
In the embodiment, the input end of the bias circuit is connected with the pull-down current lead-out branch 140 in parallel, so that the input bias current IBIAS is closer to the real input bias current under the same detection current, that is, the precision of the input bias current IBIAS is improved; in addition, since the pull-down current IOPEN _ offset always exists at the input end of the pull-down current drawing branch 140, the input offset current IBIAS is not zero, and the chip is effectively ensured not to be in an uncertain state.
Further, when the pull-down current IOPEN _ offset is equal to the detection current IOPEN, the input bias current IBIAS ═ VREF/RSET-IOPEN + IOPEN _ offset ═ VREF/RSET is the same as the true input bias current.
In practical applications, one embodiment of the pull-down current drawing branch 140, as shown in fig. 4, includes: a second current source 141; the output end of the second current source 141 is the output end of the pull-down current leading-out branch 140, and the input end thereof is the input end of the pull-down current leading-out branch 140.
It should be noted that, in practical applications, the pull-down current IOPEN _ offset may be provided not only by a current source, but also by other chips or circuits, and is not specifically limited herein, depending on the specific application environment, and is within the protection scope of the present application.
Another embodiment of the present invention provides a chip, as shown in fig. 4, which includes: the bias circuit 210, the operational amplifier AMP, and the external RSET resistance open circuit monitoring circuit 220 of the chip provided by the above embodiments.
The non-inverting input terminal of the operational amplifier AMP receives the reference voltage VREF, the inverting input terminal is connected to the output terminal of the bias circuit 210, and the output terminal is connected to the control terminal of the bias circuit 210.
The bias port of the chip is externally connected with a grounded RSET resistor.
Compared with the prior art, the embodiment provides whether the chip can monitor the bias port in an external suspension manner in the whole operation process of the chip, so that the bias port of the chip can be found in an external suspension manner in time, and the workload of searching for the fault reason of the chip by a worker is reduced.
The embodiments of the invention are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (6)
1. An external RSET resistance open circuit monitoring circuit of chip which characterized in that includes: the device comprises a detection current injection branch, a voltage detection branch and a logic judgment branch; wherein:
the detection current injection branch, the voltage detection branch and the logic judgment branch are all arranged in a chip;
the output end of the detection current injection branch circuit, the output end of the bias circuit in the chip and the inverting input end of the operational amplifier in the chip are connected, a connection point is used as a bias port of the chip, and the bias port is used for being grounded through an external RSET resistor;
the detection current injection branch circuit is used for outputting detection current to the bias port, and the detection current is smaller than a preset value;
the input end of the voltage detection branch circuit is connected with the bias port or the output end of the operational amplifier; the voltage detection branch circuit is used for detecting the voltage of the bias port or the voltage of the output end of the operational amplifier;
the input end of the logic judgment branch is connected with the output end of the voltage detection branch, and the logic judgment branch is used for judging the voltage of the bias port or the voltage of the output end of the operational amplifier and generating a monitoring result of the external suspension of the bias port when the voltage of the bias port is at a high level or the voltage of the output end of the operational amplifier is at a low level;
the pull-down current leading-out branch is used for leading out a pull-down current from the bias circuit, and the pull-down current is less than or equal to the detection current; the output end of the pull-down current leading-out branch circuit is grounded, and the input end of the pull-down current leading-out branch circuit is connected with the input end of the bias circuit.
2. The external RSET resistor open circuit monitoring circuit of claim 1, wherein the detection current injection branch comprises a first current source; the output end of the first current source is the output end of the detection current injection branch, and the input end of the first current source is the input end of the detection current injection branch.
3. The external RSET resistance open circuit monitoring circuit of the chip as claimed in claim 1 or 2, wherein the preset value is less than 1 μ A.
4. The external RSET resistor open circuit monitoring circuit of claim 1, wherein the pull-down current is equal to the detection current.
5. The external RSET resistor open circuit monitoring circuit of claim 1, wherein the pull-down current drawing branch comprises a second current source; the output end of the second current source is the output end of the pull-down current leading-out branch, and the input end of the second current source is the input end of the pull-down current leading-out branch.
6. A chip, comprising: a bias circuit, an operational amplifier and an external RSET resistance open circuit monitoring circuit of the chip as claimed in any one of claims 1-5; wherein:
the non-inverting input end of the operational amplifier receives a reference voltage;
the inverting input end of the operational amplifier is connected with the output end of the bias circuit;
the output end of the operational amplifier is connected with the control end of the bias circuit;
the bias port of the chip is externally connected with a grounded RSET resistor.
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| CN201910433031.9A CN110221644B (en) | 2019-05-23 | 2019-05-23 | Chip and external RSET resistance open circuit monitoring circuit thereof |
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| CN201910433031.9A CN110221644B (en) | 2019-05-23 | 2019-05-23 | Chip and external RSET resistance open circuit monitoring circuit thereof |
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| US5107199A (en) * | 1990-12-24 | 1992-04-21 | Xerox Corporation | Temperature compensated resistive circuit |
| JP3759135B2 (en) * | 2003-09-12 | 2006-03-22 | ローム株式会社 | Semiconductor device and electronic device |
| JP2004152092A (en) * | 2002-10-31 | 2004-05-27 | Matsushita Electric Ind Co Ltd | Voltage source circuit |
| CN101661301B (en) * | 2008-08-25 | 2011-06-29 | 原相科技股份有限公司 | Low-voltage-drop linear voltage regulator with frequency compensation |
| CN202059165U (en) * | 2011-04-26 | 2011-11-30 | 广东明阳龙源电力电子有限公司 | Controller for on-line detecting IGBT device short circuit and open circuit fault |
| CN102622032B (en) * | 2012-04-17 | 2014-04-02 | 钜泉光电科技(上海)股份有限公司 | Low temperature coefficient bandgap voltage reference circuit |
| CN103063979B (en) * | 2013-01-04 | 2014-12-31 | 合肥市英唐科技有限公司 | Load open-circuit detection circuit |
| WO2014111916A1 (en) * | 2013-01-17 | 2014-07-24 | Microsemi Corp. - Analog Mixed Signal Group, Ltd. | On-chip port current control arrangement |
| US9645195B2 (en) * | 2014-05-27 | 2017-05-09 | Freescale Semiconductor, Inc. | System for testing integrated circuit |
| US9444478B2 (en) * | 2014-09-10 | 2016-09-13 | Texas Instruments Incorporated | Voltage regulator with load compensation |
| JP6619274B2 (en) * | 2016-03-23 | 2019-12-11 | エイブリック株式会社 | Voltage regulator |
| CN106385100B (en) * | 2016-09-18 | 2019-11-05 | 英特格灵芯片(天津)有限公司 | LDO circuit |
| EP3598740B1 (en) * | 2018-02-27 | 2022-09-14 | Shenzhen Goodix Technology Co., Ltd. | Image sensor and output compensation circuit of image sensor |
| CN109164865B (en) * | 2018-11-23 | 2021-07-27 | 湖南国科微电子股份有限公司 | Overshoot protection circuit, linear voltage regulator and power module |
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