CN106385100B

CN106385100B - LDO circuit

Info

Publication number: CN106385100B
Application number: CN201610829204.5A
Authority: CN
Inventors: 杨靖; 梅当民; 刘柳
Original assignee: Integrin Chip (tianjin) Co Ltd
Current assignee: Sichuan Yichong Technology Co ltd
Priority date: 2016-09-18
Filing date: 2016-09-18
Publication date: 2019-11-05
Anticipated expiration: 2036-09-18
Also published as: CN106385100A

Abstract

The present invention relates to a kind of LDO circuits, the LDO circuit includes the first power supply, second source, the first LDO main body module (002), the 2nd LDO main body module (003) and gating module (004), and the first power supply and second source are used to provide power supply to LDO circuit；Gating module (004) includes two input terminals, two input terminals are separately connected the first power supply and second source, and one of gating module (004) is used to being selected from the first LDO main body module (002) and the 2nd LDO main body module (003) according to the first power supply and second source powers for chip interior.The present invention selects any power supply in double power-supply system to power to chip interior by the way that in double power-supply system, setting gates structure, meanwhile, dual power supply is turned off by detection surge voltage, plays safe power supply.

Description

LDO circuit

Technical Field

The invention relates to the field of high-voltage circuit design, in particular to an LDO (low dropout regulator) circuit.

Background

The application of the current OTG technology is developed rapidly, the current OTG is not limited to data transmission, but also includes energy transmission, and in a non-OTG mode, energy is transmitted from one end to the other end, and in an OTG mode, energy is in the opposite transmission direction. The energy of the corresponding control circuit may come from any one end, and how to ensure that the control circuit obtains a normal voltage becomes a problem to be solved.

Fig. 1 shows a conventional LDO circuit, and the conventional LDO architecture has only one source for power supply. The circuit consists of a series adjusting tube P1, sampling resistors R1 and R2, an amplifier AMP1, a compensation capacitor C1 and HV _ BIAS. HV _ BIAS mainly functions to generate voltage and current BIAS, a compensation capacitor C1 is added for loop stability, and other devices form a main working circuit of the LDO. The sampled feedback voltage FB is applied to the non-inverting input of amplifier AMP1, and compared to a reference VREF applied to the inverting input, the difference between the sampled feedback voltage FB and the reference VREF is amplified by the amplifier, and the voltage drop across the series regulator is controlled to stabilize the output voltage. When the output voltage VDD6V decreases, the difference between the reference voltage and the sampled voltage increases and the amplifier output voltage decreases, thereby increasing the output voltage. Conversely, if the output voltage VDD6V exceeds the desired set point, the amplifier output voltage increases, thereby decreasing the output voltage.

Disclosure of Invention

The invention aims to solve the technical problems and provides an LDO circuit.

To achieve the above object, the present invention provides an LDO circuit, including: the first LDO main body module is connected with the second LDO main body module; the first power supply and the second power supply are used for supplying power to the LDO circuit; the gating module comprises two input ends, the two input ends are respectively connected with a first power supply and a second power supply, and the gating module is used for supplying power to the interior of the chip from one selected from the first LDO main body module and the second LDO main body module according to the first power supply and the second power supply.

Preferably, the gating module compares the first power supply with the second power supply, and when the first power supply is larger than the second power supply, the first LDO main body module supplies power to the inside of the chip; when the value of the first power supply is smaller than that of the second power supply, the first LDO main body module supplies power to the inside of the chip.

Preferably, the gating module includes: a comparator, an inverter, a third transistor, and a fourth transistor;

the first input end of the comparator is connected with a first power supply, the second input end of the comparator is connected with a second power supply, and the output end of the comparator is connected with the input end of the phase inverter and the second end of the fourth transistor; the output end of the inverter is connected with the second end of the third transistor; the first end of the third transistor is connected with the first LDO main body module, and the third end of the third transistor is connected with the third end of the fourth transistor; the first end of the fourth transistor is connected with the second LDO main body module;

when the value of the first power supply connected with the first input end of the comparator is larger than the value of the second power supply connected with the second input end of the comparator, the third transistor is in a conducting state, and the fourth transistor is in a cut-off state; when the value of the first power supply at the first input terminal of the comparator is smaller than the value of the second power supply at the second input terminal of the comparator, the third transistor is in an off state and the fourth transistor is in an on state.

Preferably, the first LDO body module includes: a first transistor;

the second end of the first transistor is connected with a first power supply, and the third end of the first transistor is connected with the first end of the third transistor;

when the value of the first power supply connected with the first input end of the comparator is larger than the value of the second power supply connected with the second input end of the comparator, the third transistor is in a conducting state, the first end of the third transistor is connected with the third end of the first transistor, and therefore the first LDO main body module supplies power to the inside of the chip.

Preferably, the second LDO body module includes: a second transistor;

a second end of the second transistor is input with a second power supply, and a third end of the second transistor is connected with a first end of the fourth transistor;

when the value of the first power source connected with the first input end of the comparator is smaller than the value of the second power source connected with the second input end of the comparator, the fourth transistor is in a conducting state, the first end of the fourth transistor is connected with the third end of the second transistor, and then the second LDO main body module supplies power to the inside of the chip.

Preferably, the circuit further comprises: a first protection module;

the first protection module is used for turning off the first LDO main body module when detecting surge voltage.

Preferably, the first protection circuit includes: a fifth transistor;

the third end of the fifth transistor is connected with the first end of the first transistor;

when the second end of the fifth transistor detects surge voltage, the fifth transistor charges the first end of the first transistor through the third end of the fifth transistor, and the purposes of turning off the first transistor and protecting an internal chip are achieved.

Preferably, the circuit further comprises: a second protection module;

the second protection module is used for turning off the second LDO main body module when detecting surge voltage.

Preferably, the second protection circuit includes: a sixth transistor;

the third end of the sixth transistor is connected with the first end of the second transistor;

when the second end of the sixth transistor detects surge voltage, the sixth transistor charges the first end of the second transistor through the third end of the sixth transistor, and the purposes of turning off the second transistor and protecting an internal chip are achieved.

Preferably, the circuit further comprises a reference module;

the reference module is used for providing working voltage for the first LDO main body module and the second LDO main body module.

According to the invention, a gating structure is arranged in the dual power supply system, any power supply in the dual power supply system is selected to supply power to the interior of the chip, and meanwhile, the dual power supplies are switched off by detecting surge voltage, so that safe power supply is realized.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

FIG. 1 is a schematic diagram of a prior art LDO module;

fig. 2 is a schematic structural diagram of an LDO circuit according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of one embodiment of the reference module of FIG. 2;

FIG. 4 is a schematic diagram of an embodiment of the first LDO body module of FIG. 2;

FIG. 5 is a schematic diagram of an embodiment of a second LDO body module of FIG. 2;

FIG. 6 is a schematic diagram of an embodiment of a gating module of FIG. 2;

FIG. 7 is a schematic diagram of an embodiment of the first protection module of FIG. 2;

FIG. 8 is a schematic diagram of an embodiment of a second protection module of FIG. 2;

FIG. 9 is a schematic diagram of an embodiment of the AMP of FIG. 4 or FIG. 5.

Detailed Description

The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.

Fig. 2 is a schematic diagram of an LDO circuit according to an embodiment of the present invention. As shown in fig. 2, the LDO circuit includes a reference module 001, a first LDO body module 002, a second LDO body module 003, a gating module 004, a first protection module 005, and a second protection module 006.

The reference module 001 has a first input terminal for inputting a first power USBIN, a second input terminal for inputting a second power OUT, and an output terminal connected to the first LDO main body module 002 and the second LDO main body module 003 for providing a bias voltage (HV _ BG).

The first LDO main body module 002 is used for internal power supply of the chip; second LDO body module 003 is used to power the chip interior.

The gating module 004 is used for judging a first power supply USBIN and a second power supply OUT, and when the first power supply USBIN is larger than the second power supply OUT, the first LDO main body module 002 is in a working state to supply power to the interior of the chip; when first power USBIN is less than second power OUT, second LDO main part module 002 is in operating condition and supplies power for the inside of the chip.

The first protection module 005 is used for detecting the inside of the first LDO main body module 002, and cutting off an internal signal of the first LDO main body module 002 when the first LDO main body module 002 detects a surge voltage, so as to protect the first LDO main body module 002; inside second protection module 006 is used for detecting second LDO main part module 003, when second LDO main part module 003 detects surge voltage, cut off second LDO main part module 003 internal signal, protect second LDO main part module 003.

According to a form of providing power to the LDO circuit, the LDO circuit further includes: and the power supply module comprises a first power supply and a second power supply which are used for providing power for the LDO circuit.

Fig. 3 is a schematic structural diagram of an embodiment of the reference module 001 in fig. 2. As shown in fig. 3, the reference module 001 includes power diodes D1 and D2, zener diode ZDIO, PMOS transistors P10 to P70, transistors Q1 to Q3, resistors R10 to R30, and NMOS transistors N1 to N2.

The anode of D1 is connected with a first power supply USBIN, the anode of D2 is connected with a second power supply OUT, and the common cathodes of D1 and D2 are marked as VDD _ BG; energy is gated to the reference block 001 at the USBIN, OUT terminals through D1, D2.

D1, wherein a common cathode of D2 is marked as VDD _ BG and is connected with the sources of high-voltage PMOS tubes P10-P70, the gate of P10 is connected with the gate and the drain of P50, the drain of P10 is connected with one end of R30 and is simultaneously connected with the gate and the drain of P20, and the other end of a resistor R30 is connected with a common reference ground; the gate of P30 is connected with the gate of P20, the drain of P30 is connected with the gate and the drain of N1; the grid of P40 is connected with the grid of P50, the drain of P40 is connected with the drain of N1, the source of N1 is connected with the emitter of triode Q1, and the base and the collector of triode Q1 are connected with a common reference ground; the grid and the drain of the P50 are connected with the drain of the N2, the source end of the N2 is connected with one end of the R10, the other end of the R10 is connected with the emitter of the triode Q2, and the base and the collector of the triode Q2 are connected with a common reference ground; the grid electrode of the P6 is connected with the grid electrode and the drain electrode of the P5 to form a current mirror relation with the P5, the drain electrode of the P60 is connected with one end of the R20, the other end of the R20 is connected with the emitter electrode of the triode Q3, and the base electrode and the collector electrode of the triode Q3 are connected with a common reference ground; the grid of the P70 is connected with the grid of the P50, forms a current mirror relation with the grid of the P50, and carries out current bias on other modules; the 20V Zener clamping tube ZDIO has a cathode connected with VDD _ BG and an anode connected with ground.

The transistor P10, the transistor P20, the transistor P30, and the resistor R3 constitute a start circuit. Since the core circuit (the self-bias structure formed by the transistor P40, the transistor P50, the transistor N1, the transistor N2, the resistor R10, the transistor Q1 and the transistor Q2) has two degenerate states, the first state is an operating state, the second state is a zero-current state in which the transistor P40, the transistor P50, the transistor N1 and the transistor N2 are all turned off, and the second state needs to be avoided; when the core circuit is in the second working state, no current exists in the transistor P10, the transistor P40, the transistor P50, the transistor P60 and the transistor P70, due to the existence of the zener ZDIO, a current exists in pair formed by the diode-connected transistor P20 and the resistor R30, since the transistor P20 and the transistor P30 are in a mirror image relationship, the transistor P30 mirrors the current of the transistor P20, the transistor P30 is turned on, the transistor N1 connected to the drain of the transistor P30 is also turned on, the transistor N2 mirrored to the transistor N1 is also turned on, and the gate and drain voltages of the transistor P50 connected to the drain of the transistor N2 are reduced due to the conduction of the transistor N2, so that the whole core circuit is turned on. The correct start-up of the start-up circuit is important for the proper operation of the core circuitry.

In order to isolate the operation between the startup circuit and the core circuit, the startup circuit operates only when the core circuit needs to be started, otherwise the startup circuit does not operate.

When the start-up circuit is operating, i.e. transistor P50 is also turned on, and transistor P10, which is a mirror image of transistor P50, is also turned on, to isolate the operation of the start-up circuit from the core circuit, transistor P10 is sized larger to pull the gate and drain node voltage of transistor P20 close to HV _ BG, thus turning off transistor P20 and transistor P30, and the start-up circuit does not affect the core circuit.

The core circuit (composed of a transistor P40, a transistor P50, a transistor N1, a transistor N2, a resistor R10, a transistor Q1 and a transistor Q2) generates a current proportional to the temperature through a transistor P40, a transistor P50, a transistor N1, a transistor N2, a transistor Q1, a transistor Q2 and a transistor R10; this current is the current of transistor P50, mirroring the current of transistor P50 through transistor P60, and causing the current of transistor P60 to flow through resistor R20 and diode-connected transistor Q3; it is made to obtain a reference voltage HV _ BG substantially independent of temperature and supply voltage, which is used to provide voltage to the first LDO body module 002 and the second LDO body module 003. The other output voltage (HV _ BIAS) of the reference block 001 is mirrored by the transistor P70 to mirror the current of the transistor P50, so as to provide a current BIAS to the LDO circuit, where P70(HV _ BIAS) may have several groups, only one group is shown in fig. 3.

The D1 and D2 are used as energy selection devices, energy supply can be supplied to a bias part no matter which source of the USBIN and the OUT is active, a starting circuit can ensure that a core circuit is separated from an unwanted degenerated state and enters a normal working state, a transistor P60, a resistor R20 and a triode Q3 form a voltage reference part, a transistor P70 forms a current reference part, and a 20V Zener diode ZDIO ensures the voltage of a VDD _ BG node, so that the power supply rejection of a band gap is improved in a safe and reasonable range.

The reference module 001 may also implement this solution by other circuits.

Fig. 4 is a schematic structural diagram of an embodiment of the first LDO body module 002 in fig. 2. As shown in fig. 4, the first LDO body module 002 includes an operational amplifier AMP1, a first adjusting transistor P1(PMOS), a compensation capacitor C1, and sampling voltage-dividing resistors R1 and R2.

The first operational amplifier AMP1 has a first input terminal connected to the output voltage (HV _ BG) of the reference module 001, a second input terminal connected to the connection point of the resistor R1 and the resistor R2, and an output terminal connected to the gate of the adjusting transistor P1 and one end of the compensation capacitor C1.

The source of the adjusting transistor P1 is connected to the first power USBIN, the drain of the adjusting transistor P1 is connected to one end of R2 and one end of the compensation capacitor C1, and the drain of the adjusting transistor P1 is the output end of the first LDO main body 002.

First LDO body module 002 is used to power the chip interior.

The first LDO body module 002 may also implement this solution by other circuits.

Fig. 5 is a schematic structural diagram of an embodiment of the second LDO body module 003 in fig. 2. As shown in fig. 5, the second LDO body module 003 has the same structure as the first LDO body module 002. Except that the source of the regulating tube P2 is connected to a second power supply OUT. First LDO main part module 002 and second LDO main part module 003 of looks isostructure can guarantee like this that whether first power USBIN and second power OUT insert, the LDO circuit can both provide required operating voltage for the chip.

The second LDO body module 003 can also implement this solution by other circuits.

Fig. 6 is a schematic structural diagram of an embodiment of the gating module 004 in fig. 2. As shown in fig. 6, the gating module 004 includes a hysteresis comparator COMP, an inverter NOT0, gating switching tubes P3, P4, and a bypass capacitor C3.

The first input end of the hysteresis comparator COMP is connected with the first power supply USBIN, the second input end is connected with the second power supply OUT, and the output end is connected with the input end of the inverter NOT0 and the gate of the switch tube P4.

The input end of the inverter NOT0 is connected to the output end of the hysteresis comparator and the gate of the switching tube P4, and the output end is connected to the gate of the switching tube P3.

The drain of the switch tube P3 is connected to the output VLDO _ USBIN of the first LDO body module 002, the source of the switch tube P3 is connected to one end of the bypass capacitor C3 and the source of the switch tube P4, and is labeled VDD 6V; the node VDD6V is the output terminal of the LDO circuit.

The drain of the switching tube P4 is connected to the output VLDO _ OUT of the second LDO body module 003.

The other end of the bypass capacitor C3 is connected to a common reference ground.

The gating module 004 is used for judging a first power supply USBIN and a second power supply OUT, when the first power supply USBIN is larger than the second power supply OUT, the switch tube P3 is cut off, the switch tube P4 is switched on, and the second LDO main body module 003 selects to supply power to the interior of the chip; when the first power supply USBIN is smaller than the second power supply OUT, the switching tube P3 is turned on, the switching tube P4 is turned off, and the first LDO main body module 002 selectively supplies power to the inside of the chip; the control switch tubes P3 and P4 are not conducted at the same time, so that a direct path between the voltage source USBIN and the voltage source OUT is avoided, and the output of the LDO is ensured to normally supply power to the chip.

The gating module 004 may also implement this solution by other circuits.

Fig. 7 is a schematic structural diagram of an embodiment of the first protection module 005 in fig. 2. As shown in fig. 7, the first protection module 005 includes a control transistor P5, a zener diode Z5, a resistor R5, a capacitor C5, a source of P5, and an R5.

The voltage of the Zener tube Z5 is 6V, the cathode of the Zener tube Z5 is connected with the first power supply USBIN, one end of the resistor R5 and the source of the P5; the anode of Zener tube Z5 is connected to the gate of P1 and one end of capacitor C5. The other end of C5 is connected to reference ground.

The drain of P5 is the output terminal of the first protection module 005 and is denoted as VC.

When the source of the control tube P5 detects a surge voltage, the control tube P5 is equivalent to a resistor with a smaller resistance, and further charges the gate of the adjustment tube P1 of the first LDO main module 002, thereby turning off the adjustment tube P1 and protecting the internal chip.

The first protection module 005 can also implement this solution by other circuits.

Fig. 8 is a schematic structural diagram of an embodiment of the second protection module 006 in fig. 2. As shown in fig. 8, the second protection module 006 includes a control transistor P6, a zener diode Z6, a resistor R6, a capacitor C6, a source of P6, and an R6.

The voltage of the Zener tube Z6 is 6V, the cathode of the Zener tube Z6 is connected with a second power supply OUT, one end of a resistor R6 and the source of the P6; the anode of Zener tube Z6 is connected to the gate of P6 and one end of capacitor C6. The other end of C6 is connected to reference ground.

The drain of P6 is the output terminal of the second protection module 006, denoted as VC.

When the source of the control tube P6 detects a surge voltage, the control tube P6 is equivalent to a resistor with a smaller resistance, and further charges the gate of the adjusting tube P2 of the second LDO main module 003, so as to turn off the adjusting tube P1 and protect the internal chip.

The second protection module 006 may also implement this technical solution through other circuits.

FIG. 9 is a schematic diagram of the structure of one embodiment of the AMP of FIG. 4 or FIG. 5. As shown in fig. 9, the AMP includes a transistor P100, a transistor P200, a transistor P300, a transistor P400, a transistor P500, a transistor N100, a transistor N200, a transistor N300, and a transistor N400.

The source of the transistor P100 is connected to VDD _ BG in fig. 3, the gate of the transistor P100 is connected to BIASP1, and the drain of the transistor P100 is connected to the source of the transistor P200 and the source of the transistor P300; the gate of the transistor P200 is connected to V +, and the drain of the transistor P200 is connected to the drain of the transistor N100 and the drain of the transistor N100; the gate of the transistor P300 is connected to HV _ BG in fig. 3, and the drain of the transistor P300 is connected to the source of the transistor N400 and the drain of the transistor N200; the source of the transistor P400 and the source of the transistor P500 of the AMP in the first LDO body module 002 are connected to the power supply USBIN, and the source of the transistor P400 and the source of the transistor P500 of the AMP in the second LDO body module 003 are connected to the power supply OUT; the gate and the drain of the transistor P400 are connected to the gate of the transistor P500 and the drain of the transistor N300; the drain of the transistor P500 is connected to the output terminal VOUT of AMP, the drain of the transistor N400, and one end of the capacitor C100; the gate of the transistor N300 is connected to the gate of the transistor N400; the gate of the transistor N100 is connected to the gate of the transistor N100; the source of the transistor N100 is connected to the source of the transistor N200, the other end of the capacitor C100, and "ground".

And during the operation of the AMP, the HV _ BG is connected with the grid electrode of the transistor P300 in the operational amplifier AMP, the feedback voltage is generated by the joint of the resistor R1 and the resistor R2, and when the sampling feedback voltage (the resistor R1 and the resistor R2 in the figure 4 are sampling voltage-dividing resistors, and the joint of the resistor R1 and the resistor R2 is a feedback voltage node) is smaller than the HV _ BG. Since P100 is a constant current source, when the feedback voltage is lower than the HV _ BG voltage, the source-gate voltage of P200 is greater than the source-gate voltage of P300, so the P200 current increases and the P300 current decreases. Since the transistors N100 and N200 are biased by constant current sources, the current of the transistor P400 is reduced, the transistors P500 and P400 are in a mirror relationship, the current of the transistor P500 is also reduced, the pull-down current of the transistor N200 is unchanged, the voltage of the VOUT node is reduced, the gate-source voltage of the regulating transistor P1 in the first LDO body module 002 (and the gate-source voltage of the regulating transistor P2 in the second LDO body module 003) is increased, the conduction capability is enhanced, the VDD6V is increased, and the FB voltage is increased; the reverse is true when the sampled feedback voltage is greater than HV _ BG.

Fig. 9 shows that the current-biased voltage of the input pair transistor is VDD _ BG outputted by the 001 module, and the folded portion (formed by the transistor P400, the transistor P500, the transistor N100, the transistor N200, the transistor N300, and the transistor N400) is used for adjusting the voltage sources USBIN and OUT to a power source suitable for the power supply of the LDO circuit, so that the transistors in the LDO circuit can work within a safe range and cannot be damaged by surge voltage generated under a severe condition.

When the power supply USBIN is high enough, the output voltage of the LDO is adjusted:

VLDO_USBIN＝HV_BG*(1+R2/R1)

when the operational voltage of the USBIN is low and the voltage satisfying the VLDO _ USBIN cannot be provided, the adjusting tube P1 is directly pulled into the linear region due to the high gain characteristic of the operational amplifier, so that only the voltage drop VDS _ P1 on the adjusting tube P1 is lost from the USBIN to the VLDO _ USBIN.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. An LDO circuit, comprising a first power supply and a second power supply for providing power to the LDO circuit, characterized in that the LDO circuit further comprises a first LDO main body module (002), a second LDO main body module (003) and a gating module (004);

the gating module (004) comprises two input ends, the two input ends are respectively connected with the first power supply and the second power supply, and the gating module (004) is used for supplying power to the inside of a chip from one selected from the first LDO main body module (002) and the second LDO main body module (003) according to the first power supply and the second power supply; the gating module (004) compares the first power supply with the second power supply, and when the first power supply is larger than the second power supply, the first LDO main body module (002) supplies power to the interior of a chip; when the value of the first power supply is smaller than that of the second power supply, the second LDO main body module (003) supplies power to the inside of a chip; the gating module (004) comprises: a Comparator (COMP), an inverter, a third transistor (P3), and a fourth transistor (P4);

a first input end of the Comparator (COMP) is connected with a first power supply, a second input end of the Comparator (COMP) is connected with a second power supply, and an output end of the Comparator (COMP) is connected with an input end of the inverter and a second end of the fourth transistor (P4); an output terminal of the inverter is connected to a second terminal of the third transistor (P3); a first terminal of the third transistor (P3) is connected with the first LDO body module (002), and a third terminal of the third transistor (P3) is connected with a third terminal of the fourth transistor (P4); a first terminal of the fourth transistor (P4) is connected with the second LDO body module (003);

when the value of the first power supply connected to the first input terminal of the Comparator (COMP) is greater than the value of the second power supply connected to the second input terminal of the Comparator (COMP), the third transistor (P3) is in an on state and the fourth transistor (P4) is in an off state; when the value of the first power supply at the first input terminal of the Comparator (COMP) is smaller than the value of the second power supply at the second input terminal of the Comparator (COMP), the third transistor (P3) is in an off state and the fourth transistor (P4) is in an on state; the first LDO body module (002) comprises: a first transistor (P1);

a second terminal of the first transistor (P1) is connected to the first power supply, and a third terminal of the first transistor (P1) is connected to a first terminal of the third transistor (P3);

when the value of the first power supply connected to the first input end of the Comparator (COMP) is greater than the value of the second power supply connected to the second input end of the Comparator (COMP), the third transistor (P3) is in a conducting state, so that the first end of the third transistor (P3) and the third end of the first transistor (P1) are connected, and the first LDO main body module (002) supplies power to the interior of the chip; the second LDO body module (003) includes: a second transistor (P2);

a second terminal of the second transistor (P2) is input to the second power supply, and a third terminal of the second transistor (P2) is connected to a first terminal of the fourth transistor (P4);

when the value of the first power supply connected with the first input end of the Comparator (COMP) is smaller than the value of the second power supply connected with the second input end of the comparator, the fourth transistor (P4) is in a conducting state, the first end of the fourth transistor (P4) is connected with the third end of the second transistor (P2), and then the second LDO main body module (003) supplies power to the interior of the chip;

further comprising: a first protection module (005);

the first protection module (005) is used for turning off the first LDO main body module (002) when detecting surge voltage; wherein,

the first protection module (005) comprises: a fifth transistor (P5), a fifth Zener diode (Z5), a fifth resistor (R5) and a fifth capacitor (C5);

a third terminal of the fifth transistor (P5) is connected with the first terminal of the first transistor (P1); a second terminal of the fifth transistor (P5), a first terminal of the fifth zener diode (Z5), and a first terminal of the fifth resistor (R5) are connected to each other; a first end of a fifth transistor (P5), a second end of a fifth Zener diode (Z5) and a second end of a fifth resistor (R5) are mutually connected and connected with a first end of a fifth capacitor (C5), and a second end of the fifth capacitor (C5) is grounded;

when the second end of the fifth transistor (P5) detects surge voltage, the fifth transistor (P5) charges the first end of the first transistor (P1) through the third end of the fifth transistor (P5), so that the first transistor (P1) is turned off, and an internal chip is protected;

further comprising: a second protection module (006);

the second protection module (006) is used for turning off the second LDO main body module (003) when detecting a surge voltage; wherein,

the second protection module (006) includes: a sixth transistor (P6), a sixth Zener diode (Z6), a sixth resistor (R6) and a sixth capacitor (C6); a third terminal of the sixth transistor (P6) is connected with the first terminal of the second transistor (P2); a second terminal of the sixth transistor (P6), a first terminal of the sixth zener diode (Z6), and a first terminal of the sixth resistor (R6) are connected to each other; a first end of a sixth transistor (P6), a second end of a sixth Zener diode (Z6) and a second end of a sixth resistor (R6) are mutually connected and connected with a first end of a sixth capacitor (C6), and a second end of the sixth capacitor (C6) is grounded;

when the second end of the sixth transistor (P6) detects surge voltage, the sixth transistor (P6) charges the first end of the second transistor (P2) through the third end of the sixth transistor (P6), so that the second transistor (P2) is turned off, and internal chips are protected.

2. The circuit of claim 1, further comprising a reference module (001);

the reference module (001) is configured to provide an operating voltage to the first LDO body module (002) and the second LDO body module (003).