CN114360613A - Method and device for controlling circuit voltage - Google Patents
Method and device for controlling circuit voltage Download PDFInfo
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Abstract
The invention relates to a method and a device for controlling circuit voltage, wherein the method comprises the following steps: the main LDO receives a read/write operation instruction of a control port, generates read/write voltage, marks the read/write voltage as a first signal, and outputs the first signal to the sub LDO; matching the module address configured according to the top layer code stream with the ID of the module to generate a module selection signal, and selecting the module according to the module selection signal; the LDO output voltage control signal selector selects the LDO output voltage control signal, and the selected LDO output voltage control signal is recorded as a read/write enable signal; the sub LDO provides a voltage to a circuit according to the first signal and the read/write enable signal. By the method for controlling the circuit voltage, the power supply voltage of the memory in different working modes can be changed, the writing operation is more reliable, the power consumption is reduced, and the speed can be increased by changing the power supply voltage in different working modes.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and more particularly, to a method and an apparatus for controlling a circuit voltage.
Background
The FPGA memory is distributed throughout the whole FPGA chip and is a storage unit with the largest number in the chip, and data in the storage unit control the configurable logic resources such as wiring resources and lookup tables. The normal operation of the memory requires the normal supply of voltage to the memory.
In the prior art, a voltage is allocated to all memories, and the modules in the memories are all at the same voltage. When one module can complete the required functions, the power consumption is obviously increased by supplying power to all the modules together, waste is caused, and the circuit cannot meet the characteristic of stably realizing the functions and improving the speed simultaneously due to the single power supply voltage of the memory.
Disclosure of Invention
In order to solve the above problems, the present application provides a method and an apparatus for controlling a circuit voltage.
In a first aspect, the present application provides a method of controlling a circuit voltage, the method comprising:
the main LDO receives a read/write operation instruction of a control port, records read/write voltage generated by the operation instruction as a first signal and outputs the first signal to the sub LDO;
matching the module address configured according to the top layer code stream with the ID of the module to generate a module selection signal, and selecting the module according to the module selection signal;
the LDO output voltage control signal selector selects the LDO output voltage control signal, and the selected LDO output voltage control signal is recorded as a read/write enable signal;
the sub LDO provides a voltage to a circuit according to the first signal and the read/write enable signal.
Preferably, the selection of the LDO output voltage control signal by the LDO output voltage control signal selector includes:
determining an LDO output voltage control signal according to the module selection signal.
Preferably, the method further comprises: the switching signal of the LDO is also present in the circuit;
the sub LDO providing a voltage to a circuit according to the first signal and the read/write enable signal comprises:
and when the switching signal of the LDO is not 0, the sub LDO provides voltage for the circuit according to the first signal and the read/write enable signal.
Preferably, the providing a voltage to the circuit module includes a write voltage or a read voltage.
Preferably, the write voltage is lower than the read voltage.
In a second aspect, the present application provides an apparatus for controlling a circuit voltage, comprising:
the first signal unit is used for generating a read/write voltage according to a read/write operation instruction of a control port received by the main LDO and recording the read/write voltage as a first signal, and outputting the first signal to the sub LDO through the main LDO and recording the first signal as the first signal;
the selection unit is used for matching the module address configured by the top layer code stream with the ID of the module to generate a module selection signal and selecting the module according to the module selection signal;
the second signal unit is used for selecting the LDO output voltage control signal according to the LDO output voltage control signal selector and recording the selected LDO output voltage control signal as a read/write enabling signal;
and the power supply unit is used for enabling the sub LDO to provide voltage for the circuit according to the first signal and the read/write enabling signal.
Preferably, the second signal unit is specifically configured to:
and determining the LDO output voltage control signal selector according to the module selection signal, and selecting the LDO output voltage control signal according to the LDO output voltage control signal selector.
Preferably, the apparatus further comprises: the judging unit is used for judging an LDO switching signal existing in the circuit;
the power supply unit is specifically configured to: when the judging unit judges that the LDO switching signal is not 0, the sub LDO provides voltage for the circuit according to the first signal and the read/write enabling signal.
Preferably, the providing a voltage to the circuit module includes a write voltage or a read voltage.
Preferably, the write voltage is lower than the read voltage.
By the method for controlling the circuit voltage, the power supply voltage in the circuit under different working modes can be changed, the writing operation is more reliable, the power consumption is reduced, and the speed can be increased by changing the power supply voltage under different working modes.
Description of attached books
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a module-based VC voltage distribution provided in an embodiment of the present application;
FIG. 2 is a schematic diagram of the VC voltage generation provided in the embodiments of the present application;
FIG. 3 is a schematic diagram of the internal logic of the VC voltage generation provided in the embodiment of the present application;
FIG. 4 is a schematic diagram of a method for controlling a memory voltage according to an embodiment of the present application:
FIG. 5 is a schematic diagram of VC timing provided in the present embodiment;
fig. 6 is a schematic diagram of the variation of the delay time with the VC voltage provided in the embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
For the convenience of understanding of the embodiments of the present invention, the following description will be further explained with reference to specific embodiments, which are not to be construed as limiting the embodiments of the present invention. Copies, and duplicates of a work described herein are intended to be synonymous and refer to duplicates of a work.
It should be noted that, in the present application, the method for controlling the circuit voltage is specifically described by taking the voltage of the memory as an example, and it is understood that the memory may be equivalently replaced by circuit components in other various possible service scenarios.
Fig. 1 is a schematic diagram of a block-based VC voltage distribution provided in an embodiment of the present application. As shown in fig. 1, the main LDO receives a read operation command from the control port to generate a read voltage, or the main LDO receives a write operation command from the control port to generate a write voltage. The read operation command is denoted as main _ ldo _ ctrl _ read, the write operation command is denoted as main _ ldo _ ctrl _ write, the read voltage is denoted as n _ read, and the write voltage is denoted as n _ write. And outputting the read voltage n _ read or the write voltage n _ write to a plurality of modules. Each of the plurality of modules determines whether the module is selected based on the module selection signal and the LDO switching signal, and the sub LDO provides the VC voltage to the selected module. The module is marked as block, the module selection signal is marked as bk _ sel, the LDO switch signal is marked as cfgmem _ LDO _ pdb, and the sub LDO is marked as subldo.
Fig. 2 is a schematic diagram of VC voltage generation provided in the embodiment of the present application. As shown in fig. 2, the main LDO receives a read operation command from the control port to generate a read voltage, or the main LDO receives a write operation command from the control port to generate a write voltage. And the module generates the VC voltage according to the bk _ sel, the LDO output voltage control signal and the reading voltage or the writing voltage. Let the LDO output voltage control signal be cfgmem _ LDO _ sel.
Fig. 3 is a schematic diagram of the internal logic of VC voltage generation provided in the embodiment of the present application. As shown in FIG. 3, the read/write enable signal is asserted from bk _ sel and cfgmem _ ldo _ sel, and is noted as read _ write _ en. Then, the read voltage n _ read or the write voltage n _ write is determined according to the read/write enable signal read _ write _ en. Then, the VC voltage is determined according to the determined read voltage n _ read or write voltage n _ write and the LDO switch signal cfgmem _ LDO _ pdb.
Fig. 4 is a schematic diagram of a method for controlling a memory voltage provided in an embodiment of the present application, and fig. 4 is further explained with reference to fig. 1, fig. 2, and fig. 3. As shown in fig. 4, the method of controlling the memory voltage includes:
s201: the main LDO receives a read/write operation instruction of the control port, generates a read/write voltage, marks the read/write voltage as a first signal, and outputs the first signal to the sub LDO.
Specifically, referring to fig. 2, when the first signal is a voltage generated by a read command, it is denoted as n _ read; when the first signal is a voltage generated by the write operation command control, it is recorded as n _ write.
S202: and matching the module address configured according to the top layer code stream with the ID of the module to generate a module selection signal, and selecting the module according to the module selection signal.
The VC voltage of the selected module can be read and written, and the VC voltage of the unselected module is kept unchanged.
Specifically, the module address is denoted by bk _ adr, and the module is denoted by block. For example, there are 4 blocks, the IDs of the 4 blocks may be respectively recorded as 00, 01, 10, and 11, the module selection signal may be obtained by comparing bk _ adr with the ID of the block, and whether the memory module is turned on is determined according to the module selection signal.
S203: the LDO output voltage control signal selector selects the LDO output voltage control signal, and the selected LDO output voltage control signal is recorded as a read/write enable signal.
In some possible embodiments, the LDO output voltage control signal selector selecting the LDO output voltage control signal comprises: determining an LDO output voltage control signal according to the module selection signal.
For example, referring to FIG. 3, in the present embodiment, the output voltage control signal selector is denoted as cfgmem _ ldo _ sel [1:0], and the read/write enable signal is denoted as read _ write _ en. When the block select signal bk _ sel is 1, cfgmem _ ldo _ sel [1] is selected; when the block select signal bk _ sel is 0, cfgmem _ ldo _ sel [0] is selected. The selected signal is labeled read _ write _ en.
The output voltage control signal selector cfgmem _ ldo _ sel [1:0] is 2 bits, and the specific value is configured by the top code stream.
Illustratively, ldo _ sel [1] is 1, ldo _ sel [0] is 0, noted as 10; ldo _ sel [1] is 0 and ldo _ sel [0] is 1, noted as 01.
S204: the sub LDO provides a voltage to a memory according to the first signal and the read/write enable signal.
In some possible embodiments, there is also a switching signal of the LDO in the method of controlling the memory voltage.
At this time, the step of providing the voltage to the memory by the sub LDO according to the first signal and the read/write enable signal specifically includes:
when the value of the switching signal of the LDO is not 0, the sub LDO provides voltage for the memory according to the first signal and the read/write enable signal.
In some possible embodiments, providing a voltage to the memory module includes a write voltage or a read voltage.
In a more specific example, the output voltage control signal selector cfgmem _ ldo _ sel [1:0] and a module selection signal bk _ sel are used together to select the value of VC from the write voltage output by the main LDO or the read voltage output by the main LDO, and for a specific truth table, refer to table 1. It should be understood that the truth table shown in table 1 is one of the embodiments of the present application, and other truth tables can be applied according to the design idea of the present application.
TABLE 1
| cfgmem_ldo_pdb | cfgmem_ldo_sel[1:0] | | VC | |
| 0 | | XX | 0 | |
| 1 | 00 | 0/1 | |
|
| 1 | 11 | 0/1 | |
|
| 1 | |
0 | |
|
| 1 | |
0 | |
|
| 1 | |
1 | |
|
| 1 | |
1 | VC_write |
In the table, X denotes: the value of X is arbitrary.
As shown in table 1, when the cfgmem _ ldo _ pdb value is 0, since the priority of the cfgmem _ ldo _ pdb is the highest, regardless of the subsequent cfgmem _ ldo _ sel [1:0] and bk _ sel, the value of VC is 0. VC takes a value when the cfgmem _ ldo _ pdb value is 1.
When the cfgmem _ ldo _ pdb value is 1, the voltage starts to power up. If the value of cfgmem _ LDO _ sel [1:0] is 00, the read/write enable signal read _ write _ en is 0 and VC is VC _ write at this time, which is determined by the write operation command of the main LDO.
If cfgmem _ ldo _ sel [1:0] is 11, the read _ write _ en signal is 1, VC is VC _ read, and is determined by the read command of the main LDO.
If bk _ sel has a value of 0, cfgmem _ ldo _ sel [0] is selected, and the value of VC is determined by cfgmem _ ldo _ sel [0 ].
If bk _ sel has a value of 1, cfgmem _ ldo _ sel [1] is selected, and the value of VC is determined by cfgmem _ ldo _ sel [1 ].
In some possible embodiments, the write voltage is lower than the read voltage.
For example, the value of VC at the time of writing is 0.8V, the value of VC at the time of reading is 1.3V, and the value of VC at the time of writing is lower than the value of VC at the time of reading.
Fig. 5 is a schematic diagram of VC timing provided in the embodiment of the present application. It is to be understood that the timing diagram of fig. 5 is one of the embodiments of the present application, and other timing diagrams may also be applied according to the design concept of the present application.
As shown in fig. 5, the main LDO write control port is denoted as main _ LDO _ ctrl _ write, the main LDO read control port is denoted as main _ LDO _ ctrl _ read, the LDO output voltage control signal is denoted as cfgmem _ LDO _ sel, the module address is denoted as bk _ adr, the memory initialization signal is denoted as initial _ cmc, the LDO switch signal is denoted as cfgmem _ LDO _ pdb, and the module select signal is denoted as bk _ sel. The starting stage is marked as initial stage, the configuration stage is marked as cfg stage, the user mode stage is marked as user mode, and the module restarting stage is marked as block _ re _ initial.
The address bk _ adr of a module is used to select the module and determine which module to configure the VC. The 1000 in the diagram indicates that the most significant bit of bk _ adr is 1, which means that all modules are selected and the VC voltage of all module memories needs to be configured. 0XXX in the diagram represents the highest bit being 0, indicating that only the selected module can be configured subsequently.
The cfgmem _ LDO _ pdb signal controls the switching of the sub-LDOs, starting after reset and after cfgmem _ LDO _ sel selection.
initial _ cmc clears the memory at the beginning and then signals the next configuration restart.
It will be appreciated that VC starts to rise during the initialization phase and then enters the configuration phase. The initialization stage and the configuration stage are both a memory writing process, and the VC voltage at the time can be lower than that in a user mode, so that the memory writing is facilitated and the power consumption is saved; in the reading stage, the VC voltage can be increased, so that the memory is convenient to read, the correctness of read data can be improved, and the circuit performance can be improved. Fig. 6 is a schematic diagram of the variation of the delay time with the VC voltage provided in the embodiment of the present application, where the delay time decreases with the increase of the VC voltage, and the higher the VC voltage, the lower the delay time. Referring to fig. 6, when in user mode, the VC voltage can be raised to increase the operating speed of the circuit. When restarting, the VC voltage is reduced to the lowest, and then the VC voltage is increased according to the module pair selected by bk _ adr.
By the method for controlling the voltage of the memory, the power supply voltage of the memory in different working modes can be changed, the writing operation is more reliable, the power consumption is reduced, and the speed can be increased by changing the power supply voltage in different working modes.
Based on the method for controlling the memory voltage provided in the foregoing embodiment, an apparatus for controlling the memory voltage is also provided in this embodiment, and the apparatus for generating a copy right of a work, provided in this embodiment, may include:
and the first signal unit is used for recording a read/write voltage generated according to a read/write operation instruction of the control port received by the main LDO as a first signal and outputting the first signal to the sub LDO through the main LDO.
And the selection unit is used for matching the module address configured by the top layer code stream with the ID of the module to generate a module selection signal and selecting the module according to the module selection signal.
And the second signal unit is used for selecting the LDO output voltage control signal according to the LDO output voltage control signal selector and recording the selected LDO output voltage control signal as a read/write enable signal.
In some possible embodiments, the second signal unit is specifically configured to:
and determining the LDO output voltage control signal selector according to the module selection signal, and selecting the LDO output voltage control signal according to the LDO output voltage control signal selector.
And the power supply unit is used for enabling the sub LDOs to provide voltage for the memory module according to the first signal and the read/write enabling signal.
In some possible embodiments, the apparatus further comprises:
and the judging unit is used for judging the LDO switching signal existing in the circuit.
The power supply unit is specifically configured to:
and when the judging unit judges that the LDO switching signal is not 0, the sub LDO supplies voltage to the memory module according to the first signal and the read/write enabling signal.
In some possible embodiments, providing a voltage to the memory module includes a write voltage or a read voltage.
In some possible embodiments, the write voltage is lower than the read voltage.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above embodiments are provided to further explain the objects, technical solutions and advantages of the present invention in detail, it should be understood that the above embodiments are merely exemplary embodiments of the present invention and are not intended to limit the scope of the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method of controlling a circuit voltage, the method comprising:
the main LDO receives a read/write operation instruction of a control port, generates read/write voltage, marks the read/write voltage as a first signal, and outputs the first signal to the sub LDO;
matching the module address configured according to the top layer code stream with the ID of the module to generate a module selection signal, and selecting the module according to the module selection signal;
the LDO output voltage control signal selector selects the LDO output voltage control signal, and the selected LDO output voltage control signal is recorded as a read/write enable signal;
the sub LDO provides a voltage to a circuit according to the first signal and the read/write enable signal.
2. The method of claim 1, wherein the LDO output voltage control signal selector selecting the LDO output voltage control signal comprises:
and determining the LDO output voltage control signal selector according to the module selection signal, and selecting the LDO output voltage control signal according to the LDO output voltage control signal selector.
3. The method of claim 1, further comprising:
the switching signal of the LDO is also present in the circuit;
the sub LDO providing a voltage to a circuit according to the first signal and the read/write enable signal comprises:
and when the switching signal of the LDO is not 0, the sub LDO provides voltage for the circuit according to the first signal and the read/write enable signal.
4. The method of claim 1 or 3, wherein the providing a voltage to the circuit comprises a write voltage or a read voltage.
5. The method of claim 4, wherein the write voltage is lower than the read voltage.
6. An apparatus for controlling a voltage of a circuit, the apparatus comprising:
the first signal unit is used for generating a read/write voltage according to a read/write operation instruction of a control port received by the main LDO and recording the read/write voltage as a first signal, and outputting the first signal to the sub LDO through the main LDO;
the selection unit is used for matching the module address configured by the top layer code stream with the ID of the module to generate a module selection signal and selecting the module according to the module selection signal;
the second signal unit is used for selecting the LDO output voltage control signal according to the LDO output voltage control signal selector and recording the selected LDO output voltage control signal as a read/write enabling signal;
and the power supply unit is used for enabling the sub LDO to provide voltage for the circuit according to the first signal and the read/write enabling signal.
7. The apparatus of claim 6, wherein the second signal unit is specifically configured to:
and determining the LDO output voltage control signal selector according to the module selection signal, and selecting the LDO output voltage control signal according to the LDO output voltage control signal selector.
8. The apparatus of claim 6, further comprising:
the judging unit is used for judging an LDO switching signal existing in the circuit;
the power supply unit is specifically configured to:
when the judging unit judges that the LDO switching signal is not 0, the sub LDO provides voltage for the circuit according to the first signal and the read/write enabling signal.
9. The apparatus of claim 6 or 8, wherein the providing a voltage to the circuit comprises a write voltage or a read voltage.
10. The apparatus of claim 9, wherein the write voltage is lower than the read voltage.
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| US20100103760A1 (en) * | 2008-02-05 | 2010-04-29 | Mair Hugh T | Memory Power Management Systems and Methods |
| CN105900036A (en) * | 2014-01-09 | 2016-08-24 | 高通股份有限公司 | Charge sharing linear voltage regulator |
| CN106385100A (en) * | 2016-09-18 | 2017-02-08 | 英特格灵芯片(天津)有限公司 | Ldo circuit |
| CN108469860A (en) * | 2018-05-07 | 2018-08-31 | 武汉新芯集成电路制造有限公司 | Low pressure difference linear voltage regulator module |
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2021
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100103760A1 (en) * | 2008-02-05 | 2010-04-29 | Mair Hugh T | Memory Power Management Systems and Methods |
| US20090284246A1 (en) * | 2008-05-16 | 2009-11-19 | Ranjit Kumar Dash | Low dropout regulator testing system and device |
| CN105900036A (en) * | 2014-01-09 | 2016-08-24 | 高通股份有限公司 | Charge sharing linear voltage regulator |
| CN106385100A (en) * | 2016-09-18 | 2017-02-08 | 英特格灵芯片(天津)有限公司 | Ldo circuit |
| CN108469860A (en) * | 2018-05-07 | 2018-08-31 | 武汉新芯集成电路制造有限公司 | Low pressure difference linear voltage regulator module |
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