CN109740275B - Reconfiguration circuit of integrated circuit and method thereof - Google Patents
Reconfiguration circuit of integrated circuit and method thereof Download PDFInfo
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- CN109740275B CN109740275B CN201910023922.7A CN201910023922A CN109740275B CN 109740275 B CN109740275 B CN 109740275B CN 201910023922 A CN201910023922 A CN 201910023922A CN 109740275 B CN109740275 B CN 109740275B
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Abstract
The application relates to the field of integrated circuits and discloses a reconfiguration circuit of an integrated circuit and a method thereof. After the system enters a user mode, a user logic module outputs a reconfiguration signal according to a reconfiguration requirement, a reconfiguration selection logic module outputs a reconfiguration control signal according to the reconfiguration signal, a multi-channel configuration code stream configuration register module outputs reconfiguration code stream information according to the reconfiguration signal, a flash memory reading control logic module reads reconfiguration data from a flash memory according to the reconfiguration control signal and the reconfiguration code stream information, and a configuration logic module configures the reconfiguration data into the integrated circuit to realize reconfiguration of the integrated circuit. The circuit and the method can automatically select a new configuration code stream according to the system requirement to reconfigure the integrated circuit to realize new functions when the integrated circuit works normally, and greatly increases the flexibility and the multifunctionality of the system design.
Description
Technical Field
The present disclosure relates to the field of integrated circuits, and more particularly, to a reconfiguration circuit for an integrated circuit and a method thereof.
Background
As systems become more complex, designers are demanding more things with as little cost as possible, and FPGAs, for example, while having much flexibility, increasingly demanding cost, circuit board space and power consumption constraints require more efficient design strategies. However, in the existing FPGA system, only one configuration code stream is often stored in a configuration memory, or a function of updating an original configuration code stream is provided in a higher-level system, but a new function is started only by externally triggering and downloading again, which not only increases the design cost of the system, but also affects the stability of the system.
If the FPGA can be used, a certain configuration file can be intelligently selected and loaded to realize a certain specific function, so that the design flexibility of the FPGA is greatly increased, and different function dynamic switching functions can be realized in the same system (such as a circuit board).
In circuit board design, most FPGA systems adopt SPI Nor Flash as a configuration memory, and as memory storage is larger and cost is cheaper, a plurality of design configuration files can be placed in the configuration memory, so that reconfiguration is possible.
Disclosure of Invention
The present invention provides a reconfiguration circuit of an integrated circuit and a method thereof, which can automatically select a new configuration code stream to reconfigure the integrated circuit according to the system requirement when the integrated circuit works normally so as to realize new functions, thereby greatly increasing the flexibility and the versatility of the system design.
In order to solve the above-mentioned problem, the present application discloses a configuration logic module circuit of an integrated circuit, comprising:
the user logic module is used for outputting a reconfiguration signal according to the reconfiguration requirement;
a reconfiguration selection logic module coupled to the user logic module for outputting a reconfiguration control signal according to the reconfiguration signal, the reconfiguration control signal including a clock and a control command;
the multi-path configuration code stream configuration register module is coupled with the reconfiguration selection logic module and is used for outputting information of the reconfiguration code stream according to the reconfiguration signal;
the flash memory reading control logic module is coupled with the multi-path configuration code stream configuration register module and is used for reading reconfiguration data from a flash memory (flash) according to the reconfiguration control signal and the information of the reconfiguration code stream;
and the configuration logic module is respectively coupled with the flash memory read control logic module and the user logic module and is used for configuring the reconfiguration data into the integrated circuit so as to realize the reconfiguration of the integrated circuit.
In a preferred embodiment, the method further comprises:
the configuration code stream configuration register module is respectively coupled with the multi-path configuration code stream configuration register module and the flash memory reading control logic module and is used for reading the reconfiguration control signal and the reconfiguration code stream information from a default address of the flash memory when the system is powered on again;
the multiplexer comprises a first input end, a second input end, a control end and an output end, wherein the first input end is coupled with the multi-path configuration code stream configuration register module, the second input end is coupled with the power-on configuration code stream configuration register module, the control end is coupled with the reconfiguration selection logic module, and the output end is coupled with the flash memory reading control logic module;
and the power-on checking module is coupled with the power-on configuration code stream configuration register module and is used for determining whether to start the integrated circuit by checking whether the power supply voltage is normal.
In a preferred embodiment, the user logic module stores a function list in advance, and after a certain function option is selected from the function list, the reconfiguration selection logic module is started by decoding to generate the reconfiguration control signal, and the decoded information is input into the multi-path configuration code stream configuration register module to select the information of the reconfiguration code stream, wherein the function list is read from the flash memory without an external trigger signal when the integrated circuit is powered on.
In a preferred embodiment, the information of the reconfiguration code stream includes information of recording the position and size information of the reconfiguration code stream and the data integrity cyclic redundancy check in the flash memory;
in the process of configuring the reconfiguration data into the integrated circuit, the integrated circuit dynamically calculates a cyclic redundancy check value through a data integrity algorithm and compares the cyclic redundancy check value with the cyclic redundancy check value stored in the multi-path configuration code stream configuration register module or the configuration code stream configuration register module during power-on so as to judge whether error data are read in the configuration process.
In a preferred embodiment, the flash memory comprises serial nonvolatile flash memory.
In a preferred embodiment, the control signal further includes a selection of a clock frequency, a selection of a clock edge, and a command to read and write the flash memory.
In a preferred embodiment, the circuit is adapted for use in a design comprising at least programmable logic and application specific integrated circuits.
In a preferred embodiment, the user logic module is configured to implement the user's working logic.
The application also discloses a reconfiguration method of the integrated circuit, which comprises the following steps:
after the system enters a user mode, a reconfiguration signal is output according to the reconfiguration requirement of the user logic module;
outputting a reconfiguration control signal according to the reconfiguration signal, wherein the reconfiguration control signal includes a clock and a control command;
outputting information of a reconfiguration code stream according to the reconfiguration signal;
reading reconfiguration data from the flash memory according to the reconfiguration control signal and the reconfiguration code stream information;
the reconfiguration data is configured into the integrated circuit to effect reconfiguration of the integrated circuit.
In a preferred embodiment, the information of the reconfiguration code stream includes recording the position and size information of the reconfiguration code stream in the flash memory;
after selecting the information of the reconfiguration code stream according to the reconfiguration signal, the method further comprises: and storing the information of the code stream into a default address of the flash memory.
The application also discloses a computer readable storage medium having stored therein computer executable instructions which when executed by a processor implement the steps in the method as described hereinbefore.
In this embodiment, at least the following advantages are included:
(1) When a system (such as a circuit system containing an FPGA) works normally, a new configuration code stream is automatically selected according to the system requirement to reconfigure to realize a new function, so that the flexibility and the versatility of the system design are greatly improved;
(2) When the system is powered on again, because the information in the power-on configuration register is stored in the flash memory, the system can be ensured to work from the latest configuration after the power-on;
(3) The system has the advantages that the system has multiple functions, different functions can be realized by the integrated circuits (such as the FPGA) on the same circuit board, the flexibility of deployment is improved, and the functions can be dynamically switched when the system is started and operated by a user.
(4) The reconfiguration during normal operation of the system and the reconfiguration during the power-up of the system do not necessarily need to provide reconfiguration signals from outside, so that the system is more reliable and intelligent;
(5) The multi-functional characteristic that only large-scale integrated circuit system can be realized by small-and medium-scale integrated circuit system, and the design cost is reduced, thereby saving the economic cost of purchasing chips and system design for users.
In the present application, a number of technical features are described in the specification, and are distributed in each technical solution, which makes the specification too lengthy if all possible combinations of technical features (i.e. technical solutions) of the present application are to be listed. In order to avoid this problem, the technical features disclosed in the above summary of the present application, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (these technical solutions are all regarded as being already described in the present specification) unless such a combination of technical features is technically impossible. For example, in one example, feature a+b+c is disclosed, in another example, feature a+b+d+e is disclosed, and features C and D are equivalent technical means that perform the same function, technically only by alternative use, and may not be adopted simultaneously, feature E may be technically combined with feature C, and then the solution of a+b+c+d should not be considered as already described because of technical impossibility, and the solution of a+b+c+e should be considered as already described.
Drawings
FIG. 1 is a schematic diagram of a reconfiguration circuit configuration of an integrated circuit according to a first embodiment of the present application
FIG. 2 is a flow chart of a method for reconfiguring an integrated circuit according to a second embodiment of the present application
FIG. 3 is a schematic structural view of an example according to the first embodiment of the present application
FIG. 4 is a timing diagram of an interface of a reconfiguration select logic module in x1 mode according to one embodiment of the first embodiment of the present application
Wherein, the liquid crystal display device comprises a liquid crystal display device,
101-user logic module 102-reassortment selection logic module
103-multiple configuration code stream configuration register module 104-flash read control logic module
105-configuration logic module 106-configuration code stream configuration register module at power-up
107-multiplexer 108-power-on inspection module
109-first input 110-second input
111-control terminal 112-output terminal
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be understood by those skilled in the art that the claimed invention may be practiced without these specific details and with various changes and modifications from the embodiments that follow.
Description of the partial concepts:
field programmable gate array: field-Programmable Gate Array, FPGA for short.
Cyclic redundancy check: cyclic Redundancy Check, CRC for short.
Serial peripheral interface: serial Peripheral Interface, SPI for short.
Nor Flash: a nonvolatile flash memory.
Flash: and (3) a flash memory.
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
The first embodiment of the present application relates to a reconfiguration circuit of an integrated circuit, whose structure is shown in fig. 1, where the reconfiguration circuit of the integrated circuit includes a user logic module 101, a reconfiguration selection logic module 102, a multi-configuration code stream configuration register module 103, a flash read control logic module 104, and a configuration logic module 105.
Optionally, the reconfiguration circuit of the integrated circuit further includes a power-up checking module 108, a multiplexer 107 and a power-up configuration code stream configuration register module 106.
Optionally, the reconfiguration circuitry of the integrated circuit is adapted for use in a design comprising at least programmable logic circuitry and application specific integrated circuits.
After the system enters the user mode, if the user logic module 101 has a reconfiguration requirement, the reconfiguration selection logic module 102 is started through decoding to output a reconfiguration control signal (including a clock, a control command and the like), and the decoded information is input into the multi-path configuration code stream configuration register module 103 to select the information of the reconfiguration code stream; then the first input 109 of the multiplexer 107 is gated, then the flash memory read control logic module 104 reads the reconfiguration code stream in the flash memory according to the input reconfiguration control signal and the information of the reconfiguration code stream, and finally the configuration logic module 105 configures the read reconfiguration code stream into the integrated circuit to ensure that a new configuration code stream is automatically selected to be reconfigured according to the requirement in the normal operation of the system to realize a new function;
after the system is powered up again, the second input 110 of the multiplexer 107 is gated, the latest reconfiguration control signal and the reconfiguration code stream information are read from the default address of the flash memory and loaded into the configuration code stream configuration register module 106 when the system is powered up, then the flash memory reading control logic module 104 reads the reconfiguration code stream in the flash memory according to the input reconfiguration control signal and the reconfiguration code stream information, and finally the configuration logic module 105 configures the read reconfiguration code stream into the integrated circuit, so that the power up can be ensured to be started from the latest configuration.
Specific:
(1) The user logic module 101 is configured to output a reconfiguration signal according to a reconfiguration requirement.
Optionally, a function list is pre-stored in the user logic module 101, and after a certain function option is selected from the function list, the reconfiguration selection logic module 102 is started by decoding to generate the reconfiguration control signal, and the decoded information is input into the multi-configuration code stream configuration register module 103 to select the information of the reconfiguration code stream. In one embodiment, the user logic module 101 is used to implement the functions required by the user (i.e., user logic).
Optionally, the user logic module 101 is configured to implement user's working logic, where the user's working logic refers to FPGA functions that the user is using.
Optionally, the list of functions is read from the flash memory without an external trigger signal at system power-up.
(2) A reconfiguration selection logic module 102, coupled to the user logic module 101, for outputting a reconfiguration control signal according to a reconfiguration signal input from the user logic module 101, the reconfiguration control signal including a clock and a control command.
Alternatively, the reconfiguration selection logic module 102 is a configurable control circuit, and the reconfiguration selection logic module 102 selects and outputs the reconfiguration control signal according to the reconfiguration signal input from the user logic module 101. In one embodiment, the function of the reconfiguration selection logic module 102 is implemented by a table look-up method, specifically, the reconfiguration selection logic module 102 predefines a configuration table of a plurality of reconfiguration control signals, and the reconfiguration selection logic module 102 selects and outputs a desired reconfiguration control signal from the configuration table according to the reconfiguration signal input from the user logic module 101.
Optionally, the reconfiguration control signal further includes a clock frequency, clock edges, bit widths of the read-write flash memory, and the like.
The reconfiguration select logic module of the present application may, but is not limited to, generate flash read/write control signals that are x1, x2, and x4 bits wide.
Fig. 3 is a schematic structural view of an example according to the first embodiment of the present application; fig. 3 shows a read-write control signal of SPI x1 generated by the flash interface.
Fig. 4 is an interface timing diagram of a reconfiguration select logic module in x1 mode according to an embodiment of the first embodiment of the present application.
(3) The multi-path configuration code stream configuration register module 103 is coupled to the reconfiguration selection logic module 102 and is configured to output information of the reconfiguration code stream according to the reconfiguration signal input from the user logic module 101.
Optionally, the multi-way configuration code stream configuration register module 103 records information of different reconfiguration code streams in the flash memory, and the information of the different reconfiguration code streams is automatically read from the flash memory after the system is started.
Alternatively, the multi-way configuration stream configuration register module 103 may enable reloading without external triggers by decoding the input from the user logic module 101 and selecting the information of the new reconfiguration stream.
Optionally, the multi-configuration bitstream configuration register module 103 further includes a control register module for storing the control signals input from the reconfiguration selection logic module 102.
The multi-path configuration code stream configuration register module 103 can also change the reconfiguration control signals and the reconfiguration code stream information in the configuration code stream configuration register module 106 when power is on according to the requirement; alternatively, if the multi-path configuration code stream configuration register module 103 generates new reconfiguration code stream information and inputs a new reconfiguration control signal, the new reconfiguration code stream information and the new reconfiguration control signal are stored to the power-on configuration code stream configuration register module 106.
The information of the reconfiguration code stream is various, optionally, the information of the reconfiguration code stream includes recording the position and size information of the reconfiguration code stream in the flash memory; optionally, the information of the reconfiguration bitstream further includes data integrity Cyclic Redundancy Check (CRC) information.
(4) The flash memory read control logic module 104 is coupled to the multi-path configuration code stream configuration register module 103, and is configured to read reconfiguration data from the flash memory according to the reconfiguration control signal and the reconfiguration code stream information.
Optionally, the flash read control logic 104 may implement the reading and writing of data in the flash memory according to different commands, where the commands include reconfiguration control signals and reconfiguration code stream information.
The flash memory is of a variety of types, alternatively the flash memory may be a serial non-volatile flash memory; the flash memory may be a parallel nonvolatile flash memory.
(5) The configuration logic module 105 is coupled to the flash read control logic module 104 and the user logic module 101, respectively, and is configured to configure the reconfiguration data read by the flash read control logic module 104 into the integrated circuit, so as to implement the reconfiguration of the integrated circuit.
Optionally, the configuration logic module 105 configures the reconfiguration data read by the flash read control logic module 104 into an integrated circuit, and the integrated circuit dynamically calculates a cyclic redundancy check value through a data integrity algorithm and compares the cyclic redundancy check value with the cyclic redundancy check value stored in the multi-path configuration code stream configuration register module 103 or the configuration code stream configuration register module 106 at power-up to determine whether error data is read in during the configuration process.
(6) The configuration code stream configuration register module 106 at power-on is coupled with the multi-path configuration code stream configuration register module 103 and the flash memory read control logic module 104, respectively, and is used for reading the reconfiguration control signal and the reconfiguration code stream information from the default address of the flash memory at the time of system re-power-on, and loading the reconfiguration control signal and the reconfiguration code stream information into the configuration code stream configuration register module 106 at power-on.
Optionally, the configuration code stream configuration register module 106 further includes a start address register for storing information of the reconfiguration code stream and a control register for storing a reconfiguration control signal.
Optionally, the configuration code stream configuration register module 106 stores the reconfiguration control signal and the reconfiguration code stream information input from the multi-path configuration code stream configuration register module 103 into a default address of the flash memory, and when the integrated circuit is powered up again, the information of the code stream is read in from the flash memory again and the integrated circuit is controlled to start working from the latest configuration according to the code stream information.
(7) A multiplexer 107 comprising a first input 109, a second input 110, a control 111 and an output 112; the control terminal 111 is coupled to the reconfiguration selection logic, the first input terminal 109 is coupled to the multi-configuration code stream configuration register module 103, the second input terminal 110 is coupled to the configuration code stream configuration register module 106 when powered on, the output terminal 112 is coupled to the flash read control logic module 104, and the multiplexer 107 is used for determining whether the reconfiguration control signal and the information of the reconfiguration code stream are outputted by the configuration code stream configuration register module when powered on or outputted by the multi-configuration code stream configuration register module.
(8) The power-up checking module 108 is coupled to the power-up configuration code stream configuration register module 106, and is configured to determine whether to start the whole system by checking whether the power supply voltage is normal.
The "system" referred to in the present application is a circuit system including both the "flash memory" and the "integrated circuit (including the reconfiguration circuit of the first embodiment)".
A second embodiment of the present application relates to a reconfiguration method of an integrated circuit, the flow of which is shown in fig. 2, the method comprising the steps of:
initially, step 201 is performed: and after the system enters the user mode, outputting a reconfiguration signal according to the reconfiguration requirement of the user logic module.
Optionally, a function list is pre-stored in the user logic module, and after a certain function option is selected from the function list, the reconfiguration selection logic module is started by decoding to generate the reconfiguration control signal, and the decoded information is input into the multi-path configuration code stream configuration register module to select the information of the reconfiguration code stream, wherein the function list is read from the flash memory without an external trigger signal when the integrated circuit is powered on.
Thereafter, step 202 is performed: a reconfiguration control signal is output according to the reconfiguration signal in step 201, the reconfiguration control signal including a clock and a control command.
Optionally, the reconfiguration control signal further includes a clock frequency, a clock edge, a bit width of the read-write flash memory, and the like; the reconfiguration select logic module of the present application may, but is not limited to, generate flash read/write control signals that are x1, x2, and x4 bits wide.
Thereafter, step 203 is performed: and outputting information of the reconfiguration code stream according to the reconfiguration signal in step 201.
The information of the reconfiguration code stream is various, optionally, the information of the reconfiguration code stream includes recording the position and size information of the reconfiguration code stream in the flash memory; optionally, the information of the reconfiguration bitstream further includes data integrity Cyclic Redundancy Check (CRC) information.
Optionally, the information of the reconfiguration stream is obtained by decoding an input of the user logic.
Optionally, after step 203, step 206 is further included: the reconfiguration control signal in step 202 and the information of the reconfiguration stream selected in step 203 are stored in a default address of the flash memory.
Thereafter, step 204 is performed: the reconfiguration data is read from the flash memory according to the reconfiguration control signal selected in step 202 and the information of the reconfiguration stream selected in step 203.
Optionally, the flash memory read control logic module implements reading and writing of data in the flash memory according to different commands, where the different commands further include different reconfiguration control signals and information of the reconfiguration code stream.
The flash memory is of a variety of types, alternatively the flash memory may be a serial non-volatile flash memory; the flash memory may be a parallel nonvolatile flash memory.
Finally, step 205 is performed: the reconfiguration data read in step 204 is configured into the integrated circuit to effect reconfiguration of the integrated circuit.
Optionally, in executing step 205, the integrated circuit dynamically calculates a cyclic redundancy check value by a data integrity algorithm and compares the cyclic redundancy check value with the data integrity check value in step 203 to determine whether there is an erroneous data read in during the configuration process.
Optionally, the method further comprises: step 207, step 208; wherein, step 207: confirming that the system is powered up again; step 208: re-reading the reconfiguration control signal and the reconfiguration code stream information from the default address of the flash memory; step 204 and step 205 are then performed.
It should be noted that, the steps 207 and 208 are applicable to the case of powering up the system again.
Optionally, the reconfiguration method of the integrated circuit is applicable to designs including at least programmable logic circuits and application specific integrated circuits.
The present embodiment is a method embodiment corresponding to the first embodiment, and the technical details in the first embodiment can be applied to the present embodiment, and the technical details in the present embodiment can also be applied to the first embodiment.
Accordingly, embodiments of the present application also provide a computer-readable storage medium having stored therein computer-executable instructions which, when executed by a processor, implement the method embodiments of the present application. Computer-readable storage media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable storage media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.
It should be noted that in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements. Multiple, etc. expressions include 2, 2 times, 2, and 2 or more, 2 or more times, 2 or more.
All documents mentioned in the present application are considered to be included in the disclosure of the present application in their entirety, so that they may be subject to modification if necessary. Furthermore, it should be understood that the foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, or the like, which is within the spirit and principles of one or more embodiments of the present disclosure, is intended to be included within the scope of one or more embodiments of the present disclosure.
Claims (9)
1. A reconfiguration circuit for an integrated circuit, comprising:
the user logic module is used for outputting a reconfiguration signal according to the reconfiguration requirement;
a reconfiguration selection logic module coupled to the user logic module for outputting a reconfiguration control signal according to the reconfiguration signal, the reconfiguration control signal including a clock and a control command;
a multi-path configuration code stream configuration register module, coupled to the reconfiguration selection logic module, for outputting information of a reconfiguration code stream including information of a position and a size of the reconfiguration code stream recorded in the flash memory according to the reconfiguration signal, storing the reconfiguration control signal and the information of the reconfiguration code stream into a default address of the flash memory, and if the integrated circuit is powered on again, re-reading the reconfiguration control signal and the information of the reconfiguration code stream from the default address of the flash memory and controlling the integrated circuit to start working from the latest configuration according to the reconfiguration control signal and the information of the reconfiguration code stream;
the flash memory reading control logic module is coupled with the multi-path configuration code stream configuration register module and is used for reading reconfiguration data from the flash memory according to the reconfiguration control signals and the information of the reconfiguration code stream;
and the configuration logic module is respectively coupled with the flash memory read control logic module and the user logic module and is used for configuring the reconfiguration data into the integrated circuit so as to realize the reconfiguration of the integrated circuit.
2. The reconfiguration circuit according to claim 1, further comprising:
the configuration code stream configuration register module is respectively coupled with the multi-path configuration code stream configuration register module and the flash memory read control logic module and is used for loading reconfiguration control signals and reconfiguration code stream information from a default address of the flash memory when the system is powered on again;
the multiplexer comprises a first input end, a second input end, a control end and an output end, wherein the first input end is coupled with the multi-path configuration code stream configuration register module, the second input end is coupled with the power-on configuration code stream configuration register module, the control end is coupled with the reconfiguration selection logic module, and the output end is coupled with the flash memory read control logic module;
and the power-on checking module is coupled with the power-on configuration code stream configuration register module and is used for checking whether the power supply voltage is normal or not so as to determine whether to start the integrated circuit.
3. The reconfiguration circuit of claim 1 wherein the subscriber logic module pre-stores a list of functions, the reconfiguration select logic module is enabled by decoding to generate the reconfiguration control signal when a function option is selected from the list of functions, and the decoded information is input to the multi-way configuration code stream configuration register module to select the reconfiguration code stream information, wherein the list of functions is read from the flash memory without an external trigger signal after the integrated circuit is powered up.
4. The reconfiguration circuit according to claim 2, wherein the information of the reconfiguration stream includes information that records the position and size information of the reconfiguration stream and the data integrity cyclic redundancy check in the flash memory;
and the configuration logic module dynamically calculates a cyclic redundancy check value through a data integrity algorithm in the process of configuring the reconfiguration data into the integrated circuit, and compares the cyclic redundancy check value with the cyclic redundancy check value stored in the multi-path configuration code stream configuration register module or the configuration code stream configuration register module during power-on so as to judge whether error data are read in the configuration process.
5. The reconfiguration circuit of claim 2, wherein the flash memory comprises a serial nonvolatile flash memory.
6. The reconfiguration circuit of claim 1, wherein the control signals further include a selection of a clock frequency, a selection of a clock edge, and a command to read and write the flash memory.
7. The reconfiguration circuit according to any one of claims 1 to 6, wherein the reconfiguration circuit is adapted for use in a design including at least a programmable logic circuit and an application specific integrated circuit.
8. A method of reconfiguring an integrated circuit, comprising:
after the system enters a user mode, a reconfiguration signal is output according to the reconfiguration requirement of the user logic module;
outputting a reconfiguration control signal according to the reconfiguration signal, wherein the reconfiguration control signal comprises a clock and a control command;
outputting information of reconfiguration code stream according to the reconfiguration signal;
reading reconfiguration data from the flash memory according to the reconfiguration control signal and the reconfiguration code stream information;
configuring the reconfiguration data into the integrated circuit to effect reconfiguration of the integrated circuit; the information of the reconfiguration code stream comprises the position and size information of the reconfiguration code stream recorded in the flash memory;
after the information of the reconfiguration code stream is selected according to the reconfiguration signal, the method further comprises the following steps: and storing the reconfiguration control signal and the information of the reconfiguration code stream into a default address of the flash memory, and if the integrated circuit is powered on again, re-reading the reconfiguration control signal and the information of the reconfiguration code stream from the default address of the flash memory and controlling the integrated circuit to start working from the latest configuration according to the reconfiguration control signal and the information of the reconfiguration code stream.
9. A computer readable storage medium having stored therein computer executable instructions which when executed by a processor implement the steps in the method of claim 8.
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| CN111459874A (en) * | 2020-04-02 | 2020-07-28 | 京微齐力(北京)科技有限公司 | Multiplexing method for field programmable gate array configuration flash memory |
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