CN110212914B - Numerical control oscillator based on multi-order bridge capacitor array - Google Patents

Abstract

The invention provides a numerically controlled oscillator based on a multi-stage bridge capacitor array, which includes a negative resistance module, an inductor L and a multi-stage bridge capacitor array. The negative resistance module includes a PMOS transistor Mp and an NMOS transistor Mn, and the positive port of the negative resistance module is connected to the inductor. The upper end of L, the negative port of the negative resistance module is connected to the lower end of the inductor L; the positive port of the negative resistance module is respectively connected to the gate of the PMOS transistor Mp and the drain of the NMOS transistor Mn, and the negative port of the negative resistance module is respectively connected to the PMOS transistor Mp. The drain is connected to the gate of the NMOS transistor Mn; the source of the PMOS transistor Mp is connected to the power supply, and the source of the NMOS transistor Mn is grounded; the inductor L is connected in parallel with the multi-level bridge capacitor array; the invention changes the structure of the oscillator switched capacitor tuning module, On the basis of the original frequency resolution, the frequency resolution is increased to several hundred times of the original, so as to obtain a higher-precision frequency resolution, and at the same time, it has higher linearity and frequency stability.

Description

Numerically controlled oscillator based on multi-order bridge capacitor array

technical field

The invention relates to a numerically controlled oscillator based on a multi-order bridge capacitor array.

Background technique

An oscillator is a circuit module widely used in electronic systems. Oscillators are everywhere, from processors to carrier synthesis technology chips. In different electronic systems, the requirements for oscillators are also different. Compared with other types of oscillators, numerically controlled oscillators have the advantages of high frequency accuracy, short conversion time, high spectral purity, easy programming of frequency and phase, and high output frequency stability. They are widely used in modern communication systems, including frequency synthesis and various In a digital frequency phase digital modulation and demodulation system. So in the digital communication system, the numerical control oscillator is an indispensable part of the modulation and demodulation unit.

With the development of technologies such as communications, satellite positioning, digital television, aerospace technology and electronic technology, the frequency resolution requirements for numerically controlled oscillators are getting higher and higher.

At present, there are two main methods to improve the frequency resolution of numerically controlled oscillators:

The use of MOS capacitors is a way to improve the resolution of numerically controlled oscillators. MOS capacitors can reduce the capacitance value of the unit capacitor, but the capacitance value of this MOS tube capacitor is limited. When the capacitance value is reduced to the fF level, it is very susceptible to parasitics. The effect of capacitance results in reduced frequency accuracy and poor linearity.

Another implementation is to use a ΔΣ modulator to achieve high resolution, but the ΔΣ modulator will introduce additional phase noise, and because the ΔΣ modulator operates under a high-frequency clock, it will increase the additional power consumption burden.

The above problems are problems that should be considered and solved in the process of improving the frequency resolution of the numerically controlled oscillator.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a numerically controlled oscillator based on a multi-stage bridge capacitor array to solve the problem that the capacitance value of the MOS tube capacitor in the prior art is limited, and when the capacitance value is reduced to the fF level, it is very easy to suffer The effect of parasitic capacitance leads to reduced frequency accuracy, poor linearity, or the use of ΔΣ modulators will introduce additional phase noise, and because the ΔΣ modulators work under high frequency clocks, it will increase additional power consumption burden The problem.

The technical solution of the present invention is:

A numerically controlled oscillator based on a multi-stage bridging capacitor array, comprising a negative resistance module, an inductor L and a multi-stage bridging capacitor array, the negative resistance module includes a PMOS transistor Mp and an NMOS transistor Mn, and the positive port of the negative resistance module is connected to the upper end of the inductance L , the negative port of the negative resistance module is connected to the lower end of the inductor L; the positive port of the negative resistance module is respectively connected to the gate of the PMOS transistor Mp and the drain of the NMOS transistor Mn, and the negative port of the negative resistance module is respectively connected to the drain of the PMOS transistor Mp and the drain The gate of the NMOS transistor Mn; the source of the PMOS transistor Mp is connected to the power supply, and the source of the NMOS transistor Mn is grounded; the inductor L is connected in parallel with the multi-stage bridge capacitor array.

Further, the multi-stage bridging capacitor array includes a bridging capacitor array unit, an upper bridging capacitor unit, a lower bridging capacitor unit, a first attenuation capacitor C _a1 and a second attenuation capacitor C _a2 , and the bridging capacitor array unit includes the 0th order and the first order. , 2nd order, ..., ith order, ..., n-1th order, nth order bridge capacitor array, where i, n are integers and 0<i<n; the upper bridge capacitor unit includes the first upper bridge capacitor C ₁ on _{b, 2 on the second bridging capacitor C b} , ... ₁ , i on the ith upper bridging capacitor C _b , ..., on the n th bridging capacitor C _{b on n} , where i and n are integers and 0<i<n; the lower bridge capacitor unit includes the first lower bridge capacitor C _{b lower 1} , the first lower bridge capacitor C _{b lower 2} , ..., the ith lower bridge capacitor C _{b lower i} , ..., the nth lower bridge capacitor C _{b lower n} , where i and n are integers and 0<i<n;

Port 1 of the 0th-order bridge capacitor array is respectively connected to the positive port of the negative resistance module, the upper port of the inductor L, and the upper plate _{of 1 on the first upper bridge capacitor C b,} and the 2nd port of the 0th-order bridge capacitor array is respectively connected to the negative The negative port of the resistance module, the lower port of the inductor L, and the upper plate of the _{lower 1 of the first lower bridge capacitor C b} ;

The 1st port of the i-th order bridge capacitor array is connected to the lower plate of i on the i-th upper bridge capacitor C _b, the upper plate _{of i+1 on the second upper bridge capacitor C b,} and the 2th port of the i-th order bridge capacitor array is connected to The i-th lower bridging capacitor C _{b is connected to the lower plate of i} , and the i+1-th lower bridging capacitor C _{b is connected to the upper plate of i+1} ;

Port 1 of the nth-order bridge capacitor array is connected to the lower plate of n on the nth upper bridge capacitor C _{b and} the upper plate of the first attenuation capacitor C _a1 , and port 2 of the nth-order bridge capacitor array is connected to the nth lower bridge capacitor The lower plate _{of n under C b and} the lower plate of the second attenuation capacitor C _a2 ; the lower plate of the first attenuation capacitor C _a1 is connected to the upper plate of the second attenuation capacitor C _a2 .

Further, the structures of the 0th-order, 1st-order, 2nd-order..., i-th order,...n-th order bridge capacitor arrays are all the same.

Further, the 0th order bridging capacitor array includes a first tuning capacitor module C _u1 and a second tuning capacitor module C _u2 , the 1 port of the 0th order bridging capacitor array is connected to the upper plate of the first tuning capacitor module C _u1 , and the 0th The 2 ports of the step bridge capacitor array are connected to the lower plate of the second tuning capacitor module C _u2 ; the lower plate of the first tuning capacitor module C _u1 is connected to the upper plate of the second tuning capacitor module C _u2 .

Further, in the multi-stage bridge capacitor array, the capacitance values need to satisfy the following relationship: 1 on the first upper bridge capacitor C _b , 2 on the second upper bridge capacitor C _b , ..., i on the i-th upper bridge capacitor C _b , ... , the n-1th upper bridge capacitor _{Cb is n-1} , the first lower bridge capacitor _{Cb is 1} , the second lower bridge capacitor _{Cb is 2} , ..., the ith lower bridge capacitor _{Cb is i} , ..., the first The capacitance value of n-1 under the bridge capacitor _{Cb under n-1} is all _Cb , the capacitance value of n on the nth upper bridge capacitor _Cb, and the capacitance value of n under the nth lower bridge capacitor _Cb is _Cs , the first tuning capacitor The capacitance values of C _u1 and the second tuning capacitor C _u2 are both C _u , and the capacitance values of the first attenuation capacitor C _a1 and the second attenuation capacitor C _a2 are both C _a , when the capacitance values satisfy:

C _a =C _u -C _S

(1)

The minimum variable capacitance of the numerically controlled oscillator based on the multi-order bridge capacitor array is:

In the formula, ΔC _u is the unit variable capacitance value of any first-order bridge capacitor array, and n is the number of bridge capacitor arrays in the bridge capacitor array unit.

The beneficial effects of the present invention are: for the numerically controlled oscillator based on a multi-order bridge capacitor array, by changing the structure of the oscillator switched capacitor tuning module, on the basis of the original frequency resolution, the frequency resolution is improved to hundreds of the original. times, so as to obtain higher precision frequency resolution, and at the same time have higher linearity and frequency stability. This kind of numerical control oscillator based on multi-order bridge capacitor array adopts LC numerical control oscillator and adds bridge capacitor between the switched capacitor arrays of the oscillator, so that the modulation accuracy of the capacitor is improved hundreds of times compared with the original, so that the numerical control oscillator can be greatly improved. It has high frequency resolution, high linearity and frequency stability, and will not increase the power consumption of its entire oscillation circuit, and can optimize the phase noise performance.

Description of drawings

1 is a schematic structural diagram of a numerically controlled oscillator based on a multi-order bridge capacitor array according to an embodiment of the present invention;

Fig. 2 is the SP simulation schematic diagram of the numerically controlled oscillator based on the multi-order bridge capacitor array of the embodiment;

FIG. 3 is a schematic diagram of a phase noise simulation comparison between a numerically controlled oscillator based on a multi-order bridge capacitor array and a numerically controlled oscillator without a bridge capacitor array according to an embodiment.

Detailed ways

The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Example

A numerically controlled oscillator based on a multi-order bridge capacitor array, as shown in Figure 1, includes a negative resistance module, an inductor L and a multi-order bridge capacitor array. The negative resistance module includes a PMOS transistor Mp and an NMOS transistor Mn, and the positive port of the negative resistance module is connected. The upper end of the inductor L, the negative port of the negative resistance module is connected to the lower end of the inductor L; the positive port of the negative resistance module is respectively connected to the gate of the PMOS transistor Mp and the drain of the NMOS transistor Mn, and the negative port of the negative resistance module is respectively connected to the PMOS transistor Mp The drain of the NMOS transistor Mn is connected to the gate of the NMOS transistor Mn; the source of the PMOS transistor Mp is connected to the power supply, and the source of the NMOS transistor Mn is grounded; the inductor L is connected in parallel with the multi-stage bridge capacitor array.

The multi-stage bridge capacitor array includes a bridge capacitor array unit, an upper bridge capacitor unit, a lower bridge capacitor unit, a first attenuation capacitor C _a1 and a second attenuation capacitor C _a2 , and the bridge capacitor array unit includes the 0th order, the first order, the second order order, _. , 2 on the second upper bridging capacitor C _b , ... ₁ , i on the i-th upper bridging capacitor C _b , ... , on the n th upper bridging capacitor C _{b on n} , where i and n are integers and 0<i<n; The bridge capacitor unit includes a first lower bridge capacitor C b _{lower 1} , a first lower bridge capacitor C _{b lower 2 ,} . . . , n is an integer and 0<i<n;

Port 1 of the 0th-order bridge capacitor array is respectively connected to the positive port of the negative resistance module, the upper port of the inductor L, and the upper plate _{of 1 on the first upper bridge capacitor C b,} and the 2nd port of the 0th-order bridge capacitor array is respectively connected to the negative The negative port of the resistance module, the lower port of the inductor L, and the upper plate of the _{lower 1 of the first lower bridge capacitor C b} ;

The 1st port of the i-th order bridge capacitor array is connected to the lower plate of i on the i-th upper bridge capacitor C _b, the upper plate _{of i+1 on the second upper bridge capacitor C b,} and the 2th port of the i-th order bridge capacitor array is connected to The i-th lower bridging capacitor C _{b is connected to the lower plate of i} , and the i+1-th lower bridging capacitor C _{b is connected to the upper plate of i+1} ;

Port 1 of the nth-order bridge capacitor array is connected to the lower plate of n on the nth upper bridge capacitor C _{b and} the upper plate of the first attenuation capacitor C _a1 , and port 2 of the nth-order bridge capacitor array is connected to the nth lower bridge capacitor The lower plate _{of n under C b and} the lower plate of the second attenuation capacitor C _a2 ; the lower plate of the first attenuation capacitor C _a1 is connected to the upper plate of the second attenuation capacitor C _a2 .

This kind of numerically controlled oscillator based on multi-order bridge capacitor array, by changing the structure of the oscillator switched capacitor tuning module, on the basis of the original frequency resolution, the frequency resolution is increased to several hundred times the original, so as to obtain higher precision high frequency resolution, high linearity and frequency stability. This kind of numerical control oscillator based on multi-order bridge capacitor array adopts LC numerical control oscillator and adds bridge capacitor between the switched capacitor arrays of the oscillator, so that the modulation accuracy of the capacitor is improved hundreds of times compared with the original, so that the numerical control oscillator can be greatly improved. It has high frequency resolution, high linearity and frequency stability, and will not increase the power consumption of its entire oscillation circuit, and can optimize the phase noise performance.

In the numerically controlled oscillator based on the multi-order bridge capacitor array, the structures of the 0th order, the first order, the second order..., the ith order, and the nth order bridge capacitance array are all the same. The 0th-order bridge capacitor array includes a first tuning capacitor module C _u1 and a second tuning capacitor module C _u2 , the 1st port of the 0th-order bridge capacitor array is connected to the upper plate of the first tuning capacitor module C _u1 , and the 0th-order bridge capacitor is connected to the upper plate of the first tuning capacitor module C u1 . Port 2 of the array is connected to the lower plate of the second tuning capacitor module C _u2 ; the lower plate of the first tuning capacitor module C _u1 is connected to the upper plate of the second tuning capacitor module C _u2 .

In the multi-stage bridge capacitor array, the capacitance values must satisfy the following relationship: 1 on the first upper bridge capacitor C _b , 2 on the second upper bridge capacitor C _b , ..., i on the ith upper bridge capacitor C _b , ... , n th -1 upper bridge capacitor C _{b on n-1} , first lower bridge capacitor C _{b lower 1} , second lower bridge capacitor C _{b lower 2} , ..., i th lower bridge capacitor C _{b lower i} , ..., n-1 th The capacitance value _{of n-1 under the lower bridge capacitor Cb} is all _Cb , the capacitance value of n on the nth upper bridge capacitor _Cb, and the capacitance value of n under the nth lower bridge capacitor _Cb is _Cs , the first tuning capacitor C _u1 , The capacitance values of the second tuning capacitor C _u2 are both C _u , the capacitance values of the first attenuation capacitor C _a1 and the second attenuation capacitor C _a2 are both C _a , when the capacitance values satisfy:

C _a =C _u -C _S

The minimum variable capacitance of the numerically controlled oscillator based on the multi-order bridge capacitor array is:

In the formula, ΔC _u is the unit variable capacitance value of any first-order bridge capacitor array, and n is the number of bridge capacitor arrays in the bridge capacitor array unit.

It can be seen from equation (3) that the minimum variable capacitance ΔC _fine that can be achieved by the numerically controlled oscillator based on the multi-order bridge capacitor array is the minimum variable capacitance ΔC _u that can be achieved by any array multiplied by an attenuation coefficient. The attenuation coefficient depends on the ratio of Cs to Cu, and the order n. Therefore, the minimum variable capacitance ΔC _fine of the numerically controlled oscillator based on the multi-order bridge capacitor array is much smaller than ΔC _u , so that compared with the prior art, the numerical value of the frequency resolution can be smaller and the precision of the frequency resolution is higher.

FIG. 2 is the SP simulation diagram of the numerically controlled oscillator based on the multi-order bridge capacitor array according to the embodiment. In the simulation, ΔC _u =4fF, C _s =0.51pF, and C _u =1.2pF. After theoretical calculation, ΔC _fine = 8aF, which is consistent with the simulation results shown in Figure 2. Through simulation experiments and theoretical calculations, it can be clearly seen that the frequency resolution is 1/500 times that of the existing numerically controlled oscillator, thereby effectively achieving a higher frequency resolution.

The numerical control oscillator based on the multi-order bridge capacitor array of the embodiment and the numerical control oscillator without bridge capacitors are compared for phase noise simulation. As shown in Figure 3, at a frequency offset of 1MHz, the numerical control oscillator without bridge capacitors The phase noise of the oscillator is -106.4dBc/Hz, and after using the numerically controlled oscillator based on the multi-order bridge capacitor array of the embodiment, the phase noise of the output signal drops to -116.8dBc/Hz, that is to say, the The numerically controlled oscillator based on a multi-order bridge capacitor array can optimize the phase noise performance of the numerically controlled oscillator by 10dBc/Hz.

The embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned embodiments, and can also be made within the scope of knowledge possessed by those of ordinary skill in the art without departing from the purpose of the present invention. Various changes.

Claims (3)

1. a numerically controlled oscillator based on multi-order bridge capacitor array, it is characterized in that: comprise negative resistance module, inductance L and multi-order bridge capacitance array, negative resistance module comprises PMOS transistor Mp and NMOS transistor Mn, the positive resistance of negative resistance module. The port is connected to the upper end of the inductor L, the negative port of the negative resistance module is connected to the lower end of the inductor L; the positive port of the negative resistance module is respectively connected to the gate of the PMOS transistor Mp and the drain of the NMOS transistor Mn, and the negative port of the negative resistance module is connected to the PMOS transistor respectively. The drain of the transistor Mp is connected to the gate of the NMOS transistor Mn; the source of the PMOS transistor Mp is connected to the power supply, and the source of the NMOS transistor Mn is grounded; the inductor L is connected in parallel with the multi-stage bridge capacitor array; The multi-stage bridge capacitor array includes a bridge capacitor array unit, an upper bridge capacitor unit, a lower bridge capacitor unit, a first attenuation capacitor C _a1 and a second attenuation capacitor C _a2 , and the bridge capacitor array unit includes the 0th order, the first order, the second order order, _. , 2 on the second upper bridging capacitor C _b , ... ₁ , i on the i-th upper bridging capacitor C _b , ... , on the n th upper bridging capacitor C _{b on n} , where i and n are integers and 0<i<n; The bridge capacitor unit includes a first lower bridge capacitor C b _{lower 1} , a first lower bridge capacitor C _{b lower 2 ,} . . . , n is an integer and 0<i<n; Port 1 of the 0th-order bridge capacitor array is respectively connected to the positive port of the negative resistance module, the upper port of the inductor L, and the upper plate _{of 1 on the first upper bridge capacitor C b,} and the 2nd port of the 0th-order bridge capacitor array is respectively connected to the negative The negative port of the resistance module, the lower port of the inductor L, and the upper plate of the _{lower 1 of the first lower bridge capacitor C b} ; The 1st port of the i-th order bridge capacitor array is connected to the lower plate of i on the i-th upper bridge capacitor C _b, the upper plate _{of i+1 on the second upper bridge capacitor C b,} and the 2th port of the i-th order bridge capacitor array is connected to The i-th lower bridging capacitor C _{b is connected to the lower plate of i} , and the i+1-th lower bridging capacitor C _{b is connected to the upper plate of i+1} ; Port 1 of the nth-order bridge capacitor array is connected to the lower plate of n on the nth upper bridge capacitor C _{b and} the upper plate of the first attenuation capacitor C _a1 , and port 2 of the nth-order bridge capacitor array is connected to the nth lower bridge capacitor The lower plate _{of n under C b,} the lower plate of the second attenuation capacitor C _a2 ; the lower plate of the first attenuation capacitor C _a1 is connected to the upper plate of the second attenuation capacitor C _a2 ; In the multi-stage bridge capacitor array, the capacitance values must satisfy the following relationship: 1 on the first upper bridge capacitor C _b , 2 on the second upper bridge capacitor C _b , ..., i on the ith upper bridge capacitor C _b , ... , n th -1 upper bridge capacitor C _{b on n-1} , first lower bridge capacitor C _{b lower 1} , second lower bridge capacitor C _{b lower 2} , ..., i th lower bridge capacitor C _{b lower i} , ..., n-1 th The capacitance value _{of n-1 under the lower bridge capacitor Cb} is all _Cb , the capacitance value of n on the nth upper bridge capacitor _Cb, and the capacitance value of n under the nth lower bridge capacitor _Cb is _Cs , the first tuning capacitor C _u1 , The capacitance values of the second tuning capacitor C _u2 are both C _u , the capacitance values of the first attenuation capacitor C _a1 and the second attenuation capacitor C _a2 are both C _a , when the capacitance values satisfy: C _a =C _u -C _S (1)

The minimum variable capacitance of the numerically controlled oscillator based on the multi-order bridge capacitor array is:

In the formula, ΔC _u is the unit variable capacitance value of any first-order bridge capacitor array, and n is the number of bridge capacitor arrays in the bridge capacitor array unit. 2. The numerically controlled oscillator based on a multi-stage bridging capacitor array as claimed in claim 1, wherein the structure of the 0th order, the 1st order, the 2nd order..., the ith order, ... the nth order bridge capacitance array are the same. 3. The numerically controlled oscillator based on a multi-order bridging capacitor array as claimed in claim 1, wherein the 0th order bridging capacitor array comprises the first tuning capacitor module C _u1 and the second tuning capacitor module C _u2 , the 0th order The 1 port of the bridging capacitor array is connected to the upper plate of the first tuning capacitor module C _u1 , and the 2 port of the 0th order bridging capacitor array is connected to the lower plate of the second tuning capacitor module C _u2 ; the lower electrode of the first tuning capacitor module C _u1 The board is connected to the upper plate of the second tuning capacitor module C _u2 .

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