CN110212914B - Numerical control oscillator based on multi-order bridge capacitor array - Google Patents
Numerical control oscillator based on multi-order bridge capacitor array Download PDFInfo
- Publication number
- CN110212914B CN110212914B CN201910653701.8A CN201910653701A CN110212914B CN 110212914 B CN110212914 B CN 110212914B CN 201910653701 A CN201910653701 A CN 201910653701A CN 110212914 B CN110212914 B CN 110212914B
- Authority
- CN
- China
- Prior art keywords
- capacitor
- bridge
- bridging
- port
- order
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 241
- 238000003491 array Methods 0.000 claims description 9
- 101100134058 Caenorhabditis elegans nth-1 gene Proteins 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 3
- 150000004706 metal oxides Chemical class 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000004088 simulation Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
Landscapes
- Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
Abstract
The invention provides a multi-order bridge capacitor array-based numerically-controlled oscillator, which comprises a negative resistance module, an inductor L and a multi-order bridge capacitor array, wherein the negative resistance module comprises a PMOS (P-channel metal oxide semiconductor) transistor Mp and an NMOS (N-channel metal oxide semiconductor) transistor Mn, a positive port of the negative resistance module is connected with the upper end of the inductor L, and a negative port of the negative resistance module is connected with the lower end of the inductor L; the positive port of the negative resistance module is respectively connected with the grid of the PMOS transistor Mp and the drain of the NMOS transistor Mn, and the negative port of the negative resistance module is respectively connected with the drain of the PMOS transistor Mp and the grid of the NMOS transistor Mn; the source electrode of the PMOS transistor Mp is connected with a power supply, and the source electrode of the NMOS transistor Mn is grounded; the inductor L is connected with the multi-stage bridging capacitor array in parallel; the invention improves the frequency resolution ratio by hundreds of times on the basis of the original frequency resolution ratio by changing the structure of the oscillator switch capacitance tuning module, thereby obtaining the frequency resolution ratio with higher precision and simultaneously having higher linearity and frequency stability.
Description
Technical Field
The invention relates to a numerical control oscillator based on a multi-order bridge capacitor array.
Background
An oscillator is a circuit module widely used in electronic systems. From processors to carrier synthesis technology chips, oscillators are ubiquitous. The requirements for oscillators vary in different electronic systems. Compared with other types of oscillators, the numerically controlled oscillator has the advantages of high frequency precision, short conversion time, high spectral purity, easy programming of frequency phase, high output frequency stability and the like, and is widely applied to modern communication systems including frequency synthesis and various digital frequency phase digital modulation and demodulation systems. In a digital communication system, a digitally controlled oscillator is then an essential part of the modem unit.
With the development of technologies such as communication, satellite positioning, digital television, aerospace technology, electronic technology and the like, the requirement on the frequency resolution of the numerically controlled oscillator is higher and higher.
At present, the following two methods are mainly used for improving the frequency resolution of a numerically controlled oscillator:
the MOS capacitor is a method for improving the resolution of the numerically controlled oscillator, the MOS capacitor can reduce the capacitance value of the unit capacitor, but the capacitance value reduction of the MOS transistor capacitor is limited, when the capacitance value is reduced to the fF level, the frequency accuracy is easily reduced due to the influence of parasitic capacitance, and the linearity is poor.
Another implementation is to use a delta-sigma modulator to achieve high resolution, but the delta-sigma modulator introduces additional phase noise and adds additional power consumption burden since the delta-sigma modulator operates at a high frequency clock.
The above-mentioned problems are problems that should be considered and solved in improving the frequency resolution of the digitally controlled oscillator.
Disclosure of Invention
The invention aims to provide a numerical control oscillator based on a multi-order bridge capacitor array, which solves the problems that in the prior art, the capacity value of an MOS (metal oxide semiconductor) tube capacitor is reduced to a limit value by adopting an MOS capacitor, when the capacity value is reduced to an fF level, the frequency accuracy is reduced and the linearity is poor due to the influence of parasitic capacitance, or extra phase noise is introduced due to the adoption of a delta sigma modulator, and extra power consumption burden is increased due to the fact that the delta sigma modulator works under a high-frequency clock.
The technical solution of the invention is as follows:
a numerical control oscillator based on a multi-order bridge capacitor array comprises a negative resistance module, an inductor L and a multi-order bridge capacitor array, wherein the negative resistance module comprises a PMOS transistor Mp and an NMOS transistor Mn; the positive port of the negative resistance module is respectively connected with the grid electrode of the PMOS transistor Mp and the drain electrode of the NMOS transistor Mn, and the negative port of the negative resistance module is respectively connected with the drain electrode of the PMOS transistor Mp and the grid electrode of the NMOS transistor Mn; the source electrode of the PMOS transistor Mp is connected with a power supply, and the source electrode of the NMOS transistor Mn is grounded; the inductor L is connected in parallel with the multi-stage bridge capacitor array.
Furthermore, the multi-level bridge capacitor array includes bridge capacitor array units, upper bridge capacitor units, lower bridge capacitor units, and first attenuation capacitors C a1 And a second attenuation capacitor C a2 The bridging capacitor array unit comprises 0 th, 1 st, 2 nd, 8230, ith, 8230, nth-1 st and nth bridging capacitor arrays, wherein i and n are integers and 0<i<n; the upper bridge capacitor unit comprises a first upper bridge capacitor C b 1 on A second upper bridge capacitor C b on 2 、… 1 The ith upper bridge capacitor C b upper i 8230the n upper bridge connection capacitor C N on b Wherein i and n are integers and 0<i<n; the lower bridge capacitor unit comprises a first lower bridge capacitor C b lower 1 A first lower bridge capacitor C b lower 2 823060, the ith lower bridging capacitor C b lower i 8230the n lower bridge connection capacitor C b is lower than n Wherein i and n are integers and 0<i<n；
The 1 port of the 0 th-order bridging capacitor array is respectively connected with the positive port of the negative resistance module, the upper port of the inductor L and the first upper bridging capacitor C b 1 on 2 ports of the 0 th-order bridging capacitor array are respectively connected with a negative port of the negative resistance module, a lower port of the inductor L and a first lower bridging capacitor C b lower 1 The upper electrode plate of (1);
the 1 port of the ith bridging capacitor array is connected with the ith upper bridging capacitor C b upper i Lower plate and second upper bridge capacitor C b is on i +1 The 2 port of the ith-stage bridging capacitor array is connected with the ith lower bridging capacitor C b lower i Lower plate, i +1 th lower bridge capacitor C b is lower i +1 The upper plate of (1);
the 1 port of the nth-order bridging capacitor array is connected with the nth upper bridging capacitor C N on b Lower plate of (2), first attenuation capacitor C a1 The 2 port of the nth-order bridging capacitor array is connected with the nth lower bridging capacitor C b is lower than n Lower plate and second attenuation capacitor C a2 The lower pole plate of (1); first attenuation capacitor C a1 The lower pole plate is connected with the first pole plateTwo attenuation capacitors C a2 The upper plate of (2).
Furthermore, the 0 th order, the 1 st order, the 2 nd order, \ 8230, the ith order, \8230andthe nth order bridging capacitor arrays have the same structure.
Further, the 0 th-order bridge capacitor array comprises a first tuning capacitor module C u1 And a second tuning capacitor module C u2 The 1 port of the 0 th-order bridging capacitor array is connected with a first tuning capacitor module C u1 2 port of 0 th order bridging capacitor array is connected with second tuning capacitor module C u2 A lower polar plate; first tuning capacitor module C u1 The lower pole plate is connected with a second tuning capacitor module C u2 The upper plate of (2).
Further, in the multi-level bridge capacitor array, the capacitance value should satisfy the following relationship: first upper bridge capacitor C b 1 on A second upper bridge capacitor C b on 2 823060, the ith upper bridging capacitor C b upper i 8230the n-1 th upper bridge capacitor C N-1 on b A first lower bridge capacitor C b lower 1 A second lower bridge capacitor C b lower 2 823060, the ith lower bridging capacitor C b lower i 823060, n-1 lower bridge capacitor C b is n-1 All have a capacity value of C b An n-th upper bridge capacitor C N on b N lower bridge capacitor C b is lower than n Has a capacity value of C s First tuning capacitor C u1 A second tuning capacitor C u2 All the capacitance values of (A) are C u First attenuation capacitor C a1 A second attenuation capacitor C a2 All volume values are C a When the capacitance value satisfies:
C a ＝C u -C S
(1)
the minimum variable capacitance of the numerical control oscillator based on the multi-order bridge capacitor array is as follows:
in the formula,. DELTA.C u The unit variable capacitance value of any one-order bridging capacitor array, and n is the number of the bridging capacitor arrays in the bridging capacitor array unit.
The beneficial effects of the invention are: the numerical control oscillator based on the multi-order bridge capacitor array improves the frequency resolution to hundreds of times on the basis of the original frequency resolution by changing the structure of the oscillator switch capacitor tuning module, thereby obtaining the frequency resolution with higher precision and having higher linearity and frequency stability. This kind of numerical control oscillator based on multistage bridge connection capacitor array adopts LC numerical control oscillator, adds bridge connection electric capacity between the switch capacitor array of oscillator for the modulation precision of electric capacity improves several hundred times than originally, thereby can improve numerical control oscillator's frequency resolution greatly, and has higher linearity, frequency stability, also can not increase its whole oscillation circuit's consumption, and can realize the optimization of phase noise performance.
Drawings
FIG. 1 is a schematic diagram of a multi-stage bridge capacitor array-based VCO structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an embodiment of an SP simulation of a multi-stage bridge capacitor array based digitally controlled oscillator;
FIG. 3 is a comparison diagram of phase noise simulation of a multi-stage bridge capacitor array-based VCO and a VCO without a bridge capacitor array according to an embodiment.
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
Examples
A numerical control oscillator based on a multi-order bridge capacitor array is shown in figure 1 and comprises a negative resistance module, an inductor L and a multi-order bridge capacitor array, wherein the negative resistance module comprises a PMOS transistor Mp and an NMOS transistor Mn; the positive port of the negative resistance module is respectively connected with the grid of the PMOS transistor Mp and the drain of the NMOS transistor Mn, and the negative port of the negative resistance module is respectively connected with the drain of the PMOS transistor Mp and the grid of the NMOS transistor Mn; the source electrode of the PMOS transistor Mp is connected with a power supply, and the source electrode of the NMOS transistor Mn is grounded; the inductor L is connected in parallel with the multi-stage bridge capacitor array.
The multi-stage bridge capacitor array comprises a bridge capacitor array unit, an upper bridge capacitor unit, a lower bridge capacitor unit, and a first attenuation capacitor C a1 And a second attenuation capacitor C a2 The bridging capacitor array unit comprises 0 th, 1 st, 2 nd, 8230, ith, 8230, nth-1 st and nth bridging capacitor arrays, wherein i and n are integers and 0<i<n; the upper bridge capacitor unit comprises a first upper bridge capacitor C b in 1 A second upper bridge capacitor C b on 2 、… 1 The ith upper bridge capacitor C b upper i 8230the n upper bridge connection capacitor C N on b Wherein i and n are integers of 0<i<n; the lower bridge capacitor unit comprises a first lower bridge capacitor C b lower 1 A first lower bridge capacitor C b lower 2 823060, the ith lower bridging capacitor C b lower i 8230the n lower bridge connection capacitor C b is lower than n Wherein i and n are integers and 0<i<n；
The 1 port of the 0 th-order bridging capacitor array is respectively connected with the positive port of the negative resistance module, the upper port of the inductor L and the first upper bridging capacitor C b in 1 2 ports of the 0 th-order bridging capacitor array are respectively connected with a negative port of the negative resistance module, a lower port of the inductor L and a first lower bridging capacitor C b lower 1 The upper electrode plate of (1);
the 1 port of the ith stage bridging capacitor array is connected with the ith upper bridging capacitor C b upper i Lower plate and second upper bridge capacitor C b is on i +1 The 2 port of the ith-stage bridging capacitor array is connected with the ith lower bridging capacitor C b lower i Lower polar plate, i +1 th lower bridge capacitor C b lower i +1 The upper electrode plate of (1);
the 1 port of the nth stage bridging capacitor array is connected with the nth upper bridging capacitor C N on b Lower plate and first attenuation capacitor C a1 The 2 port of the nth-stage bridging capacitor array is connected with the nth lower bridging capacitor C b is lower than n Lower plate and second attenuation capacitor C a2 The lower pole plate of (2); first attenuation capacitor C a1 Lower pole of (2)The plate is connected with a second attenuation capacitor C a2 The upper plate of (2).
According to the numerical control oscillator based on the multi-order bridge capacitor array, the structure of the oscillator switch capacitor tuning module is changed, on the basis of the original frequency resolution, the frequency resolution is improved by hundreds of times, the frequency resolution with higher precision is obtained, and meanwhile, the numerical control oscillator has higher linearity and frequency stability. This kind of numerical control oscillator based on multistage bridge connection capacitor array adopts LC numerical control oscillator, adds bridge connection electric capacity between the switch capacitor array of oscillator for the modulation precision of electric capacity improves several hundred times than originally, thereby can improve numerical control oscillator's frequency resolution greatly, and has higher linearity, frequency stability, also can not increase its whole oscillation circuit's consumption, and can realize the optimization of phase noise performance.
In the numerical control oscillator based on the multi-stage bridging capacitor array, 0 th order, 1 st order, 2 nd order, \8230, ith order, \8230andnth order bridging capacitor arrays have the same structure. The 0 th-order bridge capacitor array comprises a first tuning capacitor module C u1 And a second tuning capacitor module C u2 The 1 port of the 0 th-order bridging capacitor array is connected with a first tuning capacitor module C u1 2 ports of the 0 th-order bridging capacitor array are connected with a second tuning capacitor module C u2 A lower polar plate; first tuning capacitor module C u1 The lower pole plate is connected with a second tuning capacitor module C u2 The upper plate of (2).
In a multi-level bridge capacitor array, the capacitance values need to satisfy the following relationship: first upper bridge capacitor C b in 1 A second upper bridge capacitor C b upper 2 823060, the ith upper bridging capacitor C b upper i 8230the n-1 upper bridge capacitor C N-1 on b A first lower bridge capacitor C b lower 1 A second lower bridge capacitor C b lower 2 823060, the ith lower bridging capacitor C b lower i 823060, n-1 lower bridge capacitor C b is n-1 All have a capacitance value of C b N upper bridge capacitor C N on b N lower bridge capacitor C b is lower than n Has a capacity value of C s First tuning capacitor C u1 A second tuning capacitor C u2 All the capacitance values of (A) are C u First attenuation capacitor C a1 A second attenuation capacitor C a2 All volume values are C a When the capacitance value satisfies:
C a ＝C u -C S
the minimum variable capacitance of the numerical control oscillator based on the multi-order bridge capacitor array is as follows:
in the formula,. DELTA.C u The unit variable capacitance value of the bridge capacitor array of any order, and n is the number of the bridge capacitor arrays in the bridge capacitor array unit.
As can be seen from the formula (3), the minimum variable capacitance Δ C that can be achieved by the numerical control oscillator based on the multi-stage bridge capacitor array fine Minimum variable capacitance Δ C achievable for any one array u Multiplied by an attenuation factor that depends on the ratio of Cs to Cu, and the order n. Therefore, the minimum variable capacitance delta C of the numerical control oscillator based on the multi-order bridge capacitor array fine Much less than Δ C u Therefore, compared with the prior art, the numerical value of the frequency resolution is smaller, and the precision of the frequency resolution is higher.
FIG. 2 is a diagram of an embodiment of an SP simulation of a multi-stage bridge capacitor array-based digitally controlled oscillator, where Δ C is obtained in the simulation u ＝4fF、C s ＝0.51pF、C u =1.2pF. Calculated by theory to obtain Δ C fine =8aF, which is consistent with the simulation result shown in fig. 2. Through simulation experiments and theoretical calculation, the frequency resolution is obviously 1/500 times that of the existing numerical control oscillator, so that the frequency resolution with higher precision is effectively realized.
Comparing the phase noise simulation of the multi-level bridge capacitor array-based digitally controlled oscillator with the phase noise simulation of the multi-level bridge capacitor array-based digitally controlled oscillator without the bridge capacitor, as shown in fig. 3, at a frequency offset of 1MHz, the phase noise of the multi-level bridge capacitor array-based digitally controlled oscillator without the bridge capacitor is-106.4 dBc/Hz, and after the multi-level bridge capacitor array-based digitally controlled oscillator of the embodiment is adopted, the phase noise of the output signal is reduced to-116.8 dBc/Hz, that is, the multi-level bridge capacitor array-based digitally controlled oscillator of the embodiment can optimize the phase noise performance of the digitally controlled oscillator to 10dBc/Hz.
The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.
Claims (3)
1. A numerical control oscillator based on a multi-order bridge capacitor array is characterized in that: the negative resistance module comprises a PMOS transistor Mp and an NMOS transistor Mn, a positive port of the negative resistance module is connected with the upper end of the inductor L, and a negative port of the negative resistance module is connected with the lower end of the inductor L; the positive port of the negative resistance module is respectively connected with the grid electrode of the PMOS transistor Mp and the drain electrode of the NMOS transistor Mn, and the negative port of the negative resistance module is respectively connected with the drain electrode of the PMOS transistor Mp and the grid electrode of the NMOS transistor Mn; the source electrode of the PMOS transistor Mp is connected with a power supply, and the source electrode of the NMOS transistor Mn is grounded; the inductor L is connected with the multi-stage bridging capacitor array in parallel;
the multi-stage bridge capacitor array comprises a bridge capacitor array unit, an upper bridge capacitor unit, a lower bridge capacitor unit, and a first attenuation capacitor C a1 And a second attenuation capacitor C a2 The bridging capacitor array unit comprises 0 th, 1 st, 2 nd, 8230, ith, 8230, nth-1 st and nth bridging capacitor arrays, wherein i and n are integers and 0<i<n; the upper bridge capacitor unit comprises a first upper bridge capacitor C b in 1 A second upper bridge capacitor C b upper 2 、… 1 The ith upper bridge capacitor C b upper i 823060, n upper bridge capacitor C N on b Wherein i and n are integers of 0<i<n; the lower bridge capacitor unit comprises a first lower bridge capacitor C b lower 1 A first lower bridge capacitor C b lower 2 8230the ith lower bridge connection capacitor C b lower i 8230the n lower bridge connection capacitor C b is lower than n Wherein i and n are integers and 0<i<n；
The 1 port of the 0 th-order bridging capacitor array is respectively connected with the positive port of the negative resistance module, the upper port of the inductor L and the first upper bridging capacitor C b in 1 2 ports of the 0 th-order bridging capacitor array are respectively connected with a negative port of the negative resistance module, a lower port of the inductor L and a first lower bridging capacitor C b lower 1 The upper electrode plate of (1);
the 1 port of the ith stage bridging capacitor array is connected with the ith upper bridging capacitor C b upper i Lower plate and second upper bridge capacitor C I +1 on b The 2 port of the ith-stage bridging capacitor array is connected with the ith lower bridging capacitor C b lower i Lower polar plate, i +1 th lower bridge capacitor C b lower i +1 The upper electrode plate of (1);
the 1 port of the nth-order bridging capacitor array is connected with the nth upper bridging capacitor C N on b Lower plate of (2), first attenuation capacitor C a1 The 2 port of the nth-stage bridging capacitor array is connected with the nth lower bridging capacitor C b is lower than n Lower plate and second attenuation capacitor C a2 The lower pole plate of (1); a first attenuation capacitor C a1 The lower pole plate of the first attenuator is connected with a second attenuation capacitor C a2 The upper plate of (1);
in a multi-level bridge capacitor array, the capacitance values need to satisfy the following relationship: first upper bridge capacitor C b in 1 A second upper bridge capacitor C b upper 2 8230the ith upper bridge connection capacitor C b upper i 8230the n-1 upper bridge capacitor C N-1 on b A first lower bridge capacitor C b lower 1 A second lower bridge capacitor C b lower 2 8230the ith lower bridge connection capacitor C b lower i 8230the n-1 lower bridge connection capacitor C b is n-1 All have a capacitance value of C b N upper bridge capacitor C N on b N lower bridge capacitor C b is lower than n Has a capacity value of C s First tuning capacitor C u1 A second tuning capacitor C u2 All the capacitance values of (A) are C u First attenuation capacitor C a1 A second attenuation capacitor C a2 All volume values are C a When the capacitance value satisfies:
C a ＝C u -C S
(1)
the minimum variable capacitance of the numerical control oscillator based on the multi-order bridge capacitor array is as follows:
in the formula,. DELTA.C u The unit variable capacitance value of any one-order bridging capacitor array, and n is the number of the bridging capacitor arrays in the bridging capacitor array unit.
2. The multiple-stage bridge capacitor array based digitally controlled oscillator of claim 1, wherein: the structures of 0 th order, 1 st order, 2 nd order, 8230, ith order, 8230and nth order bridging capacitor arrays are the same.
3. The multiple-stage bridge capacitor array based digitally controlled oscillator of claim 1, wherein: the 0 th-order bridge capacitor array comprises a first tuning capacitor module C u1 And a second tuning capacitor module C u2 The 1 port of the 0 th-order bridging capacitor array is connected with a first tuning capacitor module C u1 2 port of 0 th order bridging capacitor array is connected with second tuning capacitor module C u2 A lower polar plate; first tuning capacitor module C u1 The lower pole plate is connected with a second tuning capacitor module C u2 The upper plate of (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910653701.8A CN110212914B (en) | 2019-07-18 | 2019-07-18 | Numerical control oscillator based on multi-order bridge capacitor array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910653701.8A CN110212914B (en) | 2019-07-18 | 2019-07-18 | Numerical control oscillator based on multi-order bridge capacitor array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110212914A CN110212914A (en) | 2019-09-06 |
| CN110212914B true CN110212914B (en) | 2022-10-18 |
Family
ID=67797790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910653701.8A Active CN110212914B (en) | 2019-07-18 | 2019-07-18 | Numerical control oscillator based on multi-order bridge capacitor array |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110212914B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111786672B (en) * | 2020-06-03 | 2022-11-08 | 东南大学 | Transformer coupling switch capacitor ladder circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101483434A (en) * | 2008-01-11 | 2009-07-15 | 上海锐协微电子科技有限公司 | Voltage control oscillator with low tuning gain variance |
| CN101662281A (en) * | 2009-09-10 | 2010-03-03 | 上海交通大学 | Inductance-capacitance numerical control oscillator |
| CN108259037A (en) * | 2018-02-01 | 2018-07-06 | 中国电子科技集团公司第五十四研究所 | Multi-resonant chamber couples Low Phase Noise Voltage-controlled Oscillator |
-
2019
- 2019-07-18 CN CN201910653701.8A patent/CN110212914B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101483434A (en) * | 2008-01-11 | 2009-07-15 | 上海锐协微电子科技有限公司 | Voltage control oscillator with low tuning gain variance |
| CN101662281A (en) * | 2009-09-10 | 2010-03-03 | 上海交通大学 | Inductance-capacitance numerical control oscillator |
| CN108259037A (en) * | 2018-02-01 | 2018-07-06 | 中国电子科技集团公司第五十四研究所 | Multi-resonant chamber couples Low Phase Noise Voltage-controlled Oscillator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110212914A (en) | 2019-09-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5977805A (en) | Frequency synthesis circuit tuned by digital words | |
| US8559579B2 (en) | All-digital frequency synthesis with DCO gain calculation | |
| CN107634761B (en) | Digital phase-locked loop frequency synthesis device | |
| US11863192B2 (en) | Radio-frequency (RF) apparatus for digital frequency synthesizer including sigma-delta modulator and associated methods | |
| Saber et al. | Design and implementation of low power digital phase-locked loop | |
| US20030107442A1 (en) | All-digital frequency synthesis with capacitive re-introduction of dithered tuning information | |
| CN105577178A (en) | Broadband low-phase noise Sigma-Delta phase-locked loop | |
| CN110908270A (en) | Constant slope digital-to-time converter and control method thereof | |
| CN110212914B (en) | Numerical control oscillator based on multi-order bridge capacitor array | |
| CN111030599B (en) | Quadrature signal generation | |
| US7847642B2 (en) | Frequency tuning circuit, use of the tuning circuit and method for frequency tuning | |
| US20070008040A1 (en) | Digital phase locked loop, method for controlling a digital phase locked loop and method for generating an oscillator signal | |
| JPH1127142A (en) | Digital control oscillator | |
| CN109787621B (en) | Subsampled digital phase locked loop | |
| CN112242841A (en) | Phase-locked loop circuit with high power supply noise rejection ratio | |
| US11275344B2 (en) | Time to digital converter | |
| CN114710154B (en) | Open-loop fractional frequency divider and clock system based on time division multiplexing gain calibration | |
| CN111786672A (en) | Transformer coupling switch capacitor ladder circuit | |
| US7915968B2 (en) | Digitally controlled oscillator (DCO) | |
| CN110784212B (en) | Frequency locking method and circuit of phase-locked loop | |
| Lu et al. | A 5 GHz 90-nm CMOS all digital phase-locked loop | |
| CN110311674B (en) | Control method and circuit for suppressing spurious output clock of phase-locked loop | |
| US7277519B2 (en) | Frequency and phase correction in a phase-locked loop (PLL) | |
| CN109283832B (en) | Low-power-consumption time-to-digital converter and PHV compensation method thereof | |
| EP1351397A2 (en) | All-digital frequency synthesis with capacitive re-introduction of dithered tuning information |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |