CN110212909A - The non-full method for swinging charger and reducing dynamic readout power using it - Google Patents
The non-full method for swinging charger and reducing dynamic readout power using it Download PDFInfo
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- CN110212909A CN110212909A CN201910297160.XA CN201910297160A CN110212909A CN 110212909 A CN110212909 A CN 110212909A CN 201910297160 A CN201910297160 A CN 201910297160A CN 110212909 A CN110212909 A CN 110212909A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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Abstract
The present invention provides a kind of non-full method for swinging charger and reducing dynamic readout power using it, including the first, second PMOS tube；Third, the 4th NMOS tube；Nor gate, the first, second NAND gate and delay buffer；One of input terminal of first NAND gate connects a SRAM circuit module.The grid of the input terminal of delay buffer, another input terminal of nor gate and the first PMOS tube is accessed into same low-potential signal GPER, opens the first PMOS tube；By the enable signal of another input terminal access high potential of the second NAND gate, the second PMOS tube is opened, is charged to global bit line node GRBL；The grid of third NMOS tube is accessed into YS high level signal, the grid of the 5th to the 7th PMOS tube is connect into high level, local bitline LBLU is made to discharge.The non-full method for swinging charger and reducing dynamic readout power using it of the invention, in the case where not influencing efficiency, reads power through the non-full structure for swinging charger to reduce dynamic.
Description
Technical field
The present invention relates to IC design fields, reduce more particularly to a kind of non-full swing charger and using it dynamic
The method of state readout power.
Background technique
With the continuous development of manufacture of semiconductor technology, the further reducing of chip feature sizes (28HKMG, 22/20nm,
FinFet), static access memory (system on a chip, SoC) design challenge is higher and higher, has under especially SoC
Take into account area/power consumption/efficiency.For hand-held and palm type products, in order to extend the use time static state and dynamic function of battery
Consumption has to reduce as far as possible.There is reduction technology to reduce the technology that dynamic power consumption has been suggested at present, this technology
It can effectively reduce pressure dynamic power consumption, but this technology above can allow the efficiency of product to decline in low-voltage use.
It is, therefore, desirable to provide a kind of non-full method for swinging charger and reducing dynamic readout power using it of new one kind
To solve the above problems.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of non-complete swings charger with make
With the method that it reduces dynamic readout power, cause while for solving and reducing dynamic power consumption under low-pressure state in the prior art
The problem of product efficiency declines.
In order to achieve the above objects and other related objects, the present invention provides a kind of non-full swing charger, includes at least: the
One, the second PMOS tube；Third, the 4th NMOS tube；Nor gate, the first, second NAND gate and delay buffer；The delay is slow
Device output end is rushed to connect with one of input terminal of the nor gate；The output end of the nor gate be connected to described second with
One of input terminal of NOT gate；The output end of second NAND gate is connect with the grid of second PMOS tube；Described
The drain electrode of one PMOS tube is connect with the source electrode of second PMOS tube, and the node of connection is global bit line node；Described first
The grid of PMOS tube is connect with the input terminal of the delay buffer；The drain electrode of the third NMOS tube and the 4th NMOS tube
Source electrode be connected；The drain electrode of 4th NMOS tube is connected to the global bit line node；The output of first NAND gate
End is connected to the grid of the 4th NMOS tube；One of input terminal of first NAND gate connects SRAM circuit module.
Preferably, another input terminal and the first PMOS of the input terminal of the delay buffer, the nor gate
The grid of pipe connects same low-potential signal GPER.
Preferably, the enable signal of another input terminal connection high potential of second NAND gate.
Preferably, the source electrode of first PMOS tube connects high potential；The grounded drain of second PMOS tube.
Preferably, the source electrode ground connection of the third NMOS tube, grid connect YS high potential signal.
Preferably, the SRAM circuit module include: the 5th to the 7th PMOS tube, the SRAM that is made of six metal-oxide-semiconductors it is mono-
Member；Wherein the 5th to the 7th PMOS tube grid be connected with each other, and source, drain electrode it is end to end；Described five, the 6th
The connection of PMOS tube terminates same high potential；The connecting pin and the sram cell of 5th PMOS tube and the 7th PMOS tube
One end access local bitline LBLU；The connecting pin of 6th PMOS tube and the 7th PMOS tube and the sram cell it is another
Local bitline LBLBU is accessed in one end.
Preferably, another input terminal of first NAND gate connects Another SRAM circuit module.
Preferably, the SRAM circuit module that two input terminals of first NAND gate are separately connected is identical.
Preferably, when the non-full swing charger works normally, the wordline in circuit sets high potential.
As described above, the non-full method for swinging charger and reducing dynamic readout power using it of the invention, have with
The non-full method for swinging charger and reducing dynamic readout power using it the utility model has the advantages that of the invention is descended, through non-full swing
The structure of charger reads power in the case where not influencing efficiency to reduce dynamic.
Detailed description of the invention
Fig. 1 is shown as the non-full circuit diagram for swinging charger of the invention；
Fig. 2 is shown as each signal working timing figure in circuit of the present invention.
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Fig. 1 is please referred to Fig. 2.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only shown in schema then with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
As shown in Figure 1, Fig. 1 is shown as the non-full circuit diagram for swinging charger of the invention.The structure of the charger
Include at least in the present embodiment: the first PMOS tube M1, the second PMOS tube M2, nor gate NR, the first NAND gate ND1, second with
NOT gate ND2, delay buffer (buffer delay)；As shown in Figure 1, the wherein delay buffer (buffer delay)
Output end is connect with one of input terminal of the nor gate NR；The output end of the nor gate NR be connected to described second with
One of input terminal of NOT gate ND2；The grid of the output end of the second NAND gate ND2 and the second PMOS tube M2 connect
It connects；The drain electrode of the first PMOS tube M1 is connect with the source electrode of the second PMOS tube M2, and the node of connection is global bit line section
Point GRBL (global read B-line)；The grid and the delay buffer (buffer of the first PMOS tube M1
Delay input terminal connection).
As shown in Figure 1, the drain electrode of the third NMOS tube M3 is connected with the source electrode of the 4th NMOS tube M4；Described
The drain electrode of four NMOS tube M4 is connected to the global bit line node GRBL.Meanwhile the output end connection of the first NAND gate ND1
In the grid of the 4th NMOS tube M4；One of input terminal of the first NAND gate ND1 connects a SRAM (Static
Random-Access Memory, SRAM) circuit module.
It is the input terminal of the delay buffer (buffer delay), described as shown in Figure 1, the present embodiment is further
The grid of another input terminal of nor gate NR and the first PMOS tube M1 connect same low-potential signal GPER.Namely
It says, the first PMOS tube M1, the delay buffer (buffer delay), the nor gate NR receive the GPER simultaneously
Low-potential signal.But the input terminal that the nor gate NR is connected with the delay buffer (buffer delay) receives
Be the GPER low-potential signal after the delay of delay buffer (buffer delay).
Further, another input terminal of the second NAND gate ND2 connects the enable signal EN_ of high potential to the present embodiment
NFSP, that is to say, that as shown in Figure 1, that one of input terminal of the second NAND gate ND2 connects is the nor gate NR
Output end, another input terminal accesses the enable signal EN_NFSP, when circuit work, enable signal EN_
The state of NFSP is the high level state of " 1 " always.
Further, the source electrode of the first PMOS tube M1 connects high potential to the present embodiment；In the present embodiment simultaneously, institute
The grounded drain of the second PMOS tube M2, the source electrode ground connection of the third NMOS tube M3 are stated, grid connects high potential signal YS.More
Further, the non-full swing charger of the invention further includes SRAM circuit module, and the SRAM circuit module is in this reality
The composition applied in example is as follows: referring to Fig. 1, the SRAM circuit module includes: the 5th to the 7th PMOS tube, by six metal-oxide-semiconductor structures
At sram cell (6T CELL)；The connection relationship of 5th to the 7th PMOS tube is as follows: the 5th to the 7th PMOS tube
Grid be connected with each other, and source, drain electrode it is end to end；Since the 5th to the 7th PMOS tube is as switching tube, in this hair
Bright middle source-drain electrode is symmetrical, therefore, one of connection the 6th PMOS tube source and drain in the source-drain electrode of the 5th PMOS tube
One of them in extremely, another pole in the 6th PMOS tube source-drain electrode connects one in the 7th PMOS tube source-drain electrode
A, another in the 7th PMOS tube source-drain electrode is connected to another in the 5th PMOS tube source-drain electrode.
As shown in Figure 1, the connection of the five, the 6th PMOS tube terminates same high potential EN；5th PMOS tube with
Local bitline LBLU is accessed in the connecting pin of 7th PMOS tube and one end of the sram cell；6th PMOS tube and the 7th
The other end of the connecting pin of PMOS tube and the sram cell accesses local bitline LBLBU.
The non-full working principle for swinging charger described in the present embodiment are as follows: if the enable signal EN_NFSP set
Height, so that the circuit module in Fig. 1 dotted line frame starts.Under the mode of " reading ", electricity of the invention is shown as with reference to Fig. 2, Fig. 2
Each signal working timing figure in road.GPRE signal is low potential " 0 ", since the grid of the first PMOS tube M1 connects the low electricity
The GPRE signal of position, therefore, the first PMOS tube M1 can be opened at this time, and the high potential of its source electrode is conducted to the global position
Line node GRBL (global read B-line), the global bit line node GRBL charge.
Since GPRE signal is low potential " 0 ", the low-potential signal is into the excessively described delay buffer (buffer delay)
Enter an input terminal of the nor gate NR afterwards, another input terminal of the nor gate NR then directly receives the low potential of GPRE
Signal, when being all " 0 " due to two input terminals of the nor gate NR, output is flipped, and is exported as " 1 ", therefore, described
The output signal of nor gate NR and the GPRE are just on the contrary, nor gate NR output is high potential.Due to described second with
In two input terminals of NOT gate ND2, one connects the output end of the nor gate NR, another meets the enable signal EN_NFSP,
Therefore, when nor gate NR output is " 1 ".The enable signal EN_NFSP is set to " 1 ", then the second NAND gate ND2
Output is the low potential of " 0 ".Under this state, the second PMOS tube M2 is opened.Since the first PMOS tube M1 is in charged state, and
The second PMOS tube M2 is in discharge condition, therefore, as can be seen that its highest status of a sovereign one from the GRBL waveform diagram of Fig. 2
It is not charged to complete VDD high potential directly.
And the status of a sovereign of the global bit line node GRBL (global read B-line) is according to the delay buffer
The area ratio size of (buffer delay) and first PMOS tube and second PMOS tube.That is described complete
The size of office's bit line node GRBL status of a sovereign depends on the ratio of the area of the first PMOS tube M1 and second PMOS tube.If
The area of the first PMOS tube M1 is less than the area of the second PMOS tube M2, then the status of a sovereign of the global bit line node GRBL
Then can be relatively low, conversely, then can be higher.Preferably, the area of the first PMOS tube M1 is less than the 2nd PMOS to the present embodiment
The area of pipe M2.
And in the initial state, two input terminals of the first NAND gate ND1 are all " 1 ", when the global bit line section
When point GRBL (global read B-line) is high potential, the grid signal YS of the third NMOS tube M3 is set to high potential
Signal, meanwhile, the grid signal EN of the 5th to the 7th PMOS tube is also set to high potential.At this point, the described 5th to the 7th
PMOS tube can turn off, and the local bitline LBLU can discharge in the state of reading " 0 ".When the first NAND gate ND1 wherein
When one input is " 0 ", output becomes " 1 ", since the grid of the 4th NMOS tube M4 is connected to first NAND gate
The output end of ND1, therefore, in the state that the first NAND gate ND1 exports " 1 ", the 4th NMOS tube can be opened.Simultaneously
Since the grid potential of the third NMOS tube is height, third, the 4th NMOS tube can open simultaneously, therefore, the overall situation
The signal of bit line node GRBL can then be spread out of by the third, the 4th NMOS tube, that is to say, that can be by global bit line node
The current potential electric discharge of GRBL is the state of " 0 ".
Referring to fig. 2, in, the waveform diagram of GRBL node and the waveform diagram of local bitline LBLU are compared, by institute
The delay of third, the transmission of the 4th NMOS tube is stated, the electric potential signal of GRBL node declines than the electric potential signal of local bitline LBLU
A little later.Preferably, in the present invention, when the non-full swing charger works normally, the wordline in circuit sets high potential.
Meanwhile SAE signal is set into height.
The GRBL node is made not charge to maximum potential VDD in the present embodiment, in biography " 1 " or " 0 ", dynamic is read
Power will reduce.
Embodiment two
Unlike the embodiments above in the present embodiment, the non-full swing charger in the present embodiment is described
Another input terminal of one NAND gate ND1 connects Another SRAM circuit module.The present embodiment further, the Another SRAM circuit
Module is identical as the SRAM circuit module in previous embodiment.That is, two input terminals of first NAND gate are distinguished
The SRAM circuit module of connection is identical.The SRAM circuit module of another input terminal access of the first NAND gate ND1
Composition and connection relationship are also are as follows: the 5th to the 7th PMOS tube, the sram cell being made of six metal-oxide-semiconductors；Described 5th to the 7th
The connection relationship of PMOS tube are as follows: the grid of the 5th to the 7th PMOS tube is connected with each other, and source, drain electrode are end to end；I.e.
One of them in one of connection the 6th PMOS tube source-drain electrode in the source-drain electrode of 5th PMOS tube, described
Another pole in six PMOS tube source-drain electrodes connects one in the 7th PMOS tube source-drain electrode, the 7th PMOS tube source and drain
Another in extremely is connected to another in the 5th PMOS tube source-drain electrode.The connecting pin of five, the 6th PMOS tube
Meet same high potential EN；5th PMOS tube and the connecting pin of the 7th PMOS tube and one end access office of the sram cell
Bit line LBLD；The other end of the connecting pin and the sram cell of 6th PMOS tube and the 7th PMOS tube accesses part
Bit line LBLBD.
Since the status of a sovereign of the global bit line node GRBL (global read B-line) is according to the delay buffer
The area ratio size of (buffer delay) and first PMOS tube and second PMOS tube.That is described complete
The size of office's bit line node GRBL status of a sovereign depends on the ratio of the area of the first PMOS tube M1 and second PMOS tube.If
The area of the first PMOS tube M1 is less than the area of the second PMOS tube M2, then the status of a sovereign of the global bit line node GRBL
Then can be relatively low, conversely, then can be higher.Preferably, the area of the first PMOS tube M1 is greater than the 2nd PMOS to the present embodiment
The area of pipe M2.
Therefore, it is described it is non-it is complete swing charger working principle in the present embodiment with embodiment one the difference is that:
When circuit opens work, although two input terminals of the first NAND gate ND1 have all accessed identical SRAM circuit module,
But when circuit works normally, one of SRAM circuit module need to be only opened, the present embodiment is in the non-full swing charging
Device work normally when, unlatching be the first NAND gate ND1 another input terminal SRAM circuit module.With reference to Fig. 1, implement
What is opened in example one is the SRAM circuit module of top on the right of the first NAND gate ND1.What the present embodiment was opened is described the
The SRAM circuit module of lower section on the right of one NAND gate ND1.As long as an input terminal input state of the first NAND gate ND1
" 0 ", output are high level " 1 ".The SRAM electricity of another input terminal input of first NAND gate ND1 described in the present embodiment
The effect of road module is identical with embodiment one.
The present invention also provides a kind of using the non-full method for swinging charger and reducing dynamic readout power, and specific steps are such as
Under: Step 1: by the input terminal of the delay buffer, another input terminal of the nor gate and first PMOS tube
Grid accesses same low-potential signal GPER, opens first PMOS tube；By another input terminal of second NAND gate
The enable signal for accessing high potential opens second PMOS tube, charges to the global bit line node GRBL；The step
The grid of first PMOS tube M1 described in rapid connects the GPRE signal of the low potential, therefore, the first PMOS tube M1 meeting at this time
It opens, the high potential of its source electrode is conducted to the global bit line node GRBL (global read B-line), the overall situation
Bit line node GRBL charges.The enable signal EN_NFSP is set to " 1 ", then the second NAND gate ND2 output is
The low potential of " 0 ".Under this state, the second PMOS tube M2 is opened.Since the first PMOS tube M1 is in charged state, and described
Two PMOS tube M2 are in discharge condition, therefore, as can be seen that its highest status of a sovereign never has from the GRBL waveform diagram of Fig. 2
It is charged to complete VDD high potential.
Step 2: the grid of the third NMOS tube is accessed YS high level signal, by the 5th to the 7th PMOS tube
Grid connect high level, so that the local bitline LBLU is discharged.The grid signal YS of the third NMOS tube M3 is set to high electricity
Position signal, meanwhile, the grid signal EN of the 5th to the 7th PMOS tube is also set to high potential.At this point, the described 5th to
Seven PMOS tube can turn off, and the local bitline LBLU can discharge in the state of reading " 0 ".When its of the first NAND gate ND1
In one input be " 0 " when, output become " 1 ", due to the grid of the 4th NMOS tube M4 be connected to described first with it is non-
The output end of door ND1, therefore, in the state that the first NAND gate ND1 exports " 1 ", the 4th NMOS tube can be opened.Together
When since the grid potential of the third NMOS tube is height, third, the 4th NMOS tube can open simultaneously, therefore, described complete
The signal of office bit line node GRBL can then be spread out of by the third, the 4th NMOS tube, that is to say, that can be by global bit line node
The current potential electric discharge of GRBL is the state of " 0 ".
Referring to fig. 2, in, the waveform diagram of GRBL node and the waveform diagram of local bitline LBLU are compared, by institute
The delay of third, the transmission of the 4th NMOS tube is stated, the electric potential signal of GRBL node declines than the electric potential signal of local bitline LBLU
A little later.Preferably, in the present invention, when the non-full swing charger works normally, the wordline in circuit sets high potential.
Meanwhile SAE signal is set into height.
Preferably, when the non-full swing charger works normally, the wordline in circuit sets high potential.And further
Ground, the area of the first PMOS tube M1 are less than the area of the second PMOS tube M2.Or it is further preferred that described first
The area of PMOS tube M1 is greater than the area of the second PMOS tube M2.Due to global bit line node GRBL (the global read
B-line the status of a sovereign) is according to the delay buffer (buffer delay) and first PMOS tube and the 2nd PMOS
The area ratio size of pipe.That is the size of the global bit line node GRBL status of a sovereign depends on the first PMOS tube M1
With the ratio of the area of second PMOS tube.If the area of the first PMOS tube M1 is less than the face of the second PMOS tube M2
Product, then the status of a sovereign of the global bit line node GRBL then can be relatively low, conversely, then can be higher.
The invention enables the GRBL nodes not to charge to maximum potential VDD, and in biography " 1 " or " 0 ", dynamic reads power
It will reduce.
In conclusion the non-full method for swinging charger and reducing dynamic readout power using it of the invention, transmission are non-
The full structure for swinging charger reads power in the case where not influencing efficiency to reduce dynamic.So the present invention effectively overcomes
Various shortcoming in the prior art and have high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (15)
1. a kind of non-full swing charger, which is characterized in that include at least:
First, second PMOS tube；Third, the 4th NMOS tube；Nor gate, the first, second NAND gate and delay buffer；
The delay buffer output end is connect with one of input terminal of the nor gate；The output end of the nor gate connects
It is connected to one of input terminal of second NAND gate；The grid of the output end of second NAND gate and second PMOS tube
Pole connection；The drain electrode of first PMOS tube is connect with the source electrode of second PMOS tube, and the node of connection is global bit line section
Point；The grid of first PMOS tube is connect with the input terminal of the delay buffer；
The drain electrode of the third NMOS tube is connected with the source electrode of the 4th NMOS tube；The drain electrode of 4th NMOS tube connects
In the global bit line node；
The output end of first NAND gate is connected to the grid of the 4th NMOS tube；One of them of first NAND gate
Input terminal connects a SRAM circuit module.
2. non-full swing charger according to claim 1, it is characterised in that: the input terminal of the delay buffer, institute
The grid of another input terminal and first PMOS tube of stating nor gate connects same low-potential signal GPER.
3. non-full swing charger according to claim 2, it is characterised in that: another input terminal of second NAND gate
Connect the enable signal of high potential.
4. non-full swing charger according to claim 3, it is characterised in that: the source electrode of first PMOS tube connects high electricity
Position；The grounded drain of second PMOS tube.
5. non-full swing charger according to claim 4, it is characterised in that: the source electrode of the third NMOS tube is grounded,
Its grid connects YS high potential signal.
6. non-full swing charger according to claim 1 or 5, it is characterised in that: the SRAM circuit module includes:
Five to the 7th PMOS tube, the sram cell being made of six metal-oxide-semiconductors；Wherein the grid of the 5th to the 7th PMOS tube mutually interconnects
Connect, and source, drain electrode it is end to end；The connection of five, the 6th PMOS tube terminates same high potential；5th PMOS tube
Local bitline LBLU is accessed with the connecting pin of the 7th PMOS tube and one end of the sram cell；6th PMOS tube and the
The other end of the connecting pin of seven PMOS tube and the sram cell accesses local bitline LBLBU.
7. non-full swing charger according to claim 6, it is characterised in that: another input of first NAND gate
End connection Another SRAM circuit module.
8. non-full swing charger according to claim 7, it is characterised in that: two input terminals of first NAND gate
The SRAM circuit module being separately connected is identical.
9. non-full swing charger according to claim 8, it is characterised in that: the non-full swing charger works normally
When, the wordline in circuit sets high potential.
10. non-full swing charger according to claim 9, it is characterised in that: the area of the first PMOS tube M1 is small
In the area of the second PMOS tube M2.
11. non-full swing charger according to claim 9, it is characterised in that: the area of the first PMOS tube M1 is big
In the area of the second PMOS tube M2.
12. a kind of use the non-full method for swinging charger and reducing dynamic readout power according to claim 6, feature
Be: this method at least includes the following steps:
Step 1: by the input terminal of the delay buffer, another input terminal of the nor gate and first PMOS tube
Grid access same low-potential signal GPER, open first PMOS tube；By another input of second NAND gate
The enable signal into high potential is terminated, second PMOS tube is opened, charges to the global bit line node GRBL；
Step 2: the grid of the third NMOS tube is accessed YS high level signal, by the grid of the 5th to the 7th PMOS tube
Pole connects high level, and the local bitline LBLU is made to discharge.
13. according to claim 12 using the non-full method for swinging charger and reducing dynamic readout power, feature exists
In: when the non-full swing charger works normally, the wordline in circuit sets high potential.
14. according to claim 12 using the non-full method for swinging charger and reducing dynamic readout power, feature exists
In: the area of the first PMOS tube M1 is less than the area of the second PMOS tube M2.
15. according to claim 12 using the non-full method for swinging charger and reducing dynamic readout power, feature exists
In: the area of the first PMOS tube M1 is greater than the area of the second PMOS tube M2.
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| KR960025036A (en) * | 1994-12-30 | 1996-07-20 | 김주용 | Buffer Enable Signal Generator in Synchronous Memory |
| US20010011913A1 (en) * | 1998-05-20 | 2001-08-09 | Sher Joseph C. | Apparatus and method for generating a clock within a semiconductor device and devices and systems including same |
| CN106205678A (en) * | 2016-07-21 | 2016-12-07 | 宁波大学 | A kind of duplication bit line control circuit |
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