CN110197863A - 发光二极体显示装置及像素安装方法 - Google Patents
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Abstract
本发明涉及显示装置领域,尤其涉及一种发光二极体显示装置及像素安装方法。该方法包括步骤:将导电薄膜层放置在基板上;将多个像素呈矩阵排列且将该矩阵相邻列上的像素相互错位形成像素层;及将该像素层放置在该导电薄膜层上,并施加热力或压力以固化该导电薄膜层及使导电薄膜层中的导电胶颗粒导通,从而将该基板、导电薄膜层及像素层连接为一体。本发明中像素层上错位排列的像素使得像素间的电极之间的距离增大,进而使得像素层上的每个电极能与至少一导电薄膜上的导电胶颗粒连接,从而满足像素层上的电极与导电薄膜层相接合的需求。
Description
技术领域
本发明涉及显示装置领域,尤其涉及一种发光二极体显示装置及像素安装方法。
背景技术
异方性导电胶(Anisotropic Conductive Film,ACF)应用在面板产业。其具备单向导电及胶合固定的功能。主要应用在不适合以高温铅、锡焊接的制程,如软板FPC、LCD模块等电子线路连接,ACF在LCD模块方面的主要应用在TCP/COF封装时连接至LCD之OLB(Outer Lead Bonding),驱动IC连接于TCP/COF载板的ILB(Inner Lead Bonding)等制程。然而,在Micro LED产业上,由于LED像素小,一般异方性导电胶已无法使用,需要开发出超微矩阵列式异方性导电胶,来满足逐渐缩小的电极接合需求。异方性导电胶颗粒在现有材质上存在极限(粒径2.5um),再往下缩小异方性导电胶颗粒的粒径,其压合条件(温度、压力)将变得更加严苛,容易导致硅基板在压合过程中破裂,不利于量产制程,且无法应用于最小单边尺寸3-4um以下之微发光二极管像素。
发明内容
鉴于以上内容,有必要提供一种发光二极体显示装置及像素安装方法以解决现有的异方性导电胶颗粒无法应用于最小单边尺寸3-4um以下之微发光二极管像素的问题。
一种发光二极体显示装置,包括基板、导电薄膜层及像素层,该导电薄膜层形成在该基板上,该像素层设置在该导电薄膜层上,该像素层通过该导电薄膜层与该基板电性连接,该像素层包括多个像素,该些像素相互错位且呈矩阵排列。
优选地,该导电薄膜层为异方性导电胶形成,该导电薄膜层包括呈矩阵排列的导电胶颗粒。
优选地,该像素层上的每一像素包括一个LED管芯,每一LED管芯包括两个电极,该像素层中的像素呈矩阵排列且该矩阵相邻列上的像素相互错位,以使该像素层上发生错位的像素的电极能够与该导电薄膜层上至少一导电胶颗粒连接。
优选地,该像素层上的每一像素包括三个LED管芯,每一LED管芯包括两个电极,每一像素上的三个LED管芯相互错位排列,该像素层上的该些像素呈矩阵排列且该矩阵相邻列上的像素相互错位。
优选地,该导电薄膜层中还填充绝缘聚合物以隔绝该导电薄膜层中的导电胶颗粒之间的电性接触。
优选地,该基板为硅基板或玻璃板。
一种像素安装方法,该方法包括步骤:
将导电薄膜层放置在基板上;
将多个像素呈矩阵排列且将该矩阵相邻列上的像素相互错位形成像素层;及
将该像素层放置在该导电薄膜层上,并施加热力或压力以固化该导电薄膜层及使导电薄膜层中的导电胶颗粒导通,从而将该基板、导电薄膜层及像素层连接为一体。
优选地,该像素层上的每一像素包括一个LED管芯,每一LED管芯包括两个电极。
优选地,该像素层上的每一像素包括三个LED管芯,每一LED管芯包括两个电极,该方法在步骤“将多个像素呈矩阵排列且将该矩阵相邻列上的像素相互错位形成像素层”中还包括:
将该像素层上每一像素上的三个LED管芯相互错位排列。
优选地,该方法还包括步骤:
该导电薄膜层中填充绝缘聚合物以隔绝该导电薄膜层中的导电胶颗粒之间的电性接触。
本案中像素层上错位排列的像素使得像素间的电极之间的距离增大,使得像素层上的每个电极能与至少一导电薄膜层上的导电胶颗粒连接,从而满足像素层上的电极与导电薄膜层相接合的需求。
附图说明
图1为本发明一实施方式中发光二极体显示装置的整体示意图。
图2为本发明一实施方式中导电薄膜层的示意图。
图3为本发明一实施方式中像素层的示意图。
图4为本发明一实施方式中像素的示意图。
图5为本发明另一实施方式中像素层的示意图。
图6为本发明一实施方式中像素安装方法的流程图。
图7为本发明另一实施方式中像素安装方法的流程图。
主要元件符号说明
如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
请参考图1,所示为本发明一实施方式中发光二极体显示装置1的整体示意图。该发光二极体显示装置1包括像素层11、导电薄膜层12及基板13。该像素层11、导电薄膜层12依次形成在该基板13上。也即,该导电薄膜层12形成在该基板13上,该像素层11形成在该导电薄膜层12上。从而,该像素层11通过该导电薄膜层12与该基板13电性连接。本实施方式中,该基板13为硅基板或玻璃板。在其他实施方式中,该基板13还可以为能够弯曲的可挠性、可延展的基板,该基板13包含选自包括聚醚砜(PES)、聚芳酯(PAR)、聚醚酰亚胺(PEI)、聚萘(PEN)、聚对苯二甲酸乙酯(PET)、聚苯硫醚(PPS)、聚芳酯、聚酰亚胺、聚碳酸酯(PC)、三乙酸纤维素(TAC)、乙酸丙酸纤维素(CAP)等之群组的有机材料。
请参考图2,所示为本发明一实施方式中导电薄膜层12的示意图。该导电薄膜层12为异方性导电胶形成。该导电薄膜层12包括呈矩阵排列的导电胶颗粒121。本实施方式中,该导电胶颗粒121为异方性导电胶颗粒。该导电胶颗粒121的粒径为2.5um,该些导电胶颗粒121之间的间距为1.5um。本实施方式中,该导电薄膜层12中还填充绝缘聚合物以隔绝导电薄膜层12中导电胶颗粒121之间的电性接触。
请参考图3,所示为本发明一实施方式中像素层11的示意图。该像素层11包括多个像素2。该些像素2相互错位且呈矩阵排列构成该像素层11。本实施方式中,每一像素2包括一个LED管芯21。每一LED管芯21包括两个电极211。该LED管芯21包括红光管芯、绿光管芯及蓝光管芯。本实施方式,该像素层11上错位排列的像素2使得像素2间的电极211之间的距离增大,使得像素层11上的每个电极211能与至少一导电薄膜层12上的导电胶颗粒121连接,从而满足像素层11上的电极211与导电薄膜层12相接合的需求。
请参考图4,所示为本发明一实施方式中像素2的示意图。其中,图4a为未错位且呈矩阵排列的像素2的示意图,图4b为错位且呈矩阵排列的像素2的示意图。在图4a中,该像素层11中的像素2呈矩阵排列且该矩阵相邻列上的像素未相互错位。由于呈矩阵排列的像素层11中相邻列上的像素2之间未错位,当像素2的尺寸有缩小的需求时,该像素层11上相邻列上的像素2的两个电极211之间的距离会小于导电薄膜层12上的导电胶颗粒121之间的间距,从而导致该像素层11上的电极211不能与导电薄膜层12上至少一导电胶颗粒121连接。进而使像素层11上的电极211不能通过导电薄膜层12与基板13相电性连接。在图4b中,该像素层11中的像素2呈矩阵排列且该矩阵相邻列上的像素2相互错位。由于在矩阵相邻列上的像素2之间相互错位,该相互错位的两像素2中的电极211之间的距离大于没有发生错位的两像素2中的电极211之间的距离,且大于导电薄膜层12上的导电胶颗粒121之间的间距。该像素层11上发生错位的像素2的电极211能够与导电薄膜层12上至少一导电胶颗粒121连接。从而该像素层11上发生错位的像素2的电极211通过导电薄膜层12能够与基板13相电性连接。
请参考图5,所示为本发明另一实施方式中像素层11’的示意图。该像素层11’包括多个像素2’。其中,每一像素2’包括三个LED管芯21’。每一像素2’上的三个LED管芯21’相互错位排列。本实施方式中,每一LED管芯21’包括两个电极211’。该三个LED管芯21’分别为红光管芯、绿光管芯及蓝光管芯。本实施方式中,该像素层11’上的该些像素2’呈矩阵排列且该矩阵相邻列上的像素相互错位。由于该像素层11’上每一像素2’上的三个LED管芯21’相互错位排列且呈矩阵排列的像素2’在相邻列上相互错位,即使在像素2’的尺寸有缩小的需求时,该像素层11’上相邻列上的像素2’的电极211之间的距离及每一像素2’上相邻LED管芯21’之间的距离大于导电薄膜层12上的导电胶颗粒121之间的间距。该像素层11’上的电极211’能够与导电薄膜层12上至少一导电胶颗粒121连接。从而该像素层11’上的电极211通过导电薄膜层12能够与基板13相电性连接。
请参考图6,所示为本发明一实施方式中像素安装方法的流程图。该像素安装方法应用在该发光二极体显示装置1中。根据不同需求,该流程图中步骤的顺序可以改变,某些步骤可以省略或合并。该方法包括如下步骤。
S601:将导电薄膜层12放置在基板13上。
本实施方式中,该基板13可以为玻璃板或硅基板。该导电薄膜层12为异方性导电胶形成。该导电薄膜层12包括呈矩阵排列的导电胶颗粒121。本实施方式中,该导电胶颗粒121为异方性导电胶颗粒。该导电胶颗粒121的粒径为2.5um,该些导电胶颗粒121之间的间距为1.5um。
S602:将多个像素2呈矩阵排列且将该矩阵相邻列上的像素2相互错位形成像素层11。
本实施方式中,每一像素2包括一个LED管芯21。每一LED管芯21包括两个电极211。该LED管芯21包括红光管芯、绿光管芯及蓝光管芯。本实施方式中,由于在矩阵相邻列上的像素2之间相互错位,该像素层11上相邻列上的像素2的两个电极211之间的距离大于导电薄膜层12上的导电胶颗粒121之间的间距。该像素层11上的电极211能够与导电薄膜层12上至少一导电胶颗粒121连接。从而该像素层11上的电极211通过导电薄膜12能够与基板13相电性连接。
S603:将该像素层11放置在该导电薄膜层12上,并施加热力或压力以固化该导电薄膜层12及使导电薄膜层12中的导电胶颗粒121导通,从而将该基板13、导电薄膜层12及像素层11连接为一体。
本实施方式中,该方法在步骤S601之前还包括步骤:
该导电薄膜层12中还填充绝缘聚合物以隔绝该导电薄膜层12中的导电胶颗粒121之间的电性接触。
请参考图7,所示为本发明另一实施方式中像素安装方法的流程图。该方法包括如下步骤。
S701:将导电薄膜层12放置在基板13上。
S702:将多个像素2’呈矩阵排列且将该矩阵相邻列上的像素2’相互错位形成像素层11’。
本实施方式中,每一像素2’包括三个LED管芯21’。每一LED管芯21’包括两个电极211’。
S703:将该像素层11’上每一像素2’上的三个LED管芯21’相互错位排列。
本实施方式中,由于该像素层11’上每一像素2’上的三个LED管芯21’相互错位排列且呈矩阵排列的像素2’在相邻列上相互错位,使得该像素层11’上相邻列上的像素2’的电极211之间的距离及每一像素2’上相邻LED管芯21’之间的距离大于导电薄膜层12上的导电胶颗粒121之间的间距。该像素层11’上的电极211’能够与导电薄膜层12上至少一导电胶颗粒121连接。从而该像素层11’上的电极211通过导电薄膜层12能够与基板13相电性连接。
S704:将该像素层11’放置在该导电薄膜层12上,并施加热力或压力以固化该导电薄膜层12及使导电薄膜层12中的导电胶颗粒121导通,从而将该基板13、导电薄膜层12及像素层11’连接为一体。
本实施方式中,该方法在步骤S701之前还包括步骤:
该导电薄膜层12中还填充绝缘聚合物以隔绝该导电薄膜层12中的导电胶颗粒121之间的电性接触。
以上实施例仅用以说明本发明的技术方案而非限制,尽管参照以上较佳实施例对本发明进行了详细说明,本领域的普通技术人员应当理解,可以对本发明的技术方案进行修改或者等同替换都不应脱离本发明技术方案的精神和范围。
Claims (10)
1.一种发光二极体显示装置,包括基板、导电薄膜层及像素层,该导电薄膜层形成在该基板上,该像素层设置在该导电薄膜层上,该像素层通过该导电薄膜层与该基板电性连接,其特征在于,该像素层包括多个像素,该些像素相互错位且呈矩阵排列。
2.如权利要求1所述的发光二极体显示装置,其特征在于,该导电薄膜层为异方性导电胶形成,该导电薄膜层包括呈矩阵排列的导电胶颗粒。
3.如权利要求2所述的发光二极体显示装置,其特征在于,该像素层上的每一像素包括一个LED管芯,每一LED管芯包括两个电极,该像素层中的像素呈矩阵排列且该矩阵相邻列上的像素相互错位,以使该像素层上发生错位的像素的电极能够与该导电薄膜层上至少一导电胶颗粒连接。
4.如权利要求2所述的发光二极体显示装置,其特征在于,该像素层上的每一像素包括三个LED管芯,每一LED管芯包括两个电极,每一像素上的三个LED管芯相互错位排列,该像素层上的该些像素呈矩阵排列且该矩阵相邻列上的像素相互错位。
5.如权利要求2所述的发光二极体显示装置,其特征在于,该导电薄膜层中还填充绝缘聚合物以隔绝该导电薄膜层中的导电胶颗粒之间的电性接触。
6.如权利要求1所述的发光二极体显示装置,其特征在于,该基板为硅基板或玻璃板。
7.一种像素安装方法,其特征在于,该方法包括步骤:
将导电薄膜层放置在基板上;
将多个像素呈矩阵排列且将该矩阵相邻列上的像素相互错位形成像素层;及
将该像素层放置在该导电薄膜层上,并施加热力或压力以固化该导电薄膜层及使导电薄膜层中的导电胶颗粒导通,从而将该基板、导电薄膜层及像素层连接为一体。
8.如权利要求7所述的像素安装方法,其特征在于,该像素层上的每一像素包括一个LED管芯,每一LED管芯包括两个电极。
9.如权利要求7所述的像素安装方法,其特征在于,该像素层上的每一像素包括三个LED管芯,每一LED管芯包括两个电极,该方法在步骤“将多个像素呈矩阵排列且将该矩阵相邻列上的像素相互错位形成像素层”中还包括:
将该像素层上每一像素上的三个LED管芯相互错位排列。
10.如权利要求7-9任一所述的像素安装方法,其特征在于,该方法还包括步骤:
该导电薄膜层中填充绝缘聚合物以隔绝该导电薄膜层中的导电胶颗粒之间的电性接触。
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