CN110197850A - A kind of splitting bar SiC vertical power MOS device and preparation method thereof - Google Patents
A kind of splitting bar SiC vertical power MOS device and preparation method thereof Download PDFInfo
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- CN110197850A CN110197850A CN201910511754.6A CN201910511754A CN110197850A CN 110197850 A CN110197850 A CN 110197850A CN 201910511754 A CN201910511754 A CN 201910511754A CN 110197850 A CN110197850 A CN 110197850A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims description 15
- 238000000137 annealing Methods 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 230000002146 bilateral effect Effects 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 2
- 229910052681 coesite Inorganic materials 0.000 claims description 2
- 229910052906 cristobalite Inorganic materials 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 229910052682 stishovite Inorganic materials 0.000 claims description 2
- 229910052905 tridymite Inorganic materials 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 2
- 230000004044 response Effects 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 206010036590 Premature baby Diseases 0.000 description 1
- 230000003471 anti-radiation Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract
The invention discloses a kind of splitting bar SiC vertical power MOS devices and preparation method thereof, and using novel division grid structure, convention trench VDMOS device has very big gate-drain overlap capacitance.Due to gate-drain charge Miller effect, when element is in high frequency state, the frequency response of device is substantially reduced, and device performance is caused to lose.Optimize working performance of the VDMOS under high frequency condition, division grid structure (Split gate) is just come into being at this moment, and this configuration reduces gate leakage capacitances, improve the device performance of slot grid VDMOS.Its conducting resistance is not only lower than different MOS, and switching characteristic is more outstanding.
Description
Technical field
The present invention relates to one kind be capable of improving quality factor splitting bar SiC vertical power MOSFET element and its system
Make method, belongs to microelectronics technology.The device it is identical than under conducting resistance have lower reverse transfer capacitance and
Gate-drain charge, and the breakdown voltage of device is improved, improve the safe zone properties of device.
Background technique
SiC has unique physics, chemistry and electrology characteristic, is in high temperature, high frequency, high-power and anti-radiation etc. extremely answer
With the semiconductor material of field with development potential.And SiC power device is high with input impedance, switching speed is fast, work frequency
The high series of advantages such as high pressure resistant of rate, switching power supply, high frequency and in terms of achieve and widely answer
With.1993, J.W.Palmour proposed a kind of vertical-type UMOSFET structure, based on the moment prematurity in carbofrax material
Ion implantation technology, therefore, which eliminates lattice caused by ion implanting by extension and is lost, and makes the device
Proof voltage reaches 330V, and specific on-resistance is 33m Ω cm2, due to during UMOS structure process there are many problems,
Recent years, more researchers have put into the research of VDMOS device.And convention trench VDMOS device has very greatly
Gate-drain overlap capacitance.Due to gate-drain charge Miller effect, when element is in high frequency state, the frequency response of device is significantly
It reduces, device performance is caused to lose.Optimize working performance of the VDMOS device under high frequency condition, divides grid structure (Split
Gate it) just comes into being at this moment, grid structure is divided into two, this configuration reduces gate leakage capacitances, improve slot grid VDMOS's
Device performance.Its conducting resistance is not only lower than different MOS devices, and switching characteristic is more outstanding.
Summary of the invention
In order to more effectively improve the quality factor of device and not consume the premise than conducting resistance and breakdown voltage
Under, the present invention provides a kind of splitting bar structural improvement SiC vertical power MOS device and preparation method thereof.
The technical scheme is that
A kind of splitting bar SiC vertical power MOS device, which is characterized in that including N+/N- type SiC substrate substrate, composition is
It is equipped with N+ substrate layer in the bottom of the drift region N-, symmetrical P-well area is equipped in the upper surface of drift region N-, in two P-wells
The opposite facing side in the top in area is respectively provided with the access area P+, N+ source region is equipped in the opposite side in two access areas P+, two
There are P-WELL well regions for the opposite side of a N+ source region；Gate insulating layer is equipped with the upper surface of between two N+ source regions,
The upper surface of the N+ source region and the access area P+ are equipped with source electrode, in the upper surface of gate insulating layer bilateral symmetry and are arranged at intervals with two
A gate electrode；Interconnection electrode is equipped in the upper surface of described gate electrode and source electrode.
A kind of preparation method of the splitting bar SiC vertical power MOS device, which is characterized in that including following step
It is rapid:
(1) N+/N- type SiC substrate substrate is chosen；
(2) P-well area is formed by ion implanting；
(3) ion implanting forms the access area P+；
(4) ion implanting forms N+ source region；
(5) unified to carry out high annealing after ion implanted region formation；
(6) gate insulation layer is prepared；
(7) source electrode is prepared；
(8) gate electrode is prepared；
(9) interconnection electrode is prepared.
The invention has the advantages that division grid structure reduces gate leakage capacitance, the device performance of slot grid VDMOS is improved.?
Under conditions of not sacrificing conducting resistance and breakdown voltage, better switching characteristic is obtained.
Detailed description of the invention
Fig. 1 is the schematic cross-sectional view of splitting bar SiC vertical power MOS device of the present invention；
Fig. 2 is the process flow chart of splitting bar SiC vertical power MOS device preparation method of the present invention.
Specific embodiment
Referring to Fig. 1, a kind of structure of splitting bar SiC vertical power MOS device of the present invention, including N+/N- type SiC substrate
Substrate 1, constituting is to be equipped with N+ substrate layer in the bottom of the drift region N-, is equipped with symmetrical P-well in the upper surface of drift region N-
Area is respectively provided with the access area P+ in the opposite facing side in top in Liang Ge P-well area, sets in the opposite side in two access areas P+
There is N+ source region, there are P-WELL well regions in the opposite side of two N+ source regions；It is equipped with the upper surface of between two N+ source regions
Gate insulating layer (SiO2) 2, source electrode 4 is equipped in the upper surface of the N+ source region and the access area P+.In the upper surface of the gate insulating layer
Bilateral symmetry is simultaneously arranged at intervals with two gate electrodes 3；Interconnection electrode 5 is equipped in the upper surface of described gate electrode 3 and source electrode 4.
Referring to fig. 2, the preparation method of splitting bar SiC vertical power MOS device described in present invention one kind, including it is following
Step:
(1) N+/N- type SiC substrate substrate is chosen；
(2) P-well area (P-WELL) is formed by ion implanting: the well depth in P-well area is 1 μm, concentration 5e+17cm-3。
(3) ion implanting forms the access area P+: forming the access area P+ using multiple ion implanting, junction depth is 0.5 μm, concentration
Greater than 5e+19cm-3。
(4) ion implanting forms N+ source region: forming N+ source region using multiple ion implanting, junction depth is 0.5 μm, and concentration is greater than
5e+19cm-3。
(5) after ion implanted region formation, the unified high annealing that carries out: annealing temperature is 1600 DEG C, and the time is
30min。
(6) prepare gate insulation layer: oxidation forms SiO2Layer, with a thickness of 50nm, oxidization time is 10 hours, temperature 1050
℃；Then it carries out annealing in NO atmosphere, temperature is 1075 DEG C, and the time is 2 hours.
(7) prepare source electrode: after sputtering source electrode metal layer, removing forms source electrode, and after being deposited at 750 DEG C
5 minutes formation Ohmic contacts of short annealing.
(8) prepare gate electrode: sputtering barrier metal layer, removing form gate electrode figure.
(9) prepare interconnection electrode: sputtering interconnecting metal layer, removing form interconnection electrode.
Emulation testing, simulation result have been carried out to SiC splitting bar-MOS device and the common VDMOS device of SiC of the invention
Parameter such as following table.
| SG-MOS | Common VDMOS | |
| Breakdown voltage (V) | 1254 | 1268 |
| Threshold voltage (V) | 3.4 | 3.5 |
| Rds, on(m Ω) 25 DEG C | 168 | 165 |
| Rds, on(m Ω) 150 DEG C | 221 | 290 |
| Qgd(nC) | 6.7 | 12.5 |
| FOM<R×Q>( mΩ) 25℃ | 1126 | 2063 |
| FOM<R×Q>( mΩ) 150℃ | 1481 | 3625 |
As can be seen from the table, compared with conventional common SiC vertical power MOS device, breakdown voltage also threshold voltage
And do not lost than conducting resistance, but its Qgd and FOM are greatly reduced, and illustrate that this structure can be not
The switching characteristic of device is greatly improved under conditions of loss breakdown voltage and threshold voltage.
Splitting bar of the invention is the division grid structure based on SiC material, and process variations are very big, and pervious splitting bar is base
In Si material, it is feasible that this valve, which proves and simulates the technique of the division gate device based on SiC material, and compared to conventional
SiC vertical power MOS device there is better quality factor characteristic, switching characteristic, and do not lose its conducting resistance and breakdown
Voltage.
Claims (10)
1. a kind of splitting bar SiC vertical power MOS device, which is characterized in that including N+/N- type SiC substrate substrate, constitute
It is to be equipped with N+ substrate layer in the bottom of the drift region N-, symmetrical P-well area is equipped in the upper surface of drift region N-, in two P-
The opposite facing side in the top of well region is respectively provided with the access area P+, is equipped with N+ source region in the opposite side in two access areas P+,
There are P-WELL well regions for the opposite side of two N+ source regions；Gate insulating layer is equipped with the upper surface of between two N+ source regions,
Source electrode is equipped in the upper surface of the N+ source region and the access area P+；In the upper surface of gate insulating layer bilateral symmetry and it is arranged at intervals with
Two gate electrodes；Interconnection electrode is equipped in the upper surface of described gate electrode and source electrode.
2. splitting bar SiC vertical power MOS device according to claim 1, which is characterized in that the gate insulator
Layer is SiO2。
3. a kind of preparation method of splitting bar SiC vertical power MOS device described in claim 1, which is characterized in that including
Following steps:
(1) N+/N- type SiC substrate substrate is chosen；
(2) P-well area is formed by ion implanting；
(3) ion implanting forms the access area P+；
(4) ion implanting forms N+ source region；
(5) unified to carry out high annealing after ion implanted region formation；
(6) gate insulation layer is prepared；
(7) source electrode is prepared；
(8) gate electrode is prepared；
(9) interconnection electrode is prepared.
4. preparation method according to claim 3, which is characterized in that in the step (2), the well depth in P-well area is 1 μ
M, concentration 5e+17cm-3。
5. preparation method according to claim 3, which is characterized in that in the step (3), using multiple ion implanting
The access area P+ is formed, junction depth is 0.5 μm, and concentration is greater than 5e+19cm-3。
6. according to claim, preparation method described in 3, which is characterized in that in the step (4), infused using multiple ion
Enter to be formed N+ source region, junction depth is 0.5 μm, and concentration is greater than 5e+19cm-3。
7. preparation method according to claim 3, which is characterized in that in the step (5), annealing temperature 1600
DEG C, time 30min.
8. preparation method according to claim 3, which is characterized in that in the step (6), oxidation forms grid gate insulation
Layer, with a thickness of 50nm, oxidization time is 10 hours, and temperature is 1050 DEG C；Then it carries out annealing in NO atmosphere, temperature 1075
DEG C, the time is 2 hours.
9. preparation method according to claim 3, which is characterized in that in the step (7), sputtering source electrode metal layer
Afterwards, removing forms source electrode, and is deposited rear short annealing and forms Ohmic contact.
10. preparation method according to claim 3, which is characterized in that in the step (8), sputter barrier metal layer, stripping
From formation gate electrode figure；In the step (9), interconnecting metal layer is sputtered, removing forms interconnection electrode.
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| CN201910511754.6A CN110197850A (en) | 2019-06-13 | 2019-06-13 | A kind of splitting bar SiC vertical power MOS device and preparation method thereof |
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| CN201910511754.6A CN110197850A (en) | 2019-06-13 | 2019-06-13 | A kind of splitting bar SiC vertical power MOS device and preparation method thereof |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150053998A1 (en) * | 2012-03-30 | 2015-02-26 | Fuji Electric Co., Ltd. | Semiconductor device |
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- 2019-06-13 CN CN201910511754.6A patent/CN110197850A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150053998A1 (en) * | 2012-03-30 | 2015-02-26 | Fuji Electric Co., Ltd. | Semiconductor device |
Non-Patent Citations (2)
| Title |
|---|
| KIJEONG HAN ET AL: "Operation of 1.2-kV 4H-SiC Accumulation and Inversion Channel Split-Gate (SG) MOSFETs at Elevated Temperatures", 《IEEE TRANSACTIONS ON ELECTRON DEVICES》 * |
| KIJEONG HAN ET AL: "Split-Gate 1.2-kV 4H-SiC MOSFET: Analysis and Experimental Validation", 《IEEE ELECTRON DEVICE LETTERS》 * |
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