CN110197637A

CN110197637A - Scanning circuit, display panel and driving method of display panel

Info

Publication number: CN110197637A
Application number: CN201910580872.2A
Authority: CN
Inventors: 戴文君
Original assignee: Shanghai Tianma Microelectronics Co Ltd
Current assignee: Shanghai Tianma Microelectronics Co Ltd
Priority date: 2019-06-29
Filing date: 2019-06-29
Publication date: 2019-09-03
Anticipated expiration: 2039-06-29
Also published as: CN110197637B

Abstract

The invention discloses a scanning circuit, a display panel and a driving method of the display panel. The scanning circuit includes: the input module is respectively electrically connected with the first input end and the first clock signal end, and the first node control module is respectively electrically connected with the second input end and the first clock signal end. Compared with the prior art, the embodiment of the invention is beneficial to avoiding that the transistor in the input module is always in a voltage bias state and the transistor in the first node control module is always in a voltage bias state, thereby being beneficial to avoiding the working threshold voltage deviation of the transistors in the input module and the first node control module under severe working conditions. Therefore, the embodiment of the invention is beneficial to improving the working stability of the scanning circuit, thereby being beneficial to improving the reliability of the display panel.

Description

A kind of driving method of scanning circuit, display panel and display panel

Technical field

The present embodiments relate to the drives of display technology more particularly to a kind of scanning circuit, display panel and display panel Dynamic method.

Background technique

With the continuous development of display technology, display panel application it is also more and more extensive, for example, display panel applications in The products such as mobile phone, computer, tablet computer, e-book and information enquiry machine, additionally can be applied to instrument class display (such as Vehicular display device) and the control panel of smart home etc..

Existing display panel successively scans each row pixel conducting by scanning circuit, to show picture.Work as display surface When plate is applied to instrument class display, since application environment is more severe (for example, hot environment), to the reliability of display panel More stringent requirements are proposed.However, each transistor of existing scan drive circuit is being easy to appear operation threshold variation The problem of, i.e., there is deviation in the threshold voltage of different transistors.

Summary of the invention

The present invention provides the driving method of a kind of scanning circuit, display panel and display panel, to reduce the work of transistor Make threshold voltage shift.

In a first aspect, the embodiment of the invention provides scanning circuit, which includes:

Input module, the input module are electrically connected with first input end, the first clock signal terminal and first node, are used for The current potential of the first node is controlled according to the signal of the first input end and first clock signal terminal；

First node control module, the first node control module and first clock signal terminal, second clock are believed Number end, the electrical connection of the second input terminal, the first power end, for according to the first power end, the first clock signal terminal, it is described second when Clock signal end, second input terminal signal control the current potential of the first node；

Second node control module, the second node control module and the second clock signal end, second node electricity Connection, for controlling the current potential of the second node according to the signal of the second clock signal end；

Node cross complaint module, the node cross complaint module and first power end, the first node and described the The electrical connection of two nodes is the second current potential, Huo Zhegen for second node described in the first control of Electric potentials according to the first node First node described in the first control of Electric potentials according to the second node is the second current potential；

Output module, the output module and third clock signal terminal, the first node and scanning signal output end electricity Connection exports the signal of the third clock signal terminal for the current potential according to the first node defeated to the scanning signal Outlet；

Output keeps module, and the output keeps module to be electrically connected with the second node, second source end, for keeping The output of the scanning signal output end.

Second aspect, the embodiment of the invention also provides display panel, which includes multiple as the present invention is any Scanning circuit described in embodiment, the first clock cable, second clock signal wire, third clock cable, the 4th clock letter Number line, the 5th clock cable, the 6th clock cable, the first power signal line, second source signal wire, the first enabling signal Line, the second enabling signal line and multi-strip scanning line；

Multiple scanning circuit cascade connections, the first input end of scanning circuit described in the first order and first starting Signal wire electrical connection；First input of scanning circuit described in the scanning signal output end and next stage of scanning circuit described in upper level End electrical connection；Second input terminal of scanning circuit described in afterbody is electrically connected with the second enabling signal line；Next stage institute The scanning signal output end for stating scanning circuit is electrically connected with the second input terminal of scanning circuit described in upper level；

First clock signal terminal of scanning circuit described in odd level is electrically connected with first clock cable, when second Clock signal end is electrically connected with the second clock signal wire, and third clock signal terminal is electrically connected with the third clock cable； First clock signal terminal of scanning circuit described in even level is electrically connected with the 4th clock cable, second clock signal end It is electrically connected with the 5th clock cable, third clock signal terminal is electrically connected with the 6th clock cable；

First power end of the scanning circuit is electrically connected with first power signal line, the second source end and institute State the electrical connection of second source signal wire；The multi-strip scanning line is electrically connected with the scanning signal output end of the corresponding scanning circuit It connects

The third aspect, the embodiment of the invention also provides a kind of driving method of display panel, the drivings of the display panel Method is suitable for display panel provided by any embodiment of the invention.The driving method of the display panel includes:

In the first scan phase, the first clock cable of Xiang Suoshu sends the first clock signal, Xiang Suoshu second clock letter Number line sends second clock signal, and Xiang Suoshu third clock cable sends third clock signal, the 4th clock signal of Xiang Suoshu Line sends the 4th clock signal, and the 5th clock cable of Xiang Suoshu sends the 5th clock signal, the 6th clock cable of Xiang Suoshu The 6th clock signal is sent, the first power signal line of Xiang Suoshu sends the first power supply signal, Xiang Suoshu second source signal wire hair Second source signal is sent, Xiang Suoshu the first enabling signal line sends the first enabling signal；Wherein, first clock signal and institute State the 4th clock signal on the contrary, the second clock signal and the 5th clock signal on the contrary, the third clock signal with 6th clock signal is opposite；

Multiple scanning circuit forward directions are driven to send scanning signal to a plurality of scan line step by step.

The embodiment of the present invention is by providing a kind of new scanning circuit, wherein input module respectively with first input end and The electrical connection of first clock signal terminal, first node control module are electrically connected with the second input terminal and the first clock signal terminal respectively, Compared with prior art, be conducive to avoid the transistor in input module to be in the state of voltage bias always, and be conducive to The transistor in first node control module is avoided to be in the state of voltage bias always, to be conducive to avoid in harsh Under the conditions of, the operation threshold variation of input module and the transistor in first node control module.Therefore, the present invention is implemented Example is conducive to be promoted the stability of scanning circuit work, to be conducive to be promoted the reliability of display panel.

Detailed description of the invention

Fig. 1 is the transfer characteristic schematic diagram of the transistor in a kind of existing scanning circuit；

Fig. 2 is a kind of structural schematic diagram of scanning circuit provided in an embodiment of the present invention；

Fig. 3 is a kind of time diagram of scanning circuit provided in an embodiment of the present invention；

Fig. 4 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention；

Fig. 5 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention；

Fig. 6 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention；

Fig. 7 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention；

Fig. 8 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention；

Fig. 9 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention；

Figure 10 is a kind of structural schematic diagram of display panel provided in an embodiment of the present invention；

Figure 11 is a kind of driver' s timing schematic diagram of display panel provided in an embodiment of the present invention；

Figure 12 is a kind of flow diagram of the driving method of display panel provided in an embodiment of the present invention；

Figure 13 is the flow diagram of the driving method of another display panel provided in an embodiment of the present invention.

Specific embodiment

The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.

Fig. 1 is the transfer characteristic schematic diagram of the transistor in a kind of existing scanning circuit.Referring to Fig. 1, curve 110 be with The transistor characteristor characteristic curve of higher level's shift signal input terminal electrical connection, curve 120 are to be electrically connected with junior shift signal input terminal Transistor characteristor characteristic curve.As seen from Figure 1, electric with first input end in scanning circuit after display panel works 1000h The transistor of connection and from the second input terminal electrical connection the threshold voltage of transistor it is different, the threshold voltage of transistor occurs Drift phenomenon, and under the high temperature conditions, the threshold voltage shift problem of transistor is more serious.Through inventor the study found that going out The reason of showing this problem is that the transistor being electrically connected with first input end in scanning circuit is in first voltage biasing State, the transistor being electrically connected with the second input terminal is in the state of second voltage biasing, and first voltage and second voltage are not Together, thus the problem of causing the operation threshold variation of transistor.And since the operation threshold voltage of transistor is inclined It moves, the phenomenon that scanning circuit is easy to appear excessive leakage current or no pulse is resulted in, to affect the trust of display panel Property.

In view of this, the embodiment of the invention provides a kind of scanning circuits.Fig. 2 is that one kind provided in an embodiment of the present invention is swept The structural schematic diagram of scanning circuit.Referring to fig. 2, which includes: input module 100, first node control module 200, Two node control modules 300, node cross complaint module 400, output module 500 and output keep module 600.

Input module 100 is electrically connected with first input end g0, the first clock signal terminal clk1 and first node N1, is used for root According to the current potential of the signal of first input end g0 and the first clock signal terminal clk1 control first node N1.First node controls mould Block 200 and the first clock signal terminal clk1, second clock signal end clk2, the second input terminal g2, the first power end vgl1 are electrically connected It connects, for according to the first power end vgl1, the first clock signal terminal clk1, second clock signal end clk2, the second input terminal g2 Signal control first node N1 current potential.Second node control module 300 and second clock signal end clk2, second node N2 Electrical connection, for controlling the current potential of second node N2 according to the signal of second clock signal end clk2.Node cross complaint module 400 with First power end vgl1, first node N1 and second node N2 electrical connection, for the first current potential control according to first node N1 Second node N2 processed be the second current potential, or according to the first control of Electric potentials first node N1 of second node N2 be the second current potential. Output module 500 is electrically connected with third clock signal terminal clk3, first node N1 and scanning signal output end g1, for according to the The current potential of one node N1 exports the signal of third clock signal terminal clk3 to scanning signal output end g1.Output keeps module 600 are electrically connected with second node N2, second source end vgl2, for keeping the output of scanning signal output end g1.

Fig. 3 is a kind of time diagram of scanning circuit provided in an embodiment of the present invention.Referring to Fig. 3, illustratively, first Supply voltage and second source voltage are low level.The driving method of the scanning circuit includes first stage T1, second stage T2, phase III T3, fourth stage T4, the 5th stage T5, the 6th stage T6, the 7th stage T7 and the 8th stage T8.

First stage T1, first input end g0 input high level, the second input terminal g2 input low level, the first clock signal Hold clk1 input low level, second clock signal end clk2 input high level, third clock signal terminal clk3 input low level.It is defeated Enter module 100 to be connected in response to the high level that first input end g0 is inputted, the low level that the first clock signal terminal clk1 is inputted It is conducted to first node N1, control first node N1 is low level.First node control module 200 responds the second input terminal g2's The high level of low level and second clock signal end clk2 and be connected, the low level of the first power end vgl1 is conducted to first segment Point N1, control first node N1 are low level.Second node control module 300 responds the low level of the first clock signal terminal clk1 And it turns off.Node cross complaint module 400 is turned off in response to the low level of first node N1 and second node N2.500 sound of output module It answers the low level of first node N1 and turns off.Output keeps module 600 to turn off in response to the low level of second node N2.Due to defeated The memory action of module 500 and late-class circuit capacitor out, scanning signal output end g1 maintain low level on last stage.

Second stage T2, first input end g0 input high level, the second input terminal g2 input low level, the first clock signal Hold clk1 input high level, second clock signal end clk2 input low level, third clock signal terminal clk3 input low level.It is defeated Enter module 100 to be connected in response to the high level of first input end g0, the high level of the first clock signal terminal clk1 is conducted to One node N1, since the energy storage of output module 500 acts on, the current potential of first node N1 is gradually risen, but output module 500 is still located In off state.First node control module 200 respond the second input terminal g2 and second clock signal end clk2 low level and Shutdown.Second node control module 300 responds the first clock signal terminal clk1 input high level and is connected.At the same time, node Cross complaint module 400 in response to first node N1 high level and be connected, the low level of the first power end vgl1 is conducted to the second section Point N2, control second node N2 are low level.Since the current potential of first node N1 is not enough to output module 500 during rising Conducting, output module 500 are still off state.Due to the memory action of output module 500 and late-class circuit capacitor, scanning signal Output end g1 maintains low level on last stage.

Phase III T3, first input end g0 input low level, the second input terminal g2 input low level, the first clock signal Hold clk1 input high level, second clock signal end clk2 input low level, third clock signal terminal clk3 input high level.The The current potential raising of one node N1 is enough that output module 500 is connected, and the high level of third clock signal is connected output module 500 To scanning signal output end g1.What the high level and output module 500 of first node N1 response scanning signal output end g1 stored High level, voltage continue to increase.Input module 100 in response to first input end g0 low level and turn off.First node control Module 200 responds the low level of the second input terminal g2 and second clock signal end clk2 and turns off.Second node control module 300 It responds the first clock signal terminal clk1 input high level and is connected.At the same time, node cross complaint module 400 responds first node N1 High level and be connected, the low level of the first power end vgl1 is conducted to second node N2, control second node N2 is low electricity It is flat.7th transistor in response to second node N2 low level and turn off.Scanning signal output end g1 exports high level.

Fourth stage T4, first input end g0 input low level, the second input terminal g2 input high level, the first clock signal Hold clk1 input high level, second clock signal end clk2 input low level, third clock signal terminal clk3 input low level.It is defeated Enter module 100 to turn off in response to the low level of first input end g0.First node control module 200 respond the second input terminal g2 and The high level of second clock signal end clk2 and be connected, first node control module 200 is by the height of the first clock signal terminal clk1 Level is conducted to first node N1, and control first node N1 is high level.Second node control module 300 responds the first clock letter Number end clk1 input high level and be connected.At the same time, node cross complaint module 400 in response to first node N1 high level and lead It is logical, the low level of the first power end vgl1 is conducted to second node N2, control second node N2 is low level.7th transistor In response to second node N2 low level and turn off.Output module 500 in response to first node N1 high level and be connected, when by third The low level of clock signal end clk3 is conducted to scanning signal output end g1.First node N1 responds the low of scanning signal output end g1 The high level that level and output module 500 store, voltage reduce.To sum up, scanning signal output end g1 exports low level.

5th stage T5, first input end g0 input low level, the second input terminal g2 input high level, the first clock signal Hold clk1 input low level, second clock signal end clk2 input high level, third clock signal terminal clk3 input low level.It is defeated Enter module 100 to turn off in response to the low level of first input end g0.First node control module 200 respond the second input terminal g2 and The high level of second clock signal end clk2 and be connected, first node control module 200 is low by the first clock signal terminal clk1's Level is conducted to first node N1, and control first node N1 is low level.Second node control module 300 responds the first clock letter Number end clk1 input low level and second node N2 low level and turn off.Node cross complaint module 400 respond first node N1 and The low level of second node N2 and turn off.Output module 500 in response to first node N1 low level and turn off.To sum up, scanning letter Number output end g1 exports low level.

6th stage T6, first input end g0 input low level, the second input terminal g2 input low level, the first clock signal Hold clk1 input low level, second clock signal end clk2 input high level.Input module 100 responds the low of first input end g0 Level and turn off.First node control module 200 in response to second clock signal end clk2 high level and be connected, by the first power supply The low level of end vgl1 is conducted to first node N1, and control first node N1 is low level.Second node control module 300 responds First clock signal terminal clk1 input low level and turn off.Node cross complaint module 400 responds first node N1 and second node N2 Low level and turn off.Output module 500 in response to first node N1 low level and turn off.Due to output module 500 and rear class The memory action of circuit capacitance, scanning signal output end g1 maintain low level on last stage.

7th stage T7, first input end g0 input low level, the second input terminal g2 input low level, the first clock signal Hold clk1 input high level, second clock signal end clk2 input low level.Input module 100 responds the low of first input end g0 Level and turn off.First node control module 200 respond the second input terminal g2 and second clock signal end clk2 low level and Shutdown.Second node control module 300 responds the first clock signal terminal clk1 input high level and is connected, by the first clock signal The high level of end clk1 is conducted to second node N2, and control second node N2 is high level.The response of node cross complaint module 400 second The high level of node N2 and be connected, the low level of the first power end vgl1 is conducted to first node N1, controls first node N1 For low level.Output module 500 in response to first node N1 low level and turn off.Output keeps module 600 to respond second node The high level of N2 and be connected, the low level of second source end vgl2 is conducted to scanning signal output end g1, scanning signal output G1 is held to maintain low level output.

8th stage T8, first input end g0 input low level, the second input terminal g2 input low level, the first clock signal Hold clk1 input low level, second clock signal end clk2 input high level.Input module 100 responds the low of first input end g0 Level and turn off.First node control module 200 in response to second clock signal end clk2 high level and be connected, by the first power supply The low level of end vgl1 is conducted to first node N1, and control first node N1 is low level.Second node control module 300 responds The high level of first clock signal terminal clk1 input low level and second node N2 and be connected, the current potential of second node N2 is drawn Low, control second node N2 is low level.Node cross complaint module 400 in response to the low level of first node N1 and second node N2 and Shutdown.Output module 500 in response to first node N1 low level and turn off.Output keeps module 600 to respond second node N2's Low level and turn off.Due to the memory action of output module 500 and late-class circuit capacitor, scanning signal output end g1 maintains upper one The low level in stage.

And so on, after the 8th stage T8, scanning circuit repeats the work shape of the 7th stage T7 and the 8th stage T8 State, the current potential of second node N2 and the level state of the first clock signal terminal clk1 are consistent, and are height in second node N2 When level, output keeps module 600 to be connected, and maintains the low level of scanning signal output end g1.Therefore, the embodiment of the present invention is realized To the shift function of the pulse signal of first input end g0 input, i.e. forward scan.It should be noted that the embodiment of the present invention The pulse signal of second input terminal g2 can also be carried out displacement output, i.e. reverse scan, this field skill by the scanning circuit of offer Art personnel are appreciated that the driving process of reverse scan is similar with forward scan, repeat no more.

The embodiment of the present invention is by providing a kind of new scanning circuit, wherein input module 100 respectively with first input end G0 and the first clock signal terminal clk1 electrical connection, first node control module 200 respectively with the second input terminal g2 and the first clock Signal end clk1 electrical connection, compared with prior art, is conducive to avoid the transistor in input module 100 to be in voltage always inclined The state set, and be conducive to avoid the transistor in first node control module 200 to be in the state of voltage bias always, from And be conducive to avoid under poor working conditions, the work of input module 100 and the transistor in first node control module 200 Threshold voltage shift.Therefore, the embodiment of the present invention is conducive to be promoted the stability of scanning circuit work, to be conducive to be promoted aobvious Show the reliability of panel.

It should be noted that in the above-described embodiments, schematically illustrating the first power end vgl1 and second source end Vgl2 input low level, not limitation of the invention.In other embodiments, the first power end can also be set as needed Vgl1 and second source end vgl2 input high level, can according to need set in practical applications.

Fig. 4 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention.Referring to fig. 4, in above-mentioned each reality On the basis of applying example, optionally, input module 100 includes second brilliant including the first transistor M1, first node control module 200 Body pipe M2 and third transistor M3.

The grid of the first transistor M1 is electrically connected with first input end g0, the first pole of the first transistor M1 and the first clock Signal end clk1 electrical connection, the second pole of the first transistor M1 is electrically connected with first node N1.The grid of second transistor M2 with Second input terminal g2 electrical connection, the first pole of second transistor M2 are electrically connected with the first clock signal terminal clk1, second transistor The second pole of M2 is electrically connected with first node N1.The grid of third transistor M3 is electrically connected with second clock signal end clk2, the The first pole of three transistor M3 is electrically connected with the first power end vgl1, and the second pole and the first node N1 of third transistor M3 is electrically connected It connects.

Wherein, the first transistor M1 and second transistor M2 is symmetrical arranged, and is inputted respectively by first input end g0 and second Hold the voltage control of g2, and the not connected power end in the both ends of the first transistor M1 and second transistor M2, therefore, first crystal Pipe M1 and second transistor M2 avoids the negative of state in voltage bias and the first transistor M1 and second transistor M2 It carries also identical.The embodiment of the present invention effectively improves the operation threshold variation of the first transistor M1 and second transistor M2 Phenomenon reduces operation threshold voltage drift.

Fig. 5 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention.Referring to Fig. 5, in above-mentioned each reality On the basis of applying example, optionally, second node control module 300 includes the 4th transistor M4 and the 5th transistor M5.

The grid of 4th transistor M4 is electrically connected with its first pole, the first pole of the 4th transistor M4 and the first clock signal Clk1 electrical connection is held, the second pole of the 4th transistor M4 is electrically connected with second node N2.The grid of 5th transistor M5 and its The electrical connection of one pole, the first pole of the 4th transistor M4 are electrically connected with second node N2, the second pole and first of the 5th transistor M5 Clock signal terminal clk1 electrical connection.

Wherein, the 4th transistor M4 can be equivalent to anode and connect with the first clock signal terminal clk1, cathode and the second section The diode of point N2 connection, the 5th transistor M5 can be equivalent to anode and connect with second node N2, and cathode and the first clock are believed The diode of number end clk1 connection, therefore, the 4th transistor M4 and the 5th transistor M5 constitute the diode that inverse parallel connects. When the first clock signal terminal clk1 is high level, can control second node N2 is high level.Setting of the embodiment of the present invention the Two node control modules 300 are equivalent to the diode of inverse parallel connection, avoid using other signal line traffic control second node Control module 300, to advantageously reduce the quantity of signal wire.

Fig. 6 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention.Referring to Fig. 6, in above-mentioned each reality On the basis of applying example, optionally, node cross complaint module 400 includes the 6th transistor M6 and the 7th transistor M7.

The grid of 6th transistor M6 is electrically connected with first node N1, the first pole of the 6th transistor M6 and the first power end Vgl1 electrical connection, the second pole of the 6th transistor M6 is electrically connected with the grid of the 7th transistor M7.The first of 7th transistor M7 Pole is electrically connected with the first power end vgl1, and the second pole of the 7th transistor M7 is electrically connected with first node N1.

Wherein, control of the 6th transistor M6 by first node N1, control of the 7th transistor M7 by second node N2.When One in first node N1 and second node N2 when being high level, node cross complaint module 400 is connected, by another node control For low level.Therefore, the case where embodiment of the present invention avoids first node N1 and second node N2 while being high level, thus It avoids output module 500 and output keeps module 600 to simultaneously turn on, so that scanning circuit exports terminal shortcircuit, it is ensured that scanning The stability of signal output end g1 output signal.

Fig. 7 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention.Referring to Fig. 7, in above-mentioned each reality On the basis of applying example, optionally, output module 500 includes the 8th transistor M8 and first capacitor C1.

The grid of 8th transistor M8 is electrically connected with first node N1, and the first pole of the 8th transistor M8 and third clock are believed Number end clk3 electrical connection, the second pole of the 8th transistor M8 is electrically connected with scanning signal output end g1.The first of first capacitor C1 Pole is electrically connected with the grid of the 8th transistor M8, and the second pole of first capacitor C1 is electrically connected with the second pole of the 8th transistor M8.

Wherein, the 8th transistor M8 is driving transistor, needs to have stronger driving capability, therefore the 8th transistor M8 Need to occupy biggish area.An output module 500 can be only arranged in the embodiment of the present invention, and in the output module 500 only The shift function for driving transistor that scanning circuit can be realized including one, therefore, the embodiment of the present invention are conducive to reduce driving The quantity of transistor, reduces the chip area of display panel, to be conducive to the narrow frame design of display panel.In addition, first Capacitor C1 is set between first node N1 and scanning signal output end g1, and first node N1 and scanning signal can be kept to export Hold the potential stability of g1.And the embodiment of the present invention only needs that a capacitor is arranged in output module 500, to be conducive to Reduce the load of scanning circuit.

Fig. 8 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention.Referring to Fig. 8, in above-mentioned each reality On the basis of applying example, optionally, it includes the 9th transistor M9 that output, which keeps module 600,.The grid and second of 9th transistor M9 Node N2 electrical connection, the first pole of the 9th transistor M9 are electrically connected with second source end vgl2, the second pole of the 9th transistor M9 It is electrically connected with scanning signal output end g1.

Wherein, when output module 500 turns off, output keeps module 600 that can be connected, by the electricity of second source end vgl2 Position is transmitted to scanning signal output end g1, to keep scanning signal output end g1 current potential.The embodiment of the present invention is in this way, have Conducive to the stability for maintaining scanning signal output end g1 output signal.In addition, since the 9th transistor M9 only has maintenance current potential Effect, the 9th transistor M9 can be set to switching transistor, compared with driving transistor, the area of switching transistor compared with It is small, to be conducive to reduce the chip area of display panel, to be conducive to the narrow frame design of display panel.

On the basis of the various embodiments described above, optionally, the breadth length ratio of the 8th transistor M8 is greater than the 9th transistor M9's Breadth length ratio promotes the driving capability of the 8th transistor M8 to be conducive to increase the electric current of the 8th transistor M8.

Fig. 9 is the structural schematic diagram of another scanning circuit provided in an embodiment of the present invention.Referring to Fig. 9, in above-mentioned each reality On the basis of applying example, optionally, input module 100 includes the first transistor M1, and first node control module 200 includes second brilliant Body pipe M2 and third transistor M3, second node control module 300 include the 4th transistor M4 and the 5th transistor M5, and node is mutual Controlling module 400 includes the 6th transistor M6 and the 7th transistor M7, and output module 500 includes the 8th transistor M8 and first capacitor C1, it includes the 9th transistor M9 that output, which keeps module 600,.

Wherein, the grid of the first transistor M1 is electrically connected with first input end g0, the first pole of the first transistor M1 and the One clock signal terminal clk1 electrical connection, the second pole of the first transistor M1 is electrically connected with first node N1.Second transistor M2's Grid is electrically connected with the second input terminal g2, and the first pole of second transistor M2 is electrically connected with the first clock signal terminal clk1, and second The second pole of transistor M2 is electrically connected with first node N1.The grid of third transistor M3 is electrically connected with second clock signal end clk2 It connects, the first pole of third transistor M3 is electrically connected with the first power end vgl1, the second pole of third transistor M3 and first node N1 electrical connection.

The grid of 9th transistor M9 is electrically connected with second node N2, the first pole and second source end of the 9th transistor M9 Vgl2 electrical connection, the second pole of the 9th transistor M9 is electrically connected with scanning signal output end g1.

With continued reference to Fig. 3, illustratively, each transistor is N-type transistor.The driving method of the scanning circuit includes first Stage T1, second stage T2, phase III T3, fourth stage T4, the 5th stage T5, the 6th stage T6, the 7th stage T7 and Eight stage T8.

First stage T1, first input end g0 input high level, the second input terminal g2 input low level, the first clock signal Hold clk1 input low level, second clock signal end clk2 input high level, third clock signal terminal clk3 input low level.The One transistor M1 is connected in response to the high level that first input end g0 is inputted, the low level that the first clock signal terminal clk1 is inputted It is conducted to first node N1, control first node N1 is low level.Second transistor M2 responds the low of the second input terminal g2 input Level and turn off.Third transistor M3 in response to second clock signal end clk2 high level and be connected, by the first power end vgl1 Low level be conducted to first node N1, control first node N1 is low level.4th transistor M4 and the 5th transistor M5 structure At the diode that inverse parallel connects, the low level of response the first clock signal terminal clk1 input and the low level of second node N2 And it turns off.6th transistor M6 in response to first node N1 low level and turn off.7th transistor M7 responds second node N2's Low level and turn off.8th transistor M8 in response to first node N1 low level and turn off.9th transistor M9 responds the second section The low level of point N2 and turn off.Due to the memory action of first capacitor C1 and late-class circuit capacitor, scanning signal output end g1 dimension Hold low level on last stage.

Second stage T2, first input end g0 input high level, the second input terminal g2 input low level, the first clock signal Hold clk1 input high level, second clock signal end clk2 input low level, third clock signal terminal clk3 input low level.The One transistor M1 in response to first input end g0 high level and be connected, the high level of the first clock signal terminal clk1 is conducted to One node N1, since the energy storage of capacitor acts on, the current potential of first node N1 is gradually risen, but the 8th transistor M8 is still in shutdown State.Second transistor M2 responds the low level of the second input terminal g2 and turns off.Third transistor M3 responds second clock signal It holds the low level of clk2 and turns off.4th transistor M4 and the 5th transistor M5 constitutes the diode of inverse parallel connection, response The low level of first clock signal terminal clk1 input high level and second node N2 and be connected.At the same time, the 6th transistor M6 In response to first node N1 high level and be connected, the low level of the first power end vgl1 is conducted to second node N2, control the Two node N2 are low level.7th transistor M7 in response to second node N2 low level and turn off.Due to the electricity of first node N1 Position is not enough to be connected the 8th transistor M8 during rising, and the 8th transistor M8 is still off state.Due to first capacitor C1 With the memory action of late-class circuit capacitor, scanning signal output end g1 maintains low level on last stage.

Phase III T3, first input end g0 input low level, the second input terminal g2 input low level, the first clock signal Hold clk1 input high level, second clock signal end clk2 input low level, third clock signal terminal clk3 input high level.The The current potential raising of one node N1 is enough that the 8th transistor M8 is connected, and the 8th transistor M8 leads the high level of third clock signal Pass to scanning signal output end g1.What the high level and first capacitor C1 of first node N1 response scanning signal output end g1 stored High level, voltage continue to increase.The first transistor M1 in response to first input end g0 low level and turn off.Second transistor M2 It responds the second input terminal g2 input low level and turns off.Third transistor M3 in response to second clock signal end clk2 low level and Shutdown.4th transistor M4 and the 5th transistor M5 constitutes the diode of inverse parallel connection, responds the first clock signal terminal The low level of clk1 input high level and second node N2 and be connected.At the same time, the 6th transistor M6 responds first node N1 High level and be connected, the low level of the first power end vgl1 is conducted to second node N2, control second node N2 is low electricity It is flat.7th transistor M7 in response to second node N2 low level and turn off.Scanning signal output end g1 exports high level.

Fourth stage T4, first input end g0 input low level, the second input terminal g2 input high level, the first clock signal Hold clk1 input high level, second clock signal end clk2 input low level, third clock signal terminal clk3 input low level.The One transistor M1 in response to first input end g0 low level and turn off.Second transistor M2 responds the high level of the second input terminal g2 And be connected, the high level of the first clock signal terminal clk1 is conducted to first node N1 by second transistor M2, controls first node N1 is high level.Third transistor M3 in response to second clock signal end clk2 low level and turn off.4th transistor M4 and Five transistor M5 constitute the diode of inverse parallel connection, respond the first clock signal terminal clk1 input high level and second node The low level of N2 and be connected.At the same time, the 6th transistor M6 in response to first node N1 high level and be connected, by the first power supply The low level of end vgl1 is conducted to second node N2, and control second node N2 is low level.7th transistor M7 responds the second section The low level of point N2 and turn off.8th transistor M8 in response to first node N1 high level and be connected, by third clock signal terminal The low level of clk3 is conducted to scanning signal output end g1.First node N1 responds the low level and the of scanning signal output end g1 The high level of one capacitor C1 storage, voltage reduce.To sum up, scanning signal output end g1 exports low level.

5th stage T5, first input end g0 input low level, the second input terminal g2 input high level, the first clock signal Hold clk1 input low level, second clock signal end clk2 input high level, third clock signal terminal clk3 input low level.The One transistor M1 in response to first input end g0 low level and turn off.Second transistor M2 responds the high level of the second input terminal g2 And be connected, the low level of the first clock signal terminal clk1 is conducted to first node N1 by second transistor M2, controls first node N1 is low level.Third transistor M3 in response to second clock signal end clk2 high level and be connected, by the first power end vgl1 Low level be conducted to first node N1, control first node N1 is low level.4th transistor M4 and the 5th transistor M5 structure At the diode that inverse parallel connects, respond the low level of the first clock signal terminal clk1 input low level and second node N2 and Shutdown.6th transistor M6 in response to first node N1 low level and turn off.7th transistor M7 responds the low of second node N2 Level and turn off.8th transistor M8 in response to first node N1 low level and turn off.To sum up, scanning signal output end g1 is exported Low level.

6th stage T6, first input end g0 input low level, the second input terminal g2 input low level, the first clock signal Hold clk1 input low level, second clock signal end clk2 input high level.The first transistor M1 responds first input end g0's Low level and turn off.Second transistor M2 responds the low level of the second input terminal g2 and turns off.Third transistor M3 response second The high level of clock signal terminal clk2 and be connected, the low level of the first power end vgl1 is conducted to first node N1, control the One node N1 is low level.4th transistor M4 and the 5th transistor M5 constitutes the diode of inverse parallel connection, response first The low level of clock signal terminal clk1 input low level and second node N2 and turn off.6th transistor M6 responds first node N1 Low level and turn off.7th transistor M7 in response to second node N2 low level and turn off.8th transistor M8 response first The low level of node N1 and turn off.Due to the memory action of first capacitor C1 and late-class circuit capacitor, scanning signal output end g1 Maintain low level on last stage.

7th stage T7, first input end g0 input low level, the second input terminal g2 input low level, the first clock signal Hold clk1 input high level, second clock signal end clk2 input low level.The first transistor M1 responds first input end g0's Low level and turn off.Second transistor M2 responds the low level of the second input terminal g2 and turns off.Third transistor M3 response second Clock signal terminal clk2 input low level and turn off.4th transistor M4 and the 5th transistor M5 constitutes two poles of inverse parallel connection Pipe responds the low level of the first clock signal terminal clk1 input high level and second node N2 and is connected, and the first clock is believed The high level of number end clk1 is conducted to second node N2, and control second node N2 is high level.6th transistor M6 response first The low level of node N1 and turn off.7th transistor M7 in response to second node N2 high level and be connected, by the first power end The low level of vgl1 is conducted to first node N1, and control first node N1 is low level.8th transistor M8 responds first node The low level of N1 and turn off.9th transistor M9 in response to second node N2 high level and be connected, by second source end vgl2's Low level is conducted to scanning signal output end g1, and scanning signal output end g1 maintains low level output.

8th stage T8, first input end g0 input low level, the second input terminal g2 input low level, the first clock signal Hold clk1 input low level, second clock signal end clk2 input high level.The first transistor M1 responds first input end g0's Low level and turn off.Second transistor M2 responds the low level of the second input terminal g2 and turns off.Third transistor M3 response second The high level of clock signal terminal clk2 and be connected, the low level of the first power end vgl1 is conducted to first node N1, control the One node N1 is low level.4th transistor M4 and the 5th transistor M5 constitutes the diode of inverse parallel connection, response first The high level of clock signal terminal clk1 input low level and second node N2 and be connected, the current potential of second node N2 is dragged down, control Second node N2 processed is low level.6th transistor M6 in response to first node N1 low level and turn off.7th transistor M7 is rung It answers the low level of second node N2 and turns off.8th transistor M8 in response to first node N1 low level and turn off.9th crystal Pipe M9 in response to second node N2 low level and turn off.Due to the memory action of first capacitor C1 and late-class circuit capacitor, scanning Signal output end g1 maintains low level on last stage.

And so on, after the 8th stage T8, scanning circuit repeats the work shape of the 7th stage T7 and the 8th stage T8 State, the current potential of second node N2 and the level state of the first clock signal terminal clk1 are consistent, and are height in second node N2 When level, the 9th transistor M9 conducting maintains the low level of scanning signal output end g1.Therefore, the embodiment of the present invention realizes To the shift function of the pulse signal of first input end g0 input, i.e. forward scan.It should be noted that the embodiment of the present invention mentions The pulse signal of second input terminal g2 can also be carried out displacement output, i.e. reverse scan, art technology by the scanning circuit of confession Personnel are appreciated that the driving process of reverse scan is similar with forward scan, repeat no more.

The embodiment of the invention provides a kind of 9T1C scanning circuits, realize bilateral scanning function.Wherein, the first transistor M1 and second transistor M2 is symmetrical arranged, and load is equal, and bias is smaller, is conducive to the operation threshold voltage to work long hours It deviates smaller.Therefore, the embodiment of the present invention is conducive to be promoted the stability of scanning circuit work, to be conducive to promote display surface The reliability of plate.And the embodiment of the present invention only needs one driving transistor of setting and a capacitor, to be conducive to reduce aobvious The chip area for showing panel is conducive to the load for reducing scanning circuit clock bus.

It should be noted that schematically illustrating each transistor in the above-described embodiments is N-type transistor, not pair Restriction of the invention.It is P-type transistor that each transistor can also be set as needed in other embodiments, alternatively, part Transistor is P-type transistor, and portion of transistor is N-type transistor, be can be set as needed in practical applications.

On the basis of the various embodiments described above, optionally, the electricity of the first power end vgl1 and second source end vgl2 input Pressure is different.

Wherein, the voltage of the first power end vgl1 is the control voltage for controlling the turn-on and turn-off state of each transistor.The The voltage of two power end vgl2 output is the voltage of scanning signal output end g1 output.The first power end is arranged in the embodiment of the present invention Vgl1 and second source end vgl2 is different, can not change the voltage of second source end vgl2 and adjust the first power end vgl1's Voltage.Therefore, in the case that the embodiment of the present invention may insure scanning signal output end g1 stable output signal, first is adjusted The voltage of power end vgl1, by adjusting the voltage of the first power end vgl1, the size of current of adjustable each transistor, with choosing A suitable voltage is selected to reduce the power consumption of scanning circuit.

On the basis of the various embodiments described above, optionally, the first power end vgl1 and second source end vgl2 are shorted, this hair The quantity that can reduce signal wire is arranged in bright embodiment in this way, is conducive to the wiring of display panel.

On the basis of the various embodiments described above, optionally, the frequency of the clock signal of the first clock signal terminal clk1 input It is identical as the frequency of clock signal of second clock signal end clk2 input, the clock signal of third clock signal terminal clk3 input Frequency be twice of frequency of clock signal of second clock signal end clk2 input.

Wherein, the clock signal of the first clock signal terminal clk1 and second clock signal end clk2 input is gate pulse output Clock, it acts as the turn-on and turn-off of the transistor in control scanning circuit.The clock of third clock signal terminal clk3 input Signal is control shift clock, and effect is that output is exported to scanning signal output end g1 as scanning signal.The present invention is implemented Example setting gate pulse exports clock and control shift clock is provided separately, and advantageously reduces the load of gate pulse output clock.Separately Outside, the embodiment of the present invention can also adjust the current potential height of the first clock signal and second clock signal as needed, can adjust The size of current of each transistor is saved, reduces the power consumption of scanning circuit to select a suitable voltage.

On the basis of the various embodiments described above, optionally, the height electricity of the clock signal of the first clock signal terminal clk1 input It is flat identical as the high level of clock signal that second clock signal end clk2 is inputted.

First clock signal terminal clk1 input clock signal low level and second clock signal end clk2 input when The low level of clock signal is identical, the low level and second clock signal end of the clock signal of third clock signal terminal clk3 input The high level of the clock signal of clk2 input is different.

Wherein, the clock signal of the first clock signal terminal clk1 and second clock signal end clk2 input is gate pulse output Clock, the clock signal of third clock signal terminal clk3 input are control shift clock.The embodiment of the present invention passes through setting first Clock signal is identical with the low and high level of second clock signal, and the voltage biasing conditions for being conducive to control transistor are identical, thus Be conducive to maintain the operation threshold variation of each transistor smaller.

It should be noted that the high level of the clock signal of third clock signal terminal clk3 input can be believed with second clock The high level of the clock signal of number end clk2 input is same or different, the clock signal of third clock signal terminal clk3 input Low level can be same or different with the high level of the second clock signal end clk2 clock signal inputted, and the present invention does not limit It is fixed, it can be set as needed in practical applications.

On the basis of the various embodiments described above, optionally, the height electricity of the clock signal of the first clock signal terminal clk1 input Gentle low level is symmetrical.The high level and low level of the clock signal of second clock signal end clk2 input are symmetrical.The present invention is real Example is applied in this way, advantageously reducing the bias of each transistor, to advantageously reduce the threshold voltage shift of each transistor.

The embodiment of the invention also provides a kind of display panels.Figure 10 is a kind of display panel provided in an embodiment of the present invention Structural schematic diagram.Referring to Figure 10, the display panel include it is multiple as scanning circuits 10 provided by any embodiment of the invention, First clock cable 21, second clock signal wire 22, third clock cable 23, the 4th clock cable 24, the 5th clock Signal wire 25, the 6th clock cable 26, the first power signal line 31, second source signal wire 32, the first enabling signal line 41, Second enabling signal line 42 and multi-strip scanning line 50.

Multiple 10 cascade connections of scanning circuit, the first input end of first order scanning circuit 10 and the first enabling signal line 41 Electrical connection；The scanning signal output end of upper level scanning circuit 10 is electrically connected with the first input end of next stage scanning circuit 10； Second input terminal of afterbody scanning circuit 10 is electrically connected with the second enabling signal line 42；The scanning of next stage scanning circuit 10 Signal output end is electrically connected with the second input terminal of upper level scanning circuit 10.

First clock signal terminal of odd level scanning circuit 10 is electrically connected with the first clock cable 21, second clock letter Number end is electrically connected with second clock signal wire 22, and third clock signal terminal is electrically connected with third clock cable 23；Even level First clock signal terminal of scanning circuit 10 is electrically connected with the 4th clock cable 24, and second clock signal end and the 5th clock are believed Number line 25 is electrically connected, and third clock signal terminal is electrically connected with the 6th clock cable 26.

First power end of scanning circuit 10 is electrically connected with the first power signal line 31, and second source end and second source are believed Number line 32 is electrically connected；Multi-strip scanning line 50 is electrically connected with the scanning signal output end of corresponding scanning circuit 10.

Figure 11 is a kind of driver' s timing schematic diagram of display panel provided in an embodiment of the present invention.It is exemplary referring to Figure 11 Ground, the display panel share n grades of scanning circuits.First clock signal of first clock cable 21 to odd level scanning circuit 10 End sends the first clock signal vclk1, and second clock signal wire 22 is sent out to the second clock signal end of odd level scanning circuit 10 Send second clock signal vclk2, third clock cable 23 sends the to the third clock signal terminal of odd level scanning circuit 10 Three clock signal vclk3, when the 4th clock cable 24 sends the 4th to the first clock signal terminal of even level scanning circuit 10 Clock signal vclk4, the 5th clock cable 25 send the 5th clock letter to the second clock signal end of even level scanning circuit 10 Number vclk5, the 6th clock cable 26 send the 6th clock signal to the third clock signal terminal of even level scanning circuit 10 Vclk6, the first enabling signal line 41 input the first enabling signal vg0 to the first input end of first order scanning circuit 10.

The driving method of the display panel includes:

The first clock signal is sent to the first clock cable 21, sends second clock letter to second clock signal wire 22 Number, third clock signal is sent to third clock cable 23, the 4th clock signal is sent to the 4th clock cable 24, to the Five clock cables 25 send the 5th clock signal, the 6th clock signal are sent to the 6th clock cable 26, to the first power supply Signal wire 31 sends the first power supply signal, second source signal is sent to second source signal wire 32, to the first enabling signal line 41 send the first enabling signal；Wherein, the first clock signal and the 4th clock signal are on the contrary, second clock signal and the 5th clock Signal is on the contrary, third clock signal is opposite with the 6th clock signal.

Drive multiple scanning circuits 10 are positive to send scanning signal, i.e. first order scanning circuit to multi-strip scanning line 50 step by step 10, second level scanning circuit 10 ... (n-1)th grade of scanning circuit 10 and n-th grade of scanning circuit 10 are sequentially output scanning signal, real Existing forward scan.

It should be noted that the embodiment of the present invention can also realize reverse scan.Specifically, to the second enabling signal line 42 Enabling signal is sent, reverse scan may be implemented, it will be understood by those skilled in the art that the driving method of reverse scan is similar, It repeats no more.

Display panel provided by the embodiment of the present invention includes scanning circuit 10 provided by any embodiment of the invention, Technical principle is similar with the technical effect of generation, and which is not described herein again.

The embodiment of the invention also provides a kind of driving methods of display panel, are mentioned suitable for any embodiment of that present invention The display panel of confession.Figure 12 is a kind of flow diagram of the driving method of display panel provided in an embodiment of the present invention.Referring to Figure 12, the driving method of the display panel the following steps are included:

S110, in the first scan phase, the first clock signal is sent to the first clock cable, to second clock signal wire Second clock signal is sent, third clock signal is sent to third clock cable, when sending the 4th to the 4th clock cable Clock signal, sends the 5th clock signal to the 5th clock cable, the 6th clock signal is sent to the 6th clock cable, to the One power signal line sends the first power supply signal, second source signal is sent to second source signal wire, to the first enabling signal Line sends the first enabling signal；Wherein, the first clock signal and the 4th clock signal are on the contrary, second clock signal and the 5th clock Signal is on the contrary, third clock signal is opposite with the 6th clock signal.

S120, the multiple scanning circuit forward directions of driving send scanning signal to multi-strip scanning line step by step.

The driving method of display panel provided by the embodiment of the present invention is suitable for provided by any embodiment of the invention The technical effect of display panel, technical principle and generation is similar, and which is not described herein again.

On the basis of the various embodiments described above, optionally, the first clock signal, second clock signal, the 4th clock signal It is identical with the frequency of the 5th clock signal；Third clock signal is identical with the frequency of the 6th clock signal；Third clock signal Frequency is twice of the frequency of the first clock signal.

Figure 13 is the flow diagram of the driving method of another display panel provided in an embodiment of the present invention.Referring to figure 13, on the basis of the various embodiments described above, optionally, the driving method of the display panel the following steps are included:

S210, in the first scan phase, the first clock signal is sent to the first clock cable, to second clock signal wire Second clock signal is sent, third clock signal is sent to third clock cable, when sending the 4th to the 4th clock cable Clock signal, sends the 5th clock signal to the 5th clock cable, the 6th clock signal is sent to the 6th clock cable, to the One power signal line sends the first power supply signal, second source signal is sent to second source signal wire, to the first enabling signal Line sends the first enabling signal；Wherein, the first clock signal and the 4th clock signal are on the contrary, second clock signal and the 5th clock Signal is on the contrary, third clock signal is opposite with the 6th clock signal.

S220, the multiple scanning circuit forward directions of driving send scanning signal to multi-strip scanning line step by step.

S230, in the second scan phase, the first clock signal is sent to the first clock cable, to second clock signal wire Second clock signal is sent, third clock signal is sent to third clock cable, when sending the 4th to the 4th clock cable Clock signal, sends the 5th clock signal to the 5th clock cable, the 6th clock signal is sent to the 6th clock cable, to the One power signal line sends the first power supply signal, second source signal is sent to second source signal wire, to the second enabling signal Line sends the second enabling signal.

S240, the multiple scanning circuits of driving reversely send scanning signal to multi-strip scanning line step by step.

It should be noted that the embodiment of the present invention schematically illustrates during the driving of display panel, forward direction is swept It retouches with reverse scan alternately, not limitation of the invention.In other embodiments, display can also be set as needed The driving method of panel only includes forward scan, or only includes reverse scan, can according to need progress in practical applications Setting.

Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation, It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.

Claims

1. a kind of scanning circuit characterized by comprising

Input module, the input module are electrically connected with first input end, the first clock signal terminal and first node, are used for basis The signal of the first input end and first clock signal terminal controls the current potential of the first node；

First node control module, the first node control module and first clock signal terminal, second clock signal end, Second input terminal, the electrical connection of the first power end, for being believed according to the first power end, the first clock signal terminal, the second clock Number end, second input terminal signal control the current potential of the first node；

Second node control module, the second node control module are electrically connected with the second clock signal end, second node, For controlling the current potential of the second node according to the signal of the second clock signal end；

Node cross complaint module, the node cross complaint module and first power end, the first node and second section Point electrical connection, is the second current potential for second node described in the first control of Electric potentials according to the first node, or according to institute Stating first node described in the first control of Electric potentials of second node is the second current potential；

Output module, the output module are electrically connected with third clock signal terminal, the first node and scanning signal output end, For the signal of the third clock signal terminal to be exported to the scanning signal output end according to the current potential of the first node；

Output keeps module, and the output keeps module to be electrically connected with the second node, second source end, for keeping described The output of scanning signal output end.

2. scanning circuit according to claim 1, which is characterized in that the input module includes the first transistor, described First node control module includes second transistor and third transistor；

The grid of the first transistor is electrically connected with the first input end, the first pole of the first transistor and described the The electrical connection of one clock signal terminal, the second pole of the first transistor is electrically connected with the first node；

The grid of the second transistor is electrically connected with second input terminal, the first pole of the second transistor and described the The electrical connection of one clock signal terminal, the second pole of the second transistor is electrically connected with the first node；

The grid of the third transistor is electrically connected with the second clock signal end, the first pole of the third transistor and institute The electrical connection of the first power end is stated, the second pole of the third transistor is electrically connected with the first node.

3. scanning circuit according to claim 1, which is characterized in that the second node control module includes the 4th crystal Pipe and the 5th transistor；

The grid of 4th transistor is electrically connected with its first pole, the first pole of the 4th transistor and first clock Signal end electrical connection, the second pole of the 4th transistor is electrically connected with the second node；

The grid of 5th transistor is electrically connected with its first pole, the first pole of the 4th transistor and the second node Electrical connection, the second pole of the 5th transistor is electrically connected with first clock signal terminal.

4. scanning circuit according to claim 1, which is characterized in that the node cross complaint module include the 6th transistor and 7th transistor；

The grid of 6th transistor is electrically connected with the first node, the first pole and described first of the 6th transistor Power end electrical connection, the second pole of the 6th transistor is electrically connected with the grid of the 7th transistor；

First pole of the 7th transistor is electrically connected with first power end, the second pole of the 7th transistor with it is described First node electrical connection.

5. scanning circuit according to claim 1, which is characterized in that the output module includes the 8th transistor and first Capacitor；

The grid of 8th transistor is electrically connected with the first node, the first pole of the 8th transistor and the third Clock signal terminal electrical connection, the second pole of the 8th transistor is electrically connected with the scanning signal output end；

First pole of the first capacitor is electrically connected with the grid of the 8th transistor, the second pole of the first capacitor and institute State the second pole electrical connection of the 8th transistor.

6. scanning circuit according to claim 5, which is characterized in that it includes the 9th transistor that the output, which keeps module,；

The grid of 9th transistor is electrically connected with the second node, the first pole and described second of the 9th transistor Power end electrical connection, the second pole of the 9th transistor is electrically connected with the scanning signal output end.

7. scanning circuit according to claim 6, which is characterized in that the breadth length ratio of the 8th transistor is greater than described the The breadth length ratio of nine transistors.

8. scanning circuit according to claim 1, which is characterized in that first power end and the second source end are defeated The voltage entered is different.

9. scanning circuit according to claim 1, which is characterized in that first power end and the second source end are short It connects.

10. scanning circuit according to claim 1, which is characterized in that the clock letter of the first clock signal terminal input Number frequency it is identical as the frequency of clock signal that the second clock signal end inputs, third clock signal terminal input The frequency of clock signal is twice of the frequency of the clock signal of second clock signal end input.

11. scanning circuit according to claim 1, which is characterized in that the clock letter of the first clock signal terminal input Number high level it is identical as the high level of clock signal that the second clock signal end inputs；

The low level of the clock signal of the first clock signal terminal input and the clock of second clock signal end input are believed Number low level it is identical.

12. scanning circuit according to claim 1, which is characterized in that the clock letter of the first clock signal terminal input Number high level and low level it is symmetrical；

The high level and low level of the clock signal of the second clock signal end input are symmetrical.

13. a kind of display panel, which is characterized in that including multiple such as the described in any item scanning circuits of claim 1-12, the One clock cable, second clock signal wire, third clock cable, the 4th clock cable, the 5th clock cable, the 6th Clock cable, the first power signal line, second source signal wire, the first enabling signal line, the second enabling signal line and a plurality of Scan line；

Multiple scanning circuit cascade connections, the first input end of scanning circuit described in the first order and first enabling signal Line electrical connection；The first input end electricity of scanning circuit described in the scanning signal output end and next stage of scanning circuit described in upper level Connection；Second input terminal of scanning circuit described in afterbody is electrically connected with the second enabling signal line；It is swept described in next stage The scanning signal output end of scanning circuit is electrically connected with the second input terminal of scanning circuit described in upper level；

First clock signal terminal of scanning circuit described in odd level is electrically connected with first clock cable, second clock letter Number end is electrically connected with the second clock signal wire, and third clock signal terminal is electrically connected with the third clock cable；Idol First clock signal terminal of scanning circuit described in several levels is electrically connected with the 4th clock cable, second clock signal end and institute The electrical connection of the 5th clock cable is stated, third clock signal terminal is electrically connected with the 6th clock cable；

First power end of the scanning circuit is electrically connected with first power signal line, the second source end and described the The electrical connection of two power signal lines；The multi-strip scanning line is electrically connected with the scanning signal output end of the corresponding scanning circuit.

14. a kind of driving method of display panel as claimed in claim 13 characterized by comprising

In the first scan phase, the first clock cable of Xiang Suoshu sends the first clock signal, Xiang Suoshu second clock signal wire Second clock signal is sent, Xiang Suoshu third clock cable sends third clock signal, the 4th clock cable of Xiang Suoshu hair The 4th clock signal is sent, the 5th clock cable of Xiang Suoshu sends the 5th clock signal, and the 6th clock cable of Xiang Suoshu is sent 6th clock signal, the first power signal line of Xiang Suoshu send the first power supply signal, and Xiang Suoshu second source signal wire sends the Two power supply signals, Xiang Suoshu the first enabling signal line send the first enabling signal；Wherein, first clock signal and described the Four clock signals on the contrary, the second clock signal with the 5th clock signal on the contrary, the third clock signal with it is described 6th clock signal is opposite；

15. the driving method of display panel according to claim 14, which is characterized in that first clock signal, institute It is identical with the frequency of the 5th clock signal to state second clock signal, the 4th clock signal；

The third clock signal is identical with the frequency of the 6th clock signal；

The frequency of the third clock signal is twice of the frequency of first clock signal.

16. the driving method of display panel according to claim 14, which is characterized in that further include:

In the second scan phase, the first clock cable of Xiang Suoshu sends the first clock signal, Xiang Suoshu second clock signal wire Second clock signal is sent, Xiang Suoshu third clock cable sends third clock signal, the 4th clock cable of Xiang Suoshu hair The 4th clock signal is sent, the 5th clock cable of Xiang Suoshu sends the 5th clock signal, and the 6th clock cable of Xiang Suoshu is sent 6th clock signal, the first power signal line of Xiang Suoshu send the first power supply signal, and Xiang Suoshu second source signal wire sends the Two power supply signals, Xiang Suoshu the second enabling signal line send the second enabling signal；

Multiple scanning circuits are driven reversely to send scanning signal to a plurality of scan line step by step.