CN110165026A

CN110165026A - LED chip and preparation method thereof, display module, intelligent terminal

Info

Publication number: CN110165026A
Application number: CN201910273288.2A
Authority: CN
Inventors: 曲爽; 代郁峰
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-04-04
Filing date: 2019-04-04
Publication date: 2019-08-23
Anticipated expiration: 2039-04-04
Also published as: CN110165026B

Abstract

The embodiment of the present application provides a kind of LED chip and preparation method thereof, display module, intelligent terminal, is related to technical field of semiconductors, can not carry out PL detection to large number of micro LED for solving the problems, such as.LED chip includes at least part of main device and antenna structure.The main device includes main epitaxial layer, first electrode and second electrode.Main epitaxial layer includes the first functional layer of the first semiconductor layer upper surface part subregion of the first semiconductor layer and covering.First functional layer includes the second semiconductor layer and the first luminescent layer.First luminescent layer is between the first semiconductor layer and the second semiconductor layer.First electrode is set to the upper surface of the first semiconductor layer, and couples with the first semiconductor layer.Second electrode is set to the upper surface of the second semiconductor layer, and couples with the second semiconductor layer.Antenna structure and first electrode and second electrode couple.Antenna structure generates potential difference for receiving radiofrequency signal between the first electrode and the second electrode.

Description

LED chip and preparation method thereof, display module, intelligent terminal

Technical field

This application involves technical field of semiconductors more particularly to a kind of LED chip and preparation method thereof, display module, intelligence It can terminal.

Background technique

With the continuous development of display technology, opposite liquid crystal display (liquid crystal display, LCD) and Speech, miniature (micro) Organic Light Emitting Diode (light emitting diode, LED) are used as a kind of current mode photophore Part because of its self-luminous and higher luminous efficiency, color saturation, brightness, reliability, and can be produced on The features such as in flexible substrate and be applied in high-performance display field more and more.

In micro LED display, each micro LED can be used as a sub-pixel (sub pixel).In order to Reduce micro LED display and occur the probability of bad point (sub-pixel that can not be shone) during display, needs making Cheng Zhong carries out luminescence generated by light (photo luminescence, PL) detection to micro LED.However, due to single micro The size of LED is smaller (in the micron-scale), and in display screen micro LED quantity it is more, therefore can not be in display screen Micro LED is detected one by one.

Summary of the invention

The embodiment of the present application provides a kind of LED chip and preparation method thereof, display module, intelligent terminal, for solving nothing The problem of method carries out PL detection to large number of micro LED chip.

In order to achieve the above objectives, the present embodiment adopts the following technical scheme that

The embodiment of the present application in a first aspect, providing a kind of LED chip.The LED chip includes main device and antenna structure. The main device includes main epitaxial layer, first electrode and second electrode.Wherein, main epitaxial layer includes the first semiconductor layer and covering the First functional layer of semi-conductor layer upper surface part subregion.First functional layer includes that the second semiconductor layer and first shine Layer.Above-mentioned first luminescent layer is between the first semiconductor layer and the second semiconductor layer.In addition, first electrode is set to the first half The upper surface of conductor layer, and coupled with the first semiconductor layer.Second electrode is set to the upper surface of the second semiconductor layer, and with The coupling of two semiconductor layers.Antenna structure and first electrode and second electrode couple.Antenna structure for receiving radiofrequency signal, and Potential difference is generated between first electrode and second electrode.In this case, it is possible to be cutting to obtain above-mentioned LED in chip die Before chip, into the chip die, each strip antenna structure sends radiofrequency signal.Antenna structure makes when receiving radiofrequency signal It obtains and generates potential difference between the first electrode and second electrode that the antenna structure is coupled.The electromotive force can make first electrode There is potential difference between second electrode, therefore form electric field between first electrode and second electrode.The electric field enables to The hole in electronics and the second semiconductor layer (i.e. P-type semiconductor) in semi-conductor layer (i.e. N-type semiconductor) shines first It is compound in layer, and energy is issued in the form of photon, to drive each main device to shine.So as to judge that each main device is No failure.Belonging to each main device in the same chip die can be detected in the primary detection that shines, therefore can It solves the problems, such as that large number of LED chip can not be detected.It, can be to chip die after above-mentioned luminous detection It is cut, to obtain multiple above-mentioned LED chips.In the case, when LED chip upside-down mounting is above-mentioned aobvious in being formed on substrate After showing mould group, during which shows, the first electrode and second electrode of each LED chip receive direct current signal, It carries out luminous.Therefore, above-mentioned direct current signal will not make antenna structure induce electromotive force during display module display, To be impacted to the display of display module.

Optionally, antenna structure includes the conductive coil on the outside of main epitaxial layer.The first end of the conductive coil and the One electrode forms capacitor, and second end is in contact with second electrode.Alternatively, the first end of conductive coil and first electrode form electricity Hold, second end and second electrode form capacitor.The capacitor has the function of logical exchange barrier direct current, to receive in conductive coil To after radiofrequency signal, the coupling of the first end and first electrode of conductive coil may be implemented.Similarly in the second end of conductive coil The case where forming capacitor with second electrode can also be received by the effect of the logical exchange barrier direct current of capacitor in conductive coil After radiofrequency signal, the coupling of the second end and second electrode of conductive coil is realized.

Optionally, in the case where forming capacitor between the first end of conductive coil and first electrode, the of conductive coil There is gap, and orthographic projection of the conductive coil on main epitaxial layer, with first electrode in main extension between one end and first electrode Orthographic projection no overlap region on layer.The technical effect of the capacitor is same as above, and details are not described herein again.

Optionally, in the case where forming capacitor between the first end of conductive coil and first electrode, first electrode is close The side setting of conductive coil is fluted.The first end of above-mentioned conductive coil protrudes into groove, and the first end of conductive coil with There is gap, to form capacitor between the first end of conductive coil and the inner wall of groove between the inner wall of groove.The capacitor Technical effect is same as above, and details are not described herein again.

Optionally, the conducting direction of main device is directed toward first electrode by second electrode.Above-mentioned antenna structure includes: sub- device Part, conducting wire and conductive coil on the outside of main epitaxial layer.Wherein, sub- device includes sub- epitaxial layer and is set to sub- extension The first auxiliary electrode and the second auxiliary electrode on layer.Sub- epitaxial layer and main epitaxial layer insulation set.In addition, the conducting of sub- device Direction the first auxiliary electrode is directed toward by the second auxiliary electrode.In the case, one end of conductive coil is in contact with first electrode, The other end is in contact with the second auxiliary electrode.One end of conducting wire is in contact with the first auxiliary electrode, the other end and second electrode phase Contact.In the case, using first electrode as N electrode, second electrode is for P electrode.When the conductive coil in antenna structure When receiving above-mentioned radiofrequency signal, since the conducting direction of main device is directed toward first electrode by second electrode, so in the signal Positive pressure when being applied to first electrode, main device is not turned on, so will not generate potential difference between first electrode and second electrode. In addition, when the positive pressure in the radiofrequency signal as AC signal is applied to the second auxiliary electrode in sub- device, main device Voltage in first electrode can be negative pressure.Since the conducting direction of sub- device is directed toward the first auxiliary electricity by the second auxiliary electrode Pole, therefore sub- break-over of device, the voltage that the first auxiliary electrode on sub- device receives still are positive after certain pressure drop Pressure.Since the first auxiliary electrode of sub- device is electrically connected with the second electrode of main device by conducting wire, so in second electrode Voltage is that positive pressure is identical as the voltage of the first auxiliary electrode of sub- device.In the case, the first electrode of main device and second Potential difference is generated between electrode, so as to drive main device to shine, realizes the detection that shines.To the core after the detection that shines Wafer separation obtains multiple LED chips, and after LED chip is set in LED display, when needing LED chip to shine When, second electrode of the meeting into LED chip applies positive pressure, and first electrode applies negative pressure.In the case, LED chip can be normal Work.And LED chip neutron device, due to its conducting direction be the second auxiliary electrode be directed toward the first auxiliary electrode, and this second Auxiliary electrode can not obtain positive pressure, so not turning on, so as to avoid during display, sub- device sends out LED chip The influence of brightness.In addition, the set-up mode of above-mentioned conductive coil is same as above, can no overlap everywhere, alternatively, conductive coil In the presence of at least two parts of intersection and insulation set, details are not described herein again.First electrode or second electrode can be set in conduction In coil.Alternatively, conductive coil can be set between first electrode and second electrode, details are not described herein again.

Optionally, sub- epitaxial layer includes the second of third semiconductor layer and covering third semiconductor layer upper surface part subregion Functional layer.Second functional layer includes the 4th semiconductor layer and the second luminescent layer.Second luminescent layer is located at third semiconductor layer and Between four semiconductor layers.First auxiliary electrode is set to the upper surface of third semiconductor layer, and couples with third semiconductor layer.The Two auxiliary electrodes are set to the upper surface of the 4th semiconductor layer, and couple with the 4th semiconductor layer.In the case, sub- device Third semiconductor layer, the second functional layer and third semiconductor layer in sub- epitaxial layer can respectively with the main epitaxial layer of main device In the first semiconductor layer, the material of the second luminescent layer and the second semiconductor layer it is identical.In addition, in the sub- epitaxial layer of sub- device Other than third semiconductor layer, the second functional layer and third semiconductor layer, the set-up mode of other film layers can also be with master The structure of corresponding film layer is identical with position in the main epitaxial layer of device.So, can prepare simultaneously main epitaxial layer and Then sub- epitaxial layer is separated main epitaxial layer and sub- epitaxial layer by etching technics, and main epitaxial layer and sub- epitaxial layer it Between setting have insulation performance passivation layer.

Optionally, the first auxiliary electrode and the second auxiliary electrode are respectively positioned on the upper surface of the 5th semiconductor layer, and with the 5th Semiconductor layer coupling.5th semiconductor layer can be n type semiconductor layer.In the case, in sub- device, the first auxiliary electrode The 5th semiconductor layer and the second auxiliary electrode (P electrode) in (N electrode) and sub- epitaxial layer and the in sub- epitaxial layer the 5th Semiconductor layer forms schottky junction.At this point, the film layer quantity in the sub- epitaxial layer of sub- device is few, structure is simpler.

Optionally, any two circles coil is non-intersecting in conductive coil.The various pieces of the conductive coil are on main epitaxial layer Orthographic projection no overlap region.It so, can be by one layer of passivation layer, so that leading between conductive coil and main epitaxial layer It insulate between electric coil and main epitaxial layer, so as to simplify the structure of LED chip.

The second aspect of the embodiment of the present application provides a kind of LED chip.The LED chip includes main device and antenna structure Nubbin.The main device includes main epitaxial layer, first electrode and second electrode.Wherein, main epitaxial layer includes the first half leading First functional layer of the first semiconductor layer upper surface part subregion of body layer and covering.First functional layer includes the second semiconductor layer With the first luminescent layer.Above-mentioned first luminescent layer is between the first semiconductor layer and the second semiconductor layer.In addition, first electrode is set It is placed in the upper surface of the first semiconductor layer, and is coupled with the first semiconductor layer.Second electrode is set to the upper of the second semiconductor layer Surface, and coupled with the second semiconductor layer.The nubbin of antenna structure include be located on the outside of main epitaxial layer, and with main epitaxial layer First metal wire of insulation, the second metal wire and at least one third metal wire.Wherein, the first metal wire, the second metal wire And third metal wire mutually insulated.In addition, one end of the first metal wire is in contact with first electrode, the other end and LED chip An edge it is concordant.One end of second metal wire is in contact with second electrode, and an edge of the other end and LED chip is flat Together.A part of third metal wire is between the first metal wire and the second metal wire.The both ends of third metal wire and LED chip The same edge it is concordant；Alternatively, the both ends of third metal wire are concordant from two different edges of LED chip respectively.It is above-mentioned First metal wire, the second metal wire and third metal wire be when cutting chip die, will be in a complete conductive coil Part excision in Cutting Road, after forming LED chip, remnants are in the structure in LED chip in conductive coil.Wherein, The first end of every conductive coil is in contact with the first electrode of a main device, the second electrode phase of second end and the main device Contact.Therefore, before chip die cutting, radiofrequency signal can be sent to above-mentioned conductive coil, is made by conductive coil Potential difference is generated between first electrode and second electrode on main device, to complete the luminous survey of each main device in chip die Examination.After test, chip die is cut, the part being located on Cutting Road in conductive coil is removed, and is not cut The remaining part cut is above-mentioned first metal wire, the second metal wire and third metal wire.In the case, above-mentioned first gold medal The one end for belonging to line is the first end of above-mentioned conductive coil, is in contact with first electrode.One end of second metal wire is above-mentioned conduction The second end of coil, is in contact with second electrode.Third metal wire and the first metal wire, the second metal wire disconnect.It will at this point, working as LED chip upside-down mounting is after on substrate, forming above-mentioned display module, and during which shows, each LED chip is normal When operational reception direct current signal, the electrical connection between the first electrode and second electrode in the LED chip is interrupted.And then When LED chip works normally, the nubbin of the antenna structure in LED chip will not cause shadow to the normal luminous of LED chip It rings.

Optionally, the orthographic projection no overlap of the first metal wire, the second metal wire and third metal wire on main epitaxial layer Region.In addition, first electrode is located at the area that the edge of the third metal wire LED chip concordant with the third metal wire both ends surrounds In domain.It can be seen from the above, the first metal wire, the second metal wire and third metal wire are the nubbin of conductive coil.When One metal wire, the second metal wire and third metal wire at the orthographic projection no overlap region on main epitaxial layer, conductive coil A part is in the Cutting Road between two neighboring main device, and any two circles coil is non-intersecting in the conductive coil, i.e., should Orthographic projection no overlap region of the various pieces of conductive coil on main epitaxial layer.At this point, first electrode in main device or Second electrode can be located in above-mentioned conductive coil.So, one can be passed through between entire conductive coil and main epitaxial layer Layer passivation layer, so that insulating between conductive coil and main epitaxial layer, so as to simplify the structure of LED chip.

Optionally, include a plurality of third metal wire in LED chip, there is gap between adjacent two third metal wires.Together Upper described, after cutting chip die to obtain above-mentioned LED chip, each metal line of conductive coil remnants is in main extension Orthographic projection no overlap region on layer.It so, can be blunt by one layer first between entire conductive coil and main epitaxial layer Change layer, so that insulating between conductive coil and main epitaxial layer, so as to simplify the structure of LED chip.

Optionally, the first metal wire and third wire insulation.First metal wire and at least one third metal wire are in master Orthographic projection on epitaxial layer has overlapping region.It can be seen from the above, the first metal wire, the second metal wire and third metal wire are The nubbin of conductive coil.When the orthographic projection of the first metal wire, the second metal wire and third metal wire on main epitaxial layer When with overlapping region, which includes the first sub-portion and the second sub-portion being connected.First sub-portion is in main epitaxial layer On orthographic projection, with orthographic projection of second sub-portion on main epitaxial layer have overlapping region.In the case, in the first metal wire The second sub-portion that overlapping part can be conductive coil occurs with third metal wire.And third metal wire and the second metal wire can Think a part of the first sub-portion of conductive coil.The of insulation is provided between the first sub-portion and the second sub-portion of conductive coil Two passivation layers.Therefore can make that overlapping SI semi-insulation occurs with third metal wire in the first metal wire.So, it will lead Electric coil is set between the first electrode of main device and second electrode, so as to save the master that conductive coil occupies main device The space of epi-layer surface.

The third aspect of the embodiment of the present application provides a kind of preparation method of LED chip.The preparation method includes: to serve as a contrast Each on bottom sets up production main device in region, and substrate includes the multiple establishment areas defined by the Cutting Road that transverse and longitudinal is intersected Domain.Wherein, main epitaxial layer includes the first functional layer of the first semiconductor layer upper surface part subregion of the first semiconductor layer and covering. First functional layer includes the second semiconductor layer and the first luminescent layer.First luminescent layer is located at the first semiconductor layer and the second semiconductor Between layer.First electrode is set to the upper surface of the first semiconductor layer, and couples with the first semiconductor layer；Second electrode is set to The upper surface of second semiconductor layer, and coupled with the second semiconductor layer.In addition, production mutiple antennas structure, mutiple antennas structure It is corresponded with multiple establishment regions, the corresponding first electrode and second electrode coupling set up in region of each antenna structure It connects, forms chip die.Above-mentioned antenna structure is for receiving radiofrequency signal, and first electrode in same establishment region and the Potential difference is generated between two electrodes.In addition, sending radiofrequency signal, and each master in acquisition chip wafer to mutiple antennas structure The light emission luminance of device tests whether each main device can work normally according to the light emission luminance of each main device.In addition, Chip die is separated along Cutting Road, obtains multiple LED chips.The preparation method of above-mentioned kind of LED chip and aforementioned implementation The LED chip technical effect having the same that example provides, details are not described herein again.

Optionally, production antenna structure is included on the outside of main epitaxial layer, makes a plurality of conductive coil.Wherein, every conduction The both ends of coil are in contact with the first electrode and second electrode being located in same establishment region respectively, and every conductive coil At least part is located in the Cutting Road between two neighboring establishment region.Independent LED is being cut to chip die After chip, the part that above-mentioned conductive coil is located in Cutting Road is removed, so that remaining in LED chip have and can not be electrically connected Metal wire, i.e., the nubbin of above-mentioned conductive coil.So, when LED chip works normally reception direct current signal, the LED Electrical connection between first electrode and second electrode in chip is interrupted.And then when LED chip works normally, LED chip On the nubbin of antenna structure (i.e. above-mentioned conductive coil) normal luminous of LED chip will not be impacted.

Optionally, production antenna structure includes: to make a plurality of conductive coil, every conductive coil on the outside of main epitaxial layer In an establishment region.Capacitor, second end and the second electricity are formed between the first end and first electrode of every conductive coil Pole is in contact.Alternatively, capacitor is formed between the first end and first electrode of every conductive coil, between second end and second electrode Form capacitor.The capacitor has the function of logical exchange barrier direct current, thus after conductive coil receives radiofrequency signal, Ke Yishi The coupling of the first end and first electrode of existing conductive coil.Similarly capacitor is formed in the second end of conductive coil and second electrode Situation can also realize conductor wire after conductive coil receives radiofrequency signal by the effect of the logical exchange barrier direct current of capacitor The coupling of the second end and second electrode of circle.

Optionally, production first electrode includes: that first electrode is made on the upper surface of the first semiconductor layer, and first The side of electrode forms groove.In addition, the first end that production conductive coil includes conductive coil protrudes into groove, and conductive coil First end and groove inner wall between have gap, between the first end of conductive coil and the inner wall of groove formed electricity Hold.The technical effect of the capacitor is same as above, and details are not described herein again.

Optionally, production antenna structure includes: to form sub- device, sub- device includes and main epitaxial layer setting up in region The sub- epitaxial layer of insulation, and the first auxiliary electrode and the second auxiliary electrode on sub- epitaxial layer.The conducting of the sub- device Direction the first auxiliary electrode is directed toward by the second auxiliary electrode.In addition, production antenna structure further include: on the outside of main epitaxial layer, system Make a plurality of conductive coil and a plurality of conducting wire, there is a conductive coil and a conducting wire in each establishment region.Positioned at each group The one end for the conductive coil built in region is in contact with first electrode, and the other end is in contact with the second auxiliary electrode.Positioned at each The one end for setting up a conducting wire in region is in contact with the first auxiliary electrode, and the other end is in contact with second electrode.Main device Conducting direction first electrode is directed toward by second electrode.By sub- device, conducting wire and conductive coil on the outside of main epitaxial layer The technical effect of the antenna structure of composition is same as above, and details are not described herein again.

The fourth aspect of the embodiment of the present application provides a kind of display module, including substrate and array arrangement in substrate Any one LED chip as described above.Each LED chip is a sub-pixel.The display module has and aforementioned implementation The identical technical effect of LED chip that example provides, details are not described herein again.

The fourth aspect of the embodiment of the present application provides a kind of intelligent terminal, including processor and display mould as described above Group, processor show image for controlling display module.The intelligent terminal has the display module phase provided with previous embodiment Same technical effect, details are not described herein again.

Detailed description of the invention

Fig. 1 a is some embodiments of the present application, a kind of structural schematic diagram of the intelligent terminal provided；

Fig. 1 b is some embodiments of the present application, a kind of structural schematic diagram of the display module provided；

Fig. 2 is the structural schematic diagram of LED chip in Fig. 1；

Fig. 3 is LED chip upside-down mounting in Fig. 2 in the structural schematic diagram on substrate；

Fig. 4 is some embodiments of the present application, a kind of production method flow chart of the LED chip provided；

Fig. 5 is some embodiments of the present application, and a kind of division provided has the structural schematic diagram of the substrate of Cutting Road；

Fig. 6 a is a kind of structural schematic diagram of main epitaxial layer in Fig. 2；

Fig. 6 b is another structural schematic diagram of main epitaxial layer in Fig. 2；

Fig. 7 is some embodiments of the present application, the structural schematic diagram of the multiple epitaxial wafers provided；

Fig. 8 a, Fig. 8 b, Fig. 8 c, Fig. 8 d, Fig. 8 e are some embodiments of the present application, the first electrode and second electrode provided Manufacturing process schematic diagram；

Fig. 8 f is some embodiments of the present application, a kind of structural schematic diagram of the LED chip provided；

Fig. 8 g is some embodiments of the present application, the structural schematic diagram of another LED chip provided；

Fig. 8 h is some embodiments of the present application, and the production provided has a chip die of first electrode and second electrode Structural schematic diagram；

Fig. 9 is some embodiments of the present application, a kind of top view of the chip die provided；

Figure 10 is some embodiments of the present application, provide it is a kind of different LED chips is isolated from multiple chip dies, And form the schematic diagram of display module；

Figure 11 a is some embodiments of the present application, the top view of another chip die provided；

Figure 11 b O1-O1 dotted line along Figure 11 a carries out the cross-sectional view that cutting obtains；

Figure 11 c is to separate to chip die shown in Figure 11 a, a kind of structural schematic diagram of LED chip of acquisition；

Figure 11 d is to separate to chip die shown in Figure 11 a, the structural schematic diagram of another LED chip of acquisition；

Figure 11 e is to separate to chip die shown in Figure 11 a, the structural schematic diagram of another LED chip of acquisition；

Figure 12 is some embodiments of the present application, a kind of structural schematic diagram of the test equipment provided；

Figure 13 is the schematic diagram of the test result obtained using test equipment shown in Figure 12；

Figure 14 a is the cross-sectional view that D-D dotted line carries out a kind of LED chip that cutting obtains along Figure 11 a；

Figure 14 b is the cross-sectional view that D-D dotted line carries out another LED chip that cutting obtains along Figure 11 a；

Figure 15 a is some embodiments of the present application, the top view of another chip die provided；

Figure 15 b is the cross-sectional view that Q1-Q1 dotted line carries out a kind of LED chip that cutting obtains along Figure 15 a；

Figure 15 c is to separate to chip die shown in Figure 15 a, a kind of structural schematic diagram of LED chip of acquisition；

Figure 16 a is some embodiments of the present application, the top view of another chip die provided；

Figure 16 b is to separate to chip die shown in Figure 16 a, a kind of structural schematic diagram of LED chip of acquisition；

Figure 16 c is the cross-sectional view that O2-O2 dotted line carries out a kind of LED chip that cutting obtains along Figure 16 a；

Figure 16 d is the cross-sectional view that O2-O2 dotted line carries out another LED chip that cutting obtains along Figure 16 a；

Figure 16 e is the cross-sectional view that O2-O2 dotted line carries out another LED chip that cutting obtains along Figure 16 a；

Figure 16 f is the cross-sectional view that O2-O2 dotted line carries out another LED chip that cutting obtains along Figure 16 a；

Figure 17 a is some embodiments of the present application, the top view of another LED chip provided；

Figure 17 b is the cross-sectional view that O2-O2 dotted line carries out a kind of LED chip that cutting obtains along Figure 17 a；

Figure 18 is some embodiments of the present application, the structural schematic diagram of another test equipment provided；

Figure 19 a is some embodiments of the present application, the top view of another chip die provided；

Figure 19 b is to separate to chip die shown in Figure 19 a, a kind of structural schematic diagram of LED chip of acquisition；

Figure 19 c is the cross-sectional view that O3-O3 dotted line carries out a kind of LED chip that cutting obtains along Figure 19 b；

Figure 19 d is the cross-sectional view that Q3-Q3 dotted line carries out a kind of LED chip that cutting obtains along Figure 19 b；

Figure 20 a is a kind of schematic cross-sectional view of Figure 19 b neutron device；

Figure 20 b is a kind of schematic cross-sectional view of Figure 19 b neutron device.

Appended drawing reference:

01- display module；02- pixel；03- epitaxial wafer；04- detection device；05- intelligent terminal；06- processor；10- base Plate；101- sub-pixel；11-LED chip；100- substrate；The main epitaxial layer of 110-；The first semiconductor layer of 111-；112- the second half is led Body layer；The first luminescent layer of 113-；114- semiconductor nucleating layer；The undoped semiconductor layer of 115-；The low-doped semiconductor layer of 116-； 117- grows superlattice layer；118- electronic barrier layer；119- ohmic contact layer；120- Distributed Bragg Reflection layer；121- One electrode；1210- groove；1211- first part；1212- second part；1213- Part III；122- second electrode；20- Photoresist；21- mask plate；22- metal layer；The first functional layer of 201-；The second functional layer of 202-；30- sets up region；31- cutting Road；300- chip die；40- antenna structure；400- conductive coil；The first sub-portion of 401-；The second sub-portion of 402-；411- pedestal； 412- radio-frequency signal generator；413- optical detector；The sub- epitaxial layer of 420-；The first auxiliary electrode of 421-；422- second is assisted Electrode；432- conducting wire；The first metal wire of 441-；The second metal wire of 442-；443- third metal wire；The first passivation layer of 50-；51- Second passivation layer；60- main device；61- device；611- third semiconductor layer；The 4th semiconductor layer of 612-；613- second is sent out Photosphere；The 5th semiconductor layer of 614-.

Specific embodiment

Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application is described, and is shown So, described embodiments are only a part of embodiments of the present application, instead of all the embodiments.

Hereinafter, term " first ", " second " etc. are used for description purposes only, it is not understood to indicate or imply relatively important Property or implicitly indicate the quantity of indicated technical characteristic.The feature for defining " first ", " second " etc. as a result, can be expressed Or implicitly include one or more of the features.In the description of the present application, unless otherwise indicated, the meaning of " multiple " It is two or more.

In addition, the directional terminologies such as "upper", "lower" are that the orientation put relative to the component signal in attached drawing is come in the application Definition, it should be understood that, these directional terminologies are opposite concepts, they be used for relative to description and clarification, can The variation in the orientation placed with component in reference to the accompanying drawings and correspondingly change.

A kind of intelligent terminal is provided in some embodiments of the present application.The intelligent terminal can be mobile phone, tablet computer, pen Remember sheet, personal digital assistant (personal digital assistant, PDA), vehicle-mounted computer etc..The embodiment of the present application is to upper State intelligent terminal concrete form do not do it is specifically limited.

As shown in Figure 1a, intelligent terminal 05 includes processor 06 and display module 01.The processor 06 is aobvious for controlling Show that mould group 01 shows image.

Display module 01 in the intelligent terminal 05 includes substrate 10 as shown in Figure 1 b and more on the substrate 10 A LED chip arranged in a matrix 11.Each LED chip 11 is a sub-pixel (sub pixel) 101.

Adjacent at least three issue the sub-pixel 101 of different colours light, such as the son for issuing red (red, R) light Pixel 101, the sub-pixel 101 for issuing green (green, G) light, and the sub-pixel for issuing blue (blue, B) light 101, constitute the pixel (pixel) 02 that can issue white light.

It should be noted that in the embodiment of the present application, above-mentioned LED chip 11 can be micro LED chip.

As shown in Fig. 2, LED chip 11 includes substrate 100 (such as sapphire), the main device on above-mentioned substrate 100 60.Main device 60 includes main epitaxial layer 110, first electrode 121 and second electrode 122.

In addition, as shown in Fig. 2, above-mentioned main epitaxial layer 110 includes the first semiconductor layer of the first semiconductor layer 111 and covering First functional layer 201 of 111 upper surface part subregions.First functional layer 201 includes the second semiconductor layer 112 and the first hair Photosphere 113.First luminescent layer 113 is between the first semiconductor layer 111 and the second semiconductor layer 112.

In the case, the first semiconductor layer 111 can be n type semiconductor layer.It is exemplary, it can be in pure semiconductor material Pentad is adulterated in material, such as gallium nitride (GaN), such as phosphorus forms above-mentioned n type semiconductor layer.In n type semiconductor layer, from By electronics to be mostly sub, hole is few son, conductive mainly by free electron.The concentration of more sons (free electron) is higher, N-type semiconductor The electric conductivity of layer is stronger.

Second semiconductor layer 112 can be p type semiconductor layer.It is exemplary, it can be in pure semiconductor material, such as gallium nitride (GaN) triad is adulterated in, such as boron forms aforementioned p-type semiconductor layer.In p type semiconductor layer, hole is mostly sub, freely Electronics is few son, mainly by hole conduction.The concentration of more sons (hole) is higher, and the electric conductivity of p type semiconductor layer is stronger.

Based on this, first electrode 121 is set to the upper surface with the first semiconductor layer 111, and is located at the first semiconductor layer The region that 111 upper surfaces are not covered by the first functional layer 201, the region for enable first electrode 121 with this first half Conductor layer 111 couples.

The first electricity in the case where the first semiconductor layer 111 is n type semiconductor layer, with the coupling of the first semiconductor layer 111 Pole 121 is N electrode.

In addition, second electrode 122 is set to the upper surface of the second semiconductor layer 112, and with 112 coupling of the second semiconductor layer It connects.

The second electricity in the case where the second semiconductor layer 112 is p type semiconductor layer, with the coupling of the second semiconductor layer 112 Pole 122 is P electrode.

It should be noted that " coupling " in the application refers to that two elements can be directly electrically connected, or pass through Between element be electrically connected.

Based on this, PN junction is formed between above-mentioned first semiconductor layer 111 and the second semiconductor layer 112.Above-mentioned first shines Layer 113 is multiple quantum well layer.Since first luminescent layer 113 is set to the first semiconductor layer 111 and the second semiconductor layer 112 Between, i.e. the first luminescent layer 113 is located at the active area of above-mentioned PN junction.

In addition, above-mentioned LED chip 11 can use flip-chip (flip chip) technique, as shown in figure 3, upside-down mounting is in base On plate 10.Substrate 10 can be printed circuit board (printed circuit board, PCB), the flexible print circuit of hard Plate (flexible printed circuit board, FPCB) or silicon substrate.It is provided on substrate 10 each for driving The luminous driving circuit (not shown) of LED chip 11.

When the first electrode into each LED chip 11 respectively of each driving circuit on the substrate 10 in display module 01 121 and second electrode 122 provide voltage when, under the action of extra electric field, in the first semiconductor layer 111 (i.e. N-type semiconductor) Electronics and the hole in the second semiconductor layer 112 (i.e. P-type semiconductor) it is compound in the first luminescent layer 113, and with photon Form issues energy, so that the main device 60 in LED chip 11 shines, reaches driving display module 01 and performs image display Purpose.

The embodiment of the present application provides a kind of preparation method of LED chip 11, as shown in figure 4, this method include S101~ S104。

Above-mentioned main device 60 is made in S101, each establishment region 30 on substrate 100.

Wherein, substrate 100 is as shown in figure 5, include the multiple establishment regions 30 defined by the Cutting Road 31 that transverse and longitudinal is intersected.

The preparation method of substrate 100 includes using crystal growth technique, prepares sapphire (aluminum oxide (Al₂O₃)) brilliant Scapus.Then the lens cylinder is sliced, polishing obtains above-mentioned substrate 100.Exemplary, the thickness of the substrate 100 can be 2Inch or so.

In addition, the main epitaxial layer 110 of main device 60, in addition to include the first semiconductor layer 111, the second semiconductor layer 112 with And first other than luminescent layer 113, further includes semiconductor nucleating layer 114 as shown in Figure 6 a, undoped semiconductor layer 115, low-mix Miscellaneous semiconductor layer 116, superlattice layer 117, electronic barrier layer 118, ohmic contact layer 119 and Distributed Bragg Reflection layer (distributed brag reflection, DBR) 120.

Based on this, the production method of main device 60 includes: to grow firstly, in the upper surface of substrate 100 as shown in Figure 6 a Semiconductor (such as GaN) nucleating layer 114.The thickness of semiconductor nucleating layer 114 can be 25nm or so.Semiconductor nucleating layer 114 As buffer layer, for being adapted between substrate 100 and the 114 top film layer of GaN nucleating layer.

Next, growing undoped semiconductor (such as GaN) layer 115 in the upper surface of semiconductor nucleating layer 114.It is non-to mix The thickness of miscellaneous semiconductor layer 115 can be 1um or so.Undoped semiconductor layer 115 is used to improve the thickness of entire main epitaxial layer 110 Degree, enables its thickness to reach design requirement.

Next, growing above-mentioned first semiconductor layer 111, i.e. N-type semiconductor in undoped 115 upper surface of semiconductor layer Layer.The thickness of first semiconductor layer 111 can be 2um, and doping concentration can be 5E18/cm³.First semiconductor layer 111 is used In offer electronics.

Next, growing low-doped semiconductor (for example, GaN) layer 116 in the upper surface of the first semiconductor layer 111.Low-mix The thickness of miscellaneous semiconductor layer 116 can be 300nm, doping concentration 5E17/cm³.Low-doped semiconductor layer 116 is for improving LED The voltage endurance capability of chip 11.

Next, growing superlattice layer 117 in the upper surface of low-doped semiconductor layer 116.The superlattice layer 117 is most main It to be made of the GaN and indium gallium nitride (InGaN) in period, thickness can be 2.5nm/5nm.The superlattice layer 117 is for improving The luminous efficiency of first luminescent layer 113.

Next, growth is about the multiple quantum well layer in 12 periods as the first luminescent layer in the upper surface of superlattice layer 117 113.The quantum well layer is mainly made of InGaN and GaN, and thickness can be 3nm to 7nm.Wherein it is possible to by adjusting the first hair The ratio of element In in photosphere 113 allows the first luminescent layer 113 to issue the light of different colours, such as issues wavelength and exist The light (i.e. blue light) of 450nm.

Next, growing electronic barrier layer 118 in the upper surface of the first luminescent layer 113.Constitute the electronic barrier layer 118 Material can be aluminum gallium nitride (AlGaN), thickness can be 70nm.The electronic barrier layer 118 is used for the electronics for stopping to overflow, Improve the luminous efficiency of the first luminescent layer 113.

Next, in the upper surface of electronic barrier layer 118, two semiconductor layer 112 of growth regulation, i.e. p type semiconductor layer.This The thickness of two semiconductor layers 112 can be 150nm, and doping concentration can be 1E20/cm³.Second semiconductor layer 112 is for providing Hole.

Next, growing ohmic contact layer 119 in the upper surface of the second semiconductor layer 112.The ohmic contact layer 119 can Think the InGaN, doping concentration 1E20/cm of N doping³, thickness can be 1.5nm.Ohmic contact layer 119 is for improving the The contact performance of two electrodes 122 and the second semiconductor layer 112.

In addition, in above-mentioned LED chip 11 as shown in figure 3, upside-down mounting is in the case where on substrate 10, in order to improve LED chip 11 light extraction efficiency, as shown in Figure 6 a, in the upper surface of ohmic contact layer 119, growth distribution formula Bragg reflecting layer 120.It should The light that Distributed Bragg Reflection layer 120 can issue the first luminescent layer 113 reflects, so that more light are by serving as a contrast The outgoing of 100 side of bottom.

It can be seen from the above, first electrode 121 needs to couple with the first semiconductor layer 111, therefore making main epitaxial layer After each tunic layer in 110, it is also necessary to by by the film layer on the first semiconductor layer 111, i.e., above-mentioned first functional layer 201 A part removal, as shown in Figure 6 a, so that 111 upper surface of the first semiconductor layer has the area not covered by the first functional layer 201 Domain, the region are used to couple with first electrode 121.

Wherein, when the structure of main device 60 is as shown in Figure 6 a, above-mentioned first functional layer 201 further includes low-doped semiconductor Layer 116, superlattice layer 117,118 ohmic contact layer 119 of electronic barrier layer and Distributed Bragg Reflection layer 120.

In addition, when above-mentioned main epitaxial layer 110 further includes the Distributed Bragg Reflection layer positioned at 119 top of ohmic contact layer When 120, as shown in Figure 6 b, it is also necessary to remove a part of Distributed Bragg Reflection layer 120, to expose ohmic contact layer 119 a part, for being contacted with second electrode 122, to realize the coupling of second electrode 122 and the second semiconductor layer 112.

After executing above-mentioned steps, the preparation of epitaxial wafer can be completed.It can be seen from the above, when by adjusting the first luminescent layer The ratio of element In in 113 can make the first luminescent layer 113 issue the light of different colours.First in one epitaxial wafer Luminescent layer 113 is that a continuous flood is laid on substrate 100, so an epitaxial wafer is typically only capable to issue a kind of color Light.

In the case, in order to prepare the LED chip 11 that can issue R light, G light and B light respectively, as shown in fig. 7, The epitaxial wafer 03_a for issuing R light, the epitaxial wafer 03_b for issuing G light can be produced, and for issuing B light Epitaxial wafer 03_c.

Next, making first electrode 121 and second electrode 122 in each establishment region 30 of extension on piece.

Specifically, as shown in Figure 8 a, in the upper surface of above-mentioned main epitaxial layer 110, i.e., coating photoresist 20 in epitaxial surface.With The photoresist 20 is for positive photoresist.

Then, as shown in Figure 8 b, using mask plate 21, on the above-mentioned epitaxial wafer, to pre-seting first electrode 121 and Region other than the position of two electrodes 122 carries out illumination, makes its solidification.First electrode 121 and second electrode 122 are on mask plate Light shielding part block under the action of, be not affected by the irradiation of light, and do not occur solidification (portion of shade is beaten in figure in photoresist 20 Point).

Next, as shown in Figure 8 c, not solidified photoresist is washed using developer solution, to expose main epitaxial layer 110 Portion of epi face.

For example, exposing the partial region of 111 upper surface of the first semiconductor layer in main epitaxial layer 110, it is used for and the first electricity Pole 121 couples, and exposes the partial region of 119 upper surface of ohmic contact layer in main epitaxial layer 110, is used for and the second electricity Pole 122 couples.

Next, forming metal layer 22 as Fig. 8 d is deposited in the epitaxial surface of main epitaxial layer 110 using electron beam, such as thick Degree can be 1.5 μm.

Next, remaining photoresist 20 is removed using liquid is removed photoresist, thus by the metal layer 22 above photoresist It removes together.In the case, as figure 8 e shows, pre-set at 122 position of second electrode retain metal layer as this second Electrode 122, and pre-set a part of the metal layer retained at 121 position of first electrode as first electrode 121.

In addition, in order to enable the upper surface of first electrode 121 and second electrode 122 can be put down substantially as illustrated in fig. 8f Together, above-mentioned coating photoresist can be used again, and exposure mask, exposure, development and evaporated metal layer, removal are carried out to photoresist The step of photoresist, goes out to increase the thickness of remaining metal layer, to be formed as illustrated in fig. 8f pre-seting 121 position of first electrode First electrode 121.

It is exemplary, in order to improve the contact performance of first electrode 121, second electrode 122 and main epitaxial layer 110, such as Fig. 8 g Shown, when first electrode 121 is N electrode, first electrode 121 includes two metal layers (B1 and C1).

Wherein, the material for the metal layer B1 being in contact with the first semiconductor layer 111 in main epitaxial layer 110 can be titanium (Ti)；Metal layer C1 away from the first semiconductor layer 111 is golden (Au).

When second electrode 122 is P electrode, second electrode 122 may include two metal layers (B2 and C2).

Wherein, the material with the metal layer B2 of the second semiconductor layer 112 coupling in main epitaxial layer 110 is aluminium (Al)；Back Metal layer C2 from the second semiconductor layer 112 is golden (Au).

It should be noted that above-mentioned is the explanation carried out so that photoresist 20 is positive photoresist as an example.When photoresist 20 uses negtive photoresist When, it is not affected by the partially solidified of light irradiation, does not dissolve in developer solution.The part irradiated by light does not solidify, is dissolved in developer solution. Remaining step is same as above, and details are not described herein again.

After executing above-mentioned S101, the structure of formation is as shown in Fig. 8 h, and multiple main devices 60 are arranged in matrix form, and each The main epitaxial layer 110 of a main device 60 is connected.

S102, the multiple antenna structures 40 as shown in Figure 9 of production.

As shown in figure 9, mutiple antennas structure 40 and multiple establishment regions 30 correspond.Each antenna structure 40 is right with it The first electrode 121 set up in region 30 and second electrode 122 answered couple, and form chip die 300.

Before chip die 300 is cut to isolate LED chip 11, antenna structure 40 for receiving RF signal, and Potential difference is generated between the same first electrode 121 and second electrode 122 set up in region 30.

After antenna structure 40 receives and receives radio frequency (radio frequency, RF) signal, antenna structure 40 can be The first electrode 121 and second electrode 122 coupled in establishment region 30 corresponding to the antenna structure 40 with the antenna structure 40 Between induce electromotive force.The electromotive force can make have potential difference between first electrode 121 and second electrode 122, therefore Electric field is formed between first electrode 121 and second electrode 122.

The electric field enables to 111 (the i.e. N-type half of the first semiconductor layer in establishment region 30 corresponding to antenna structure 40 Conductor) in electronics and the hole in the second semiconductor layer 112 (i.e. P-type semiconductor) it is compound in the first luminescent layer 113, and with The form of photon issues energy, so that the main device 60 set up in region 30 shines.

S103, PL test is carried out to chip die 300.

RF signal, and each main device in acquisition chip wafer 300 are sent to mutiple antennas structure 40 as shown in Figure 9 60 light emission luminance tests whether each main device 60 can work normally according to the light emission luminance of each main device 60.

So, can using S103 provide PL detection mode to each main device 60 in the chip die 300 into Row detection, and judge whether it fails (know good die, KGD).So as to which solve can not be to large number of LED core The problem of piece 11 is detected.

S104, chip die 300 is separated along Cutting Road, obtains multiple LED chips 11.

In the case, as shown in Figure 10, the chip die 300_a for sending out R light is separated, can be obtained multiple For sending out the LED chip 11_a of R light.

Chip die 300_b for sending out G light is separated, can be obtained multiple for sending out the LED chip 11_ of G light b。

Chip die 300_b for sending out B light is separated, can be obtained multiple for sending out the LED chip 11_ of B light c。

Next, above-mentioned LED chip 11_a, LED chip 11_b and LED chip 11_c are carried out batch transfer, and press According to certain pixel arrangements upside-down mounting in substrate 10, forming display module 01 as shown in Figure 10.

It can be seen from the above, antenna structure 40 can when receiving RF signal so that the antenna structure 40 coupled Potential difference is generated between one electrode 121 and second electrode 122, to drive in establishment region 30 corresponding to the antenna structure 40 Main device 60 shines.Wherein, which is AC signal.

In addition, the LED chip 11 that the separation of chip die 300 is formed, and by 11 upside-down mounting of LED chip on substrate 10, shape After above-mentioned display module 01, during which shows, the first electrode 121 and second of each LED chip 11 Electrode 122 receives direct current signal, carries out luminous.Therefore, above-mentioned direct current signal will not make antenna structure 40 in display module 01 Electromotive force is induced during display, to will not impact to the display of display module 01.

Below to the specific set-up mode of antenna structure 40 in chip die 300, and to chip die 300 cut after, The structure of obtained LED chip 11 carries out detailed illustration.For convenience of explanation, following embodiment is to set up region 30 length L (as shown in Figure 9) is 300 μm, the explanation that width B is carried out for being 100 μm.In the case, by chip After wafer 300 is separated, the specification of any one LED chip 11 of acquisition is approximately 300 μm of 100 μ m.

Example one

In this example, above-mentioned S102 production antenna structure 40 is included in main 110 outside of epitaxial layer, makes a plurality of and main extension 110 insulation of layer, conductive coil 400 as shown in fig. 11a.

The both ends of every conductive coil 400 are electric with the first electrode 121 being located in same establishment region 30 and second respectively Pole 122 is in contact, and at least part of every conductive coil 400 is located at the Cutting Road between two neighboring establishment region 30 In 31.

In some embodiments of the present application, as shown in fig. 11a, above-mentioned first electrode 121 (or second electrode 122) can be with In conductive coil 400.In addition, any two circles coil is non-intersecting in conductive coil 400, i.e., the conductive coil 400 is each Orthographic projection no overlap region of the part on main epitaxial layer 110.

It is exemplary, in the case where the specification of LED chip 11 is 100 × 300 μm, when conductive coil 400 is using such as Figure 11 a Shown in set-up mode when, the number of turns of the conductive coil 400 can be 8 circles.

In addition, as shown in fig. 11a, S11=250 μm of the length of outmost turns；12=120 μm of the width S of outmost turns；Innermost circle S21=80 μm of length；22=70 μm of the width S of innermost circle.

M=2 μm of the line width of the conductive coil 400.Such as Figure 11 b (O1-O1 carries out the cross-sectional view that cutting obtains along Figure 11 a) It is shown, N=1 μm of the thickness of conductive coil 400.

It should be noted that above-mentioned is only the act to the size of 400 the number of turns of conductive coil and innermost circle or outmost turns Example explanation.The application to the size respectively enclosed in conductive coil 400 without limitation, as long as can guarantee to cut to chip die 300 Before cutting to isolate LED chip 11, which can induce electromotive force, make after receiving above-mentioned RF signal Obtain has potential difference between 400 both ends of the conductive coil first electrode 121 being directly connected to and second electrode 122, with driving Main device 60 in establishment region 10 corresponding to conductive coil 400 shines.

In addition, when conductive coil 400 uses set-up mode as shown in fig. 11a, in order to enable conductive coil 400 and master Epitaxial layer 110 insulate, and as shown in figure 11b, which further includes the first passivation layer 50.

The upper surface of first passivation layer 50 is in contact with the lower surface of conductive coil 400, the following table of the first passivation layer 50 Face is in contact with the upper surface of main epitaxial layer 110.At this point, the various pieces of conductive coil 400 are all set in the first passivation layer 50 Upper surface.So, conductive coil 400 and main epitaxial layer 110 can be kept apart by the first passivation layer 50.

Wherein, the material for constituting above-mentioned first passivation layer 50 can be the resin material with insulation performance.

In this example, after executing S102 and making above-mentioned lead loop 400, can execute S103 to chip die 300 into Row PL test.

As shown in figure 12, the detection device 04 for being tested the chip die 300, including pedestal 411, radio frequency letter Number generator 412 and optical detector 413.

Wherein, pedestal 411 is used to carry the chip die 300 with above-mentioned lead loop 400.

Radio-frequency signal generator 412 can be set on pedestal 411.For example, it is set to the lower surface of the pedestal 411, and Spacing between chip die 300 can be in 1cm or so.

The radio-frequency signal generator 412 is for the antenna structure 40 in chip die 300, i.e., above-mentioned lead loop 400 Send RF signal.Exemplary, the frequency of the RF signal can be 20MHz, transmission power 10W.Said chip wafer 300 Receiving power can be 100mW.

In the case, above-mentioned lead loop 400 can be used as inductor layer, after receiving above-mentioned RF signal, can feel Electromotive force should be gone out, so that the both ends of lead loop 400 are distinguished with establishment region 30 corresponding to the lead loop 400 Potential difference is generated between the first electrode 121 being in contact and second electrode 122.

At this point, under the electric field action that first electrode 121 and second electrode 122 generate, the first semiconductor of main device 60 The hole in electronics and the second semiconductor layer 112 (i.e. P-type semiconductor) in 111 (i.e. N-type semiconductor) of layer is in the first luminescent layer It is compound in 113, and energy is issued in the form of photon, so that main device 60 shines.

Based on this, above-mentioned optical signal detector 413, such as integrating sphere, it can be set in chip die 300 away from pedestal 411 side, the i.e. upper surface of the chip die 300.After each main device 60 shines in chip die 300, optical signal is visited The light emission luminance in region 30 can be set up by each main device 60 in acquisition chip wafer 300 by surveying device 413, according to the hair of main device 60 Brightness, judge its whether normal luminous.

The collection result of above-mentioned optical signal detector 413 can be as shown in figure 13.As shown in Figure 13, according to optical signal detection The collection result of device 413, the position of the available main device 60 to non-normal luminous, i.e. bad point (use black square in figure Indicate) position.So, after being separated chip die 300 to get LED chip 11, to multiple LED cores During piece 11 carries out batch transfer, the LED chip 11 of above-mentioned bad point position can be skipped, avoids its upside-down mounting in substrate 10 On.Alternatively, can also be maintained to above-mentioned bad point position.

In addition, executing S104 after said chip wafer 300 terminates PL test and being separated to chip die 300, to obtain Obtain multiple LED chips 11.

It can be seen from the above, the main epitaxial layer 110 in each main device 60 on same chip wafer 300 is both connected to one It rises.Therefore, before separating chips wafer 300, as shown in Figure 14 a (carrying out the cross-sectional view that cutting obtains along D-D in Figure 11 a), Need to be located at the film layer in the Cutting Road 31 between two neighboring establishment region 30, such as the first passivation layer 50 and the second passivation Layer 51 and main epitaxial layer 110 remove.

It is exemplary, sense coupling (inductively couple plasma, ICP) work can be used Skill performs etching the film layer in above-mentioned Cutting Road 31, and the structure of the chip die 300 after etching is as shown in fig. 14b.By Figure 14 b Know that the two neighboring film layer set up between region 30 disconnects.

Next, cutting separation is carried out to substrate 100 at Cutting Road 31, to obtain multiple LED chips 11.

It can be seen from the above, a part of conductive coil 400 is located at cutting between two neighboring establishment region 30 in this example It cuts in 31, therefore after being separated to chip die 300, the part being located in Cutting Road 31 in conductive coil 400 is gone It removes, conductive coil 400 is disconnected in 31 position of Cutting Road.The nubbin of conductive coil 400 is located at the main extension of main device 60 110 outside of layer.

So, after executing S104, there is above-mentioned day knot in the independent LED chip 11 of any one isolated The nubbin of structure 40 (i.e. above-mentioned conductive coil 400).The nubbin of the antenna structure 40 as shown in fig. 11c, including first Metal 441, the second metal wire 442 and at least one third metal wire 443.

Wherein, the first metal wire 441, the second metal wire 442 and third metal wire 443 are as residual in conductive coil 400 The remaining structure in LED chip 11, phase between the first metal wire 441, the second metal wire 442 and third metal wire 443 Mutually insulation.So that the first electrode 121 when LED chip 11 works normally and receives direct current signal, in the LED chip 11 Electrical connection between second electrode 122 is interrupted.And then when LED chip 11 works normally, above-mentioned antenna structure 40 will not The normal luminous of LED chip 11 is impacted.

One end of first metal wire 441 is in contact with first electrode 121, and an edge of the other end and LED chip 11 is flat Together.One end of second metal wire 442 is in contact with second electrode 122, and the other end is concordant with an edge of LED chip 11.

A part of third metal wire 443 is between the first metal wire 441 and the second metal wire 442.Such as Figure 11 c institute Show, the both ends of third metal wire 443 are concordant from two different edges of LED chip 11 respectively.Alternatively, as illustrated in fig. 11d, the The both ends of three metal wires 443 and the same edge of LED chip 11 are concordant.

It should be noted that one end of above-mentioned first metal wire 441, the second metal wire 442 or third metal wire 443 with The edge of LED chip 11 concordantly refers to, after being cut to chip die 300 as shown in fig. 11a, the LED chip 11 isolated The end face of side and 443 one end of the first metal wire 441, the second metal wire 442 or third metal wire be in the same plane.

Since in chip die 300 shown in Figure 11 a, each any two circles coil of conductive coil 400 is non-intersecting, i.e., should Orthographic projection no overlap region of the various pieces of conductive coil 400 on main epitaxial layer 110, therefore, chip shown in Figure 11 a are brilliant Circle 300 cutting after, the LED chip 11 isolated as shown in fig. 11c, the first metal wire 441, the second metal wire 442 and third Orthographic projection no overlap region of the metal wire 443 on main epitaxial layer 110.

In addition, first electrode 121 is located at the LED chip 11 concordant with 443 both ends of third metal wire of third metal wire 443 The region that surrounds of edge in.

On this basis, when antenna structure 40 includes a plurality of third metal wire 443 as illustrated in fig. 11e, adjacent two Setting is spaced between third metal wire 443.

Alternatively, in other embodiments of the application, as shown in fig. 15 a, the conductor wire made when executing above-mentioned S102 Circle 400 can be between first electrode 121 and second electrode 122.

Conductive coil 400 includes the first sub-portion 401 and the second sub-portion 402 being connected.First sub-portion 401 is in main extension Orthographic projection on layer 110 has overlapping region with orthographic projection of second sub-portion 402 on main epitaxial layer 110.

At this point, the first sub-portion 401 and the second sub-portion 402 in lead loop 400 are intersected and insulation set.

In the case, in order to enable setting is isolated with main epitaxial layer 110 in conductive coil 400, if Figure 15 b is (along Figure 15 a Q1-Q1 carry out cutting, obtained cross-sectional view) shown in, which further includes the first passivation layer 50 and the second passivation Layer 51.

Wherein, the first passivation layer 50 is located between the first sub-portion 401 of conductive coil 400 and main epitaxial layer 110.Second is blunt Change layer 51 to be located between the second sub-portion 402 of conductive coil 400 and the first sub-portion 401 of conductive coil 400.

The material for constituting above-mentioned first passivation layer 50 and the second passivation layer 51 can be identical, for example, above-mentioned to have insulating properties The resin material of energy.

It so, can be by the first sub-portion 401 of conductive coil 400 and main epitaxial layer 110 by the first passivation layer 50 Keep apart.First sub-portion 401 and the second sub-portion 402 arranged in a crossed manner can be kept apart by the second passivation layer 51.

The PL test method of chip die 300 with above-mentioned conductive coil 400 is same as above, and details are not described herein again.

In the case, after carrying out PL test to chip die 300, S104 is executed to chip die shown in Figure 15 a 300, it is separated along Cutting Road 31, the part being located on Cutting Road 31 in conductive coil 400 is removed, conductive coil 400 It is disconnected in 31 position of Cutting Road.Retain in addition, being located at the part set up in region 30 in conductive coil 400.

So, after executing S104, the nubbin for the antenna structure 40 in independent LED chip 11 isolated Including the first metal 441 as shown in fig. 15 c, the second metal wire 442 and at least one third metal wire 443.

Same as above, one end of the first metal wire 441 is in contact with first electrode 121, and the one of the other end and LED chip 11 A edge is concordant.One end of second metal wire 442 is in contact with second electrode 122, an edge of the other end and LED chip 11 Concordantly.A part of third metal wire 443 is between the first metal wire 441 and the second metal wire 442.Third metal wire 443 Both ends it is concordant from two different edges of LED chip 11 respectively.Or the both ends of third metal wire 443 and LED chip 11 The same edge it is concordant.

In addition, third metal wire 443 is between first electrode 121 and second electrode 122.First metal wire 441 with Orthographic projection of at least one third metal wire 443 on main epitaxial layer 110 has overlapping region.

Wherein, overlapping part occurring in the first metal wire 441 with third metal wire 443 can be conductor wire in Figure 15 a Second sub-portion 402 of circle 400.And third metal wire 443 and the second metal wire 442 can be conductive coil 400 in Figure 15 a A part of first sub-portion 401.By Figure 15 b it is found that being arranged between the first sub-portion 401 and the second sub-portion 402 of conductive coil 400 There is the second passivation layer 52 of insulation.Therefore can make that overlapping part occurs with third metal wire 443 in the first metal wire 441 Insulation.

Example two

In this example, above-mentioned S102 production antenna structure 40 includes as illustrated in fig 16 a, in main 110 outside of epitaxial layer, making A plurality of conductive coil 400, every conductive coil 400 are located in an establishment region 30.

In this example, the both ends of every conductive coil 400 are known as first end and second end.Wherein, conductive coil 400 First end is towards first electrode 121, and the second end of conductive coil 400 is towards second electrode 122.

In the case, in order to enable the first end of conductive coil 400 and first electrode 121 couple, second end and second Electrode 122 couples, and capacitor, second end and the second electricity are formed between the first end and first electrode 121 of every conductive coil 400 Pole 122 is in contact.

Alternatively, capacitor is formed between the first end and first electrode 121 of every conductive coil 400, second end and the second electricity Capacitor is formed between pole 122.

In the case, when execute S104, to chip die 300 shown in Figure 16 a separation after, acquisition any one The structure of LED chip 11 is as shown in fig 16b.It can be seen that the LED chip 11 includes a complete above-mentioned conductive coil 400. In the LED chip 11,400 both ends of conductive coil respectively with 122 coupling of first electrode 121 and second electrode in the LED chip 11 The mode connect is same as above, and details are not described herein again.

Based on this, in some embodiments of the present application, after being separated to chip die 300 shown in Figure 16 a, acquisition In LED chip 11 shown in set-up mode Figure 16 b of lead loop 400, first electrode 121 (or second electrode 122) can be located at In conductive coil 400.In addition, orthographic projection no overlap region of the various pieces of conductive coil 400 on main epitaxial layer 110.

It is exemplary, in the case where the specification of LED chip 11 is 100 × 300 μm, when the size of conductive coil 400 uses When set-up mode as shown in fig 16b, the number of turns of the conductive coil 400 can be 6 circles.S11=250 μm of the length of outmost turns； 12=80 μm of the width S of outmost turns；S21=80 μm of the length of innermost circle；22=70 μm of the width S of innermost circle.

M=2 μm of the line width of the conductive coil 400.Such as Figure 16 c (O2-O2 carries out the cross-sectional view that cutting obtains along Figure 16 b) It is shown, N=1 μm of the thickness of conductive coil 400.

Capacitor, second end and second electrode are formed between the first end and first electrode 121 of every conductive coil 400 In the case that 122 are in contact, as shown in figure 16 c, first end and first electrode 121 of the conductive coil 400 towards first electrode 121 Between there is gap H, and orthographic projection of the conductive coil 400 on main epitaxial layer 110, with first electrode 121 in main epitaxial layer 110 On orthographic projection no overlap region.

So, conductive coil 400 can be filled towards between the first end and first electrode 121 of first electrode 121 The second passivation layer 51 with insulation performance, so that first end and first electrode of the conductive coil 400 towards first electrode 121 Capacitor can be formed between 121.

The capacitor has the function of logical exchange barrier direct current, thus after conductive coil 400 receives RF signal, Ke Yishi The coupling of the first end and first electrode 121 of existing conductive coil 400.

In addition, the second end of conductive coil 400 is in contact with second electrode 122.In the case, when conductive coil 400 After receiving RF signal, which can be used as inductor layer and induces electromotive force, and couple first at its both ends The potential for driving the LED chip 11 with above-mentioned conductive coil 400 luminous is generated between electrode 121 and second electrode 122 Difference.

Alternatively, in order to enable capacitor is formed between the first end and first electrode 121 of conductive coil 400, the application's In other embodiments, production first electrode includes as shown in figure 16d, the of main epitaxial layer 110 in executing above-mentioned S101 First electrode 121 is made on the upper surface of semi-conductor layer 111, and in first electrode 121 close to the side shape of conductive coil 400 At groove 1210.

In the application, making, there is the method for first electrode 121 of above-mentioned groove 1210 can be, using above-mentioned gluing, The techniques such as exposure mask, exposure, development and evaporated metal layer, in three times in first electrode 121, as shown in figure 16d first Part 1211, second part 1212 and Part III 1213 are made respectively, so as to be formed with groove 1210 First electrode 121.The production method of the electrode provided in S101 before specific production method can similarly obtain, no longer superfluous herein It states.

Next, the antenna structure 40 that makes in executing S102, i.e., above-mentioned conductive coil 400 include as shown in figure 16d, The first end of the conductive coil 400 protrudes into groove 1210, and between the first end of conductive coil 400 and the inner wall of groove 1210 With gap H, to form capacitor between the first end of conductive coil 400 and the inner wall of groove 1210.So that conductive coil 400 first end and first electrode 121 couples.

It should be noted that above-mentioned is the first end and first electrode 121 with conductive coil 400 towards first electrode 121 Between form capacitor, the explanation that second end carries out for being in contact with second electrode 122.In other embodiments of the application In, as shown in figure 16e, the first end of conductive coil 400 can be in contact with first electrode 121, second end and second electrode 122 Between form capacitor.And the second end of the conductive coil 400 and the mode that second electrode 122 forms capacitor are same as above, this Place repeats no more.

Alternatively, in the other embodiment of the application, in order to enable the first end and first electrode of conductive coil 400 Capacitor is formed between 121, forms capacitor between second end and second electrode 122, it, can be in first electrode 121 as shown in Figure 16 f Groove is formed towards the side of 400 first end of conductive coil, is formed in the side of second electrode 121 towards conductive coil second end Groove.So that the first end of conductive coil 400 protrudes into the groove of first electrode 121, second end protrudes into second electrode 122 Groove in.The set-up mode of above-mentioned groove is same as above, and details are not described herein again.

In the case, in order to enable conductive coil 400 and main 110 insulation set of epitaxial layer, the setting side with example one Formula is identical, which further includes first as shown in Figure 16 f, between conductive coil 400 and main epitaxial layer 110 Passivation layer 50.

It is above-mentioned be by taking the various pieces of conductive coil 400 are in the orthographic projection no overlap region on main epitaxial layer 110 as an example, it is right The explanation that the set-up mode of conductive coil 400 in LED chip 11 carries out.

In addition, the set-up mode of lead loop 400 is as illustrated in fig 17 a, above-mentioned to lead in other embodiments of the application Electric coil 400 can be between first electrode 121 and second electrode 122.

In addition, conductive coil 400 includes the first sub-portion 401 and the second sub-portion 402 being connected.First sub-portion 401 exists Orthographic projection on main epitaxial layer 110 has overlapping region with orthographic projection of second sub-portion 402 on main epitaxial layer 110.

In the case, in order to enable conductive coil 400 and main 110 insulation set of epitaxial layer, can similarly obtain with example one, As shown in Figure 17 b (Q2-Q2 in Figure 17 a carries out cutting, obtained cross-sectional view), which further includes being located at first The first passivation layer 50 between sub-portion 401 and the epitaxial surface of main epitaxial layer 110, and part are located at the first sub-portion 401 and second The second passivation layer 51 between sub-portion 402.

When using conductive coil 400 shown in Figure 17 a, one end and first electrode 121 or the second electricity of conductive coil 400 The mode that capacitor is formed between pole 122 is same as above, and details are not described herein again.

It can be seen from the above, LED chip 11 has complete conductive coil 400 in this example, i.e., when executing S102, system Each conductive coil 400 of work is located in an establishment region 30 on substrate 100.It so, can be to execution S102 The chip die 300 obtained afterwards first removes the film layer of 31 position of Cutting Road, so that in each establishment region 30 as shown in fig. 14b Main epitaxial layer 110 be spaced apart.Wherein, the mode for removing the film layer of 31 position of Cutting Road is same as above, and details are not described herein again.

Then, PL test is carried out to the chip die 300.It is exemplary, as shown in figure 18, radio-frequency signal generator 412 with Spacing between chip die 300 can be in 0.5cm or so.The frequency for the RF signal that radio-frequency signal generator 412 issues can be with For 2GHz, transmission power 5W.The reception power of said chip wafer 300 can be 300mW.

Finally, executing S104, the substrate 100 of chip die 300 is cut, is isolated each such as Figure 16 a or Figure 17 a Shown in LED chip 11.

So, by being set to the process for separating main epitaxial layer 110 for the PL testing process to chip die 300 Later, so that the order of the PL testing process of chip die 300, in the entire preparation process of LED chip 11 more posteriorly.Herein In the case of, the result of PL test can be more nearly under the practical service environment of LED chip 11, i.e., be set to LED chip 11 aobvious Show in mould group 01, environment when normal work.So as to improve the accuracy of PL test, reach the mesh for improving product quality 's.

Example three

It includes as shown in figure 19a, setting up in region 30, being formed that antenna structure 40 is made in this example, in above-mentioned S102 Sub- device 61.In addition, making a plurality of conductive coil 400 and a plurality of conducting wire 432, each establishment region in main 11 outside of epitaxial layer There is a conductive coil 400 and a conducting wire 432 in 30.

In the case, when execute S104, to chip die 300 shown in Figure 19 a separation after, acquisition any one The structure of LED chip 11 is as shown in fig. 19b.The antenna structure 40 of the LED chip 11 include sub- device 61 as shown in fig. 19b, Conducting wire 432 and conductive coil 400 positioned at main 110 outside of epitaxial layer.

Wherein, identical as example two, conductive coil 400 in LED chip 11 can no overlap everywhere, alternatively, conductor wire There are at least two parts of intersection and insulation set in circle 400, details are not described herein again.

Identical as example two, first electrode 121 or second electrode 122 can be set in conductive coil 400.Alternatively, leading Electric coil 400 can be set between first electrode 121 and second electrode 122, and details are not described herein again.

Illustratively, in the case where the specification of LED chip 11 is 100 × 300 μm, when conductive coil 400 is using as schemed Shown in 19b when set-up mode, the number of turns of the conductive coil 400 can be 5 circles.S11=150 μm of the length of outmost turns；It is outermost 12=80 μm of the width S of circle；S21=80 μm of the length of innermost circle；22=50 μm of the width S of innermost circle.

M=2 μm of the line width of the conductive coil 400.Such as Figure 19 c (O3-O3 carries out the cross-sectional view that cutting obtains along Figure 19 b) It is shown, N=1 μm of the thickness of conductive coil 400.

In addition, sub- device 61 include as shown in Figure 19 c (O3-O3 in Figure 19 b carries out the cross-sectional view that cutting obtains), Sub- epitaxial layer 420 and the first auxiliary electrode 421 and the second auxiliary electrode 422 being set on sub- epitaxial layer 420.

110 insulation set of main epitaxial layer of sub- epitaxial layer 420 and main device 60.It is exemplary, it can use etching technics will Sub- epitaxial layer 420 is spaced apart with main epitaxial layer 110, and filling has the passivation layer of insulation performance in gap.

60 conducting direction of main device is directed toward first electrode 122 by second electrode 121.The conducting direction of the sub- device 61 is by Two auxiliary electrodes 422 are directed toward the first auxiliary electrode 421.

In addition, one end of conductive coil 400 is in contact with first electrode 121, the other end connects with the second auxiliary electrode 422 Touching.

As described in Figure 19 d (carrying out the obtained cross-sectional view of cutting along Q3-Q3 in Figure 19 b), one end of conducting wire 432 and first auxiliary Electrode 421 is helped to be in contact, the other end is in contact with second electrode 121.

It should be noted that in some embodiments of the present application, in order to simplify manufacture craft, as shown in Figure 19 d, sub- device The sub- epitaxial layer 420 of part 61 and the main epitaxial layer 110 of main device 60 can be located on same substrate 100.Alternatively, the application's In other embodiments, the passivation layer for insulation can be made, then makes above-mentioned sub- device again after having made main device 60 Part 61.

In addition, in order to simplify manufacture craft, and be conducive to the optimal setting in cloth member space in LED chip, in main device 60 First electrode 121, the first auxiliary electrode 421 of second electrode 122 and sub- device 61, the second auxiliary electrode 422 it is transversal Face it is (parallel with the loading end of substrate 100) be rectangle when, the long side or short side of above-mentioned electrode cross-section can be with LED chips 11 Sides aligned parallel.Alternatively, the long side or short side of above-mentioned electrode can also be with LED chips 11 in other embodiments of the application Edge intersection.

The application is in same LED chip 11, sub- device 61 and main device 60 and first electrode 121, second electrode 122, the first auxiliary electrode 421, the second auxiliary electrode 422 positional relationship without limitation, as long as can satisfy sub- device 61 The main epitaxial layer 110 of sub- epitaxial layer 420 and main device 60 insulate.

The set-up mode of the sub- epitaxial layer 420 of sub- device 61 is illustrated below.

In some embodiments of the present application, as illustrated in fig. 20, the sub- epitaxial layer 420 of sub- device 61 includes that third is partly led Second functional layer 202 of body layer 611 and covering 611 upper surface part subregion of third semiconductor layer.

Second functional layer 202 includes the 4th semiconductor layer 612 and the second luminescent layer 613.Second luminescent layer 613 is located at the Between three semiconductor layers 611 and the 4th semiconductor layer 612.

In the case, the first auxiliary electrode 421 is set to the upper surface of third semiconductor layer 611, and partly leads with third Body layer 611 couples.

Second auxiliary electrode 422 is set to the upper surface of the 4th semiconductor layer 612, and couples with the 4th semiconductor layer 612.

Third semiconductor layer 611, second in some embodiments of the present application, in the sub- epitaxial layer 420 of sub- device 61 Functional layer 202 and third semiconductor layer 611 can respectively with the first semiconductor layer in the main epitaxial layer 110 of main device 60 111, the material of the second luminescent layer 113 and the second semiconductor layer 112 is identical.

In addition, in addition to third semiconductor layer 611, the second functional layer 202 and third in the sub- epitaxial layer 420 of sub- device 61 Other than semiconductor layer 611, the set-up mode of other film layers can also be with corresponding film layer in the main epitaxial layer 110 of main device Structure is identical with position.

In the case, the third semiconductor layer 611 in sub- device 61 is n type semiconductor layer, the 4th semiconductor layer 612 When for p type semiconductor layer, there is PN junction in sub- device 6161.

In addition, the material of the first auxiliary electrode 421 of composition and the material of composition first electrode 121 can be identical.Constitute the The material of two auxiliary electrodes 422 can be identical with the material for constituting second electrode 122.Details are not described herein.

Alternatively, in other embodiments of the application, the set-up mode of the sub- epitaxial layer 420 of sub- device 61, such as Figure 20 b Shown, the first auxiliary electrode 421 and the second auxiliary electrode 422 are respectively positioned on the upper surface of the 5th semiconductor layer 614, and with the 5th half Conductor layer 614 couples.5th semiconductor layer 614 can be n type semiconductor layer.

In the case, the first auxiliary electrode 421 is N electrode, and the first auxiliary electrode 421 may include two metal layers (B1 and C1).Wherein, the material for the metal layer B1 being in contact with the 5th semiconductor layer 614 in sub- epitaxial layer 420 can be titanium (Ti)；Metal layer C1 away from the 5th semiconductor layer 614 is golden (Au).

Second auxiliary electrode 422 is P electrode, and the second auxiliary electrode 422 may include two metal layers (B2 and C2).Its In, the material for the metal layer B2 being in contact with the 5th semiconductor layer 614 in sub- epitaxial layer 420 is nickel (Ni)；Away from the 5th half The metal layer C2 of conductor layer 614 is golden (Au).

In the case, in sub- device 61, the first auxiliary electrode 421 (N electrode) is led with the 5th half in sub- epitaxial layer 420 The 5th semiconductor layer 614 in body layer 614 and the second auxiliary electrode 422 (P electrode) and sub- epitaxial layer 420 forms Schottky Knot.

When group device 61 uses the set-up mode of schottky junction as shown in fig. 20b, relative to using shown in Figure 20 a For the set-up mode of PN knot, the film layer quantity in the sub- epitaxial layer 420 of sub- device 61 is few, and structure is simpler.

Due to having after being cut to chip die 300, in any one LED chip 11 of acquisition complete in this example Antenna structure 40, including above-mentioned sub- device 61, conducting wire 432 and conductive coil 400.Therefore identical as example two, it can be right The chip die 300 obtained after S102 is executed, the film layer of 31 position of Cutting Road is first removed as shown in fig. 14b, so that each establishment Main epitaxial layer 110 in region 30 is spaced apart.Wherein, the mode for removing the film layer of 31 position of Cutting Road is same as above, herein not It repeats again.

Then, PL test is carried out to the chip die 300 as shown in figure 18.It is exemplary, radio-frequency signal generator 412 and core Spacing between wafer 300 can be in 2cm or so.The frequency of RF signal that radio-frequency signal generator 412 issues can be 30GHz, transmission power 30W.The reception power of said chip wafer 300 can be 50mW.

It in the case, is N electrode with first electrode 121, second electrode 122 is for P electrode.When antenna structure 40 In conductive coil 400 when receiving above-mentioned RF signal, as conducting direction second electrode as shown in Figure 19 b of main device 60 122 are directed toward first electrode 121, so main device 60 is not turned on when the positive pressure in RF signal is applied to first electrode 121, institute Potential difference will not be generated between first electrode 121 and second electrode 122.

In addition, being applied in sub- device 61 in the positive pressure (such as 10V) in the RF signal as AC signal second auxiliary When helping electrode 422, the voltage in the first electrode 121 of main device 60 can be 0V.

Since the conducting direction of sub- device 61 is directed toward the first auxiliary electrode 421, sub- device by the second auxiliary electrode 422 61 are connected, and the voltage that the first auxiliary electrode 421 on sub- device 61 receives remains as positive pressure, example after certain pressure drop Such as 8V.

Since the first auxiliary electrode 421 of sub- device 61 is electrically connected with the second electrode 122 of main device by conducting wire 432, So the voltage in second electrode 122 is identical as the first auxiliary electrode 421, it is positive pressure, i.e., above-mentioned 8V.In the case, main device Potential difference is generated between the first electrode 121 (0V) and second electrode 122 (8V) of part 60, so as to drive main device to shine, Realize PL detection.

Multiple LED chips 11 are being obtained to the separation of chip die 300 after PL is detected, and LED chip 11 is being arranged After in display module 01, when needing LED chip 11 to shine, second electrode 122 of the meeting into LED chip 11 applies positive pressure, First electrode 121 applies negative pressure.

In the case, LED chip 11 can work normally.And 11 neutron device 61 of LED chip, since its conducting direction is Second auxiliary electrode 422 is directed toward the first auxiliary electrode 421, and second auxiliary electrode 422 can not obtain positive pressure, so will not lead It is logical, so as to avoid during display, influence of the sub- device 61 to 11 light emission luminance of LED chip.

In this example, what the separate mode of LED chip 11 and the technical effect of PL test method and aforementioned exemplary provided Scheme is identical, and details are not described herein again.

The above, the only specific embodiment of the application, but the protection scope of the application is not limited thereto, it is any Change or replacement within the technical scope of the present application should all be covered within the scope of protection of this application.Therefore, this Shen Protection scope please should be based on the protection scope of the described claims.

Claims

1. a kind of Light-emitting diode LED chip, which is characterized in that including main device and antenna structure, the main device includes master Epitaxial layer, first electrode and second electrode；

The main epitaxial layer includes the first semiconductor layer and the first function for covering the first semiconductor layer upper surface part subregion Ergosphere；First functional layer includes the second semiconductor layer and the first luminescent layer；First luminescent layer is located at described the first half Between conductor layer and second semiconductor layer；

The first electrode is set to the upper surface of first semiconductor layer, and couples with first semiconductor layer；

The second electrode is set to the upper surface of second semiconductor layer, and couples with second semiconductor layer；

The antenna structure and the first electrode and the second electrode couple；The antenna structure is for receiving radio frequency letter Number, and potential difference is generated between the first electrode and the second electrode.

2. LED chip according to claim 1, which is characterized in that the antenna structure includes being located at the main epitaxial layer The conductive coil in outside；

The first end of the conductive coil and the first electrode form capacitor, and second end is in contact with the second electrode；

Alternatively,

The first end of the conductive coil and the first electrode form capacitor, and second end and the second electrode form capacitor.

3. LED chip according to claim 2, which is characterized in that

The first electrode is fluted close to the setting of the side of the conductive coil, and the first end of the conductive coil protrudes into described In groove, and there is gap between the first end of the conductive coil and the inner wall of the groove, in the conductive coil Capacitor is formed between first end and the inner wall of the groove.

4. LED chip according to claim 1, which is characterized in that

The conducting direction of the main device is directed toward the first electrode by the second electrode；

The antenna structure includes: sub- device, conducting wire and conductive coil on the outside of the main epitaxial layer；

The sub- device includes sub- epitaxial layer and the first auxiliary electrode being set on the sub- epitaxial layer and the second auxiliary electricity Pole；The sub- epitaxial layer and the main epitaxial layer insulation set；

The conducting direction of the sub- device is directed toward first auxiliary electrode by second auxiliary electrode；

One end of the conductive coil is in contact with the first electrode, and the other end is in contact with second auxiliary electrode；

One end of the conducting wire is in contact with first auxiliary electrode, and the other end is in contact with the second electrode.

5. LED chip according to claim 4, which is characterized in that the sub- epitaxial layer includes third semiconductor layer and covers Cover the second functional layer of the third semiconductor layer upper surface part subregion；Second functional layer include the 4th semiconductor layer and Second luminescent layer；Second luminescent layer is between the third semiconductor layer and the 4th semiconductor layer；

First auxiliary electrode is set to the upper surface of the third semiconductor layer, and couples with the third semiconductor layer；

Second auxiliary electrode is set to the upper surface of the 4th semiconductor layer, and couples with the 4th semiconductor layer.

6. LED chip according to claim 4, which is characterized in that the sub- epitaxial layer includes the 5th semiconductor layer；

First auxiliary electrode and second auxiliary electrode are respectively positioned on the upper surface of the 5th semiconductor layer, and with it is described The coupling of 5th semiconductor layer.

7. LED chip according to claim 2 or 4, which is characterized in that any two circles coil not phase in the conductive coil It hands over.

8. a kind of Light-emitting diode LED chip, which is characterized in that the nubbin including main device and antenna structure, the master Device includes main epitaxial layer, first electrode and second electrode:

The nubbin of the antenna structure includes first for being located on the outside of the main epitaxial layer, and insulating with the main epitaxial layer Metal wire, the second metal wire and at least one third metal wire；First metal wire, second metal wire and institute State third metal wire mutually insulated；

One end of first metal wire is in contact with the first electrode, and an edge of the other end and the LED chip is flat Together；

One end of second metal wire is in contact with the second electrode, and an edge of the other end and the LED chip is flat Together；

A part of the third metal wire is between first metal wire and second metal wire；

The both ends of the third metal wire and the same edge of the LED chip are concordant；Alternatively, the two of the third metal wire It holds concordant from two different edges of the LED chip respectively.

9. a kind of preparation method of Light-emitting diode LED chip characterized by comprising

On substrate each is set up and makes main device in region, and the substrate includes being defined by the Cutting Road that transverse and longitudinal is intersected Multiple establishment regions；The main device includes main epitaxial layer, first electrode and second electrode；The main epitaxial layer includes the first half Conductor layer and the first functional layer for covering the first semiconductor layer upper surface part subregion；First functional layer includes second Semiconductor layer and the first luminescent layer；First luminescent layer be located at first semiconductor layer and second semiconductor layer it Between；The first electrode is set to the upper surface of first semiconductor layer, and couples with first semiconductor layer；Described Two electrodes are set to the upper surface of second semiconductor layer, and couple with second semiconductor layer；

Mutiple antennas structure is made, multiple antenna structures and multiple establishment regions correspond, each antenna The first electrode and second electrode coupling in the corresponding establishment region of structure, form chip die；Institute Antenna structure is stated for receiving radiofrequency signal, and in the same first electrode and the second electrode set up in region Between generate potential difference；

Radiofrequency signals are sent to multiple antenna structures, and acquire shining for each main device in the chip die Brightness tests whether each main device can work normally according to the light emission luminance of each main device；

The chip die is separated along the Cutting Road, obtains multiple LED chips.

10. the preparation method of LED chip according to claim 9, which is characterized in that

Making the antenna structure includes: to make a plurality of conductive coil on the outside of the main epitaxial layer；

The both ends of every conductive coil are respectively and positioned at the same first electrode set up in region and second electricity Pole is in contact, and at least part of every conductive coil is located at the two neighboring cutting set up between region In road.

11. the preparation method of LED chip according to claim 9, which is characterized in that

Making the antenna structure includes: to make a plurality of conductive coil, every conductive coil on the outside of the main epitaxial layer In an establishment region；

Capacitor, second end and the second electrode phase are formed between the first end and the first electrode of every conductive coil Contact；

Alternatively,

Form capacitor between the first end and the first electrode of every conductive coil, second end and the second electrode it Between form capacitor.

12. the preparation method of LED chip according to claim 11, which is characterized in that

Production first electrode includes: that the first electrode is made on the upper surface of first semiconductor layer, and described the The side of one electrode forms groove；

The first end that the conductive coil includes: the conductive coil is made to protrude into the groove, and the conductive coil There is gap between first end and the inner wall of the groove, with the inner wall of the first end of the conductive coil and the groove it Between form capacitor.

13. the preparation method of LED chip according to claim 9, which is characterized in that

Making the antenna structure includes: to form sub- device in the establishment region, the sub- device include with outside the master Prolong the sub- epitaxial layer of layer insulation, and the first auxiliary electrode and the second auxiliary electrode on the sub- epitaxial layer；The son The conducting direction of device is directed toward first auxiliary electrode by second auxiliary electrode；

Make the antenna structure further include: on the outside of the main epitaxial layer, make a plurality of conductive coil and a plurality of conducting wire, each Setting up has a conductive coil and a conducting wire in region；

It is in contact positioned at each described one end for setting up the conductive coil in region with the first electrode, the other end and institute The second auxiliary electrode is stated to be in contact；

It is in contact positioned at each described one end for setting up a conducting wire in region with first auxiliary electrode, the other end It is in contact with the second electrode；

The conducting direction of the main device is directed toward the first electrode by the second electrode.

14. a kind of display module, which is characterized in that including substrate and array arrangement in the substrate such as claim The described in any item LED chips of 1-8；

Each LED chip is a sub-pixel.

15. a kind of intelligent terminal, which is characterized in that including processor and display module as claimed in claim 14, the place Reason device shows image for controlling the display module.