CN110162494A - A kind of field programmable gate array chip and data interactive method - Google Patents

A kind of field programmable gate array chip and data interactive method Download PDF

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Publication number
CN110162494A
CN110162494A CN201910351369.XA CN201910351369A CN110162494A CN 110162494 A CN110162494 A CN 110162494A CN 201910351369 A CN201910351369 A CN 201910351369A CN 110162494 A CN110162494 A CN 110162494A
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substrate
metallic conductor
dynamic random
memory module
random memory
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CN110162494B (en
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谭经纶
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ICLeague Technology Co Ltd
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ICLeague Technology Co Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package

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  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computing Systems (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

The embodiment of the invention discloses a kind of programmable gate array chips, comprising: dynamic random memory module, logic module;Wherein, the dynamic random memory module includes the first substrate and the first metallic conductor for being set on first substrate;The logic module includes the second substrate and the second metallic conductor for being set on second substrate;First substrate of the dynamic random memory module and the second substrate attaching of the logic module are arranged, and the first metallic conductor of the dynamic random memory module and the conducting of the second metallic conductor of the logic module;The dynamic random memory module, for the access to be formed and logic module progress data interaction to be connected by first metallic conductor and second metallic conductor.The embodiment of the present invention also discloses a kind of data interactive method simultaneously.

Description

A kind of field programmable gate array chip and data interactive method
Technical field
The present invention relates to technical field of integrated circuits more particularly to a kind of field programmable gate array chip and data Exchange method.
Background technique
Field programmable gate array (Field-Programmable Gate Array, FPGA), is a kind of Programmable Part, designer can be realized quickly exploitation, be imitated by the connection structure and logic inside software tool change, configuration device True and test.
In practical applications, traditional fpga chip is normally based on Static RAM (Static Random- Access Memory, SRAM) structure.The basic structure of fpga chip based on SRAM memory as shown in Figure 1 is by 7 Divide and constitute, is respectively as follows: programmable input-output unit (Input Output Block, IOB), basic programmable logic cells It is (Configurable Logic Block, CLB), Clock management module (Digital Clock Manager, DCM), embedded RAM, interconnection resource abundant, embedded bottom functional unit (not shown) and embedded application specific hardware modules (are not shown in figure Out).Wherein, embedded RAM is SRAM.
In practical applications, the metal-oxide-semiconductor as used in the SRAM element in insertion FPGA is relatively more, so that fpga chip Area occupied it is relatively large, integrated level is low.Also, the limited storage space of included SRAM inside FPGA, as progress great Rong When measuring data storage, existing fpga chip is unable to satisfy system design considerations, needs FPGA combining completion with external RAM The storage of Large Volume Data, therefore, data transmission need to consume a large amount of time, and the speed of data processing is slower.
Summary of the invention
In order to solve the above technical problems, an embodiment of the present invention is intended to provide a kind of fpga chip and data interactive methods.
The technical scheme of the present invention is realized as follows:
In a first aspect, providing a kind of fpga chip, comprising: dynamic random memory module, logic module;Wherein,
The dynamic random memory module includes the first substrate and the first metallic conductor for being set on first substrate;
The logic module includes the second substrate and the second metallic conductor for being set on second substrate;
First substrate of the dynamic random memory module and the second substrate attaching of the logic module are arranged, and described First metallic conductor of dynamic random memory module and the second metallic conductor conducting of the logic module;
The dynamic random memory module, for shape to be connected by first metallic conductor and second metallic conductor At access and the logic module carry out data interaction.
Further, the first substrate is connected with second substrate by hybrid bonded mode.
Further, the material of first metallic conductor and the second metallic conductor is copper.
Further, the dynamic random memory module is configured as the internal memory array of the fpga chip.
Further, the logic module includes: complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) wafer.
Further, the dynamic memory module includes: dynamic RAM (Dynamic Random Access Memory, DRAM) wafer.
Further, it states in dynamic random memory module further include: imput output circuit.
Second aspect provides a kind of data interactive method, is applied to fpga chip, the fpga chip includes dynamic random Memory module and logic module, the dynamic random memory module include the first substrate and be set on first substrate the One metallic conductor;The logic module includes the second substrate and the second metallic conductor for being set on second substrate;It is described Dynamic random memory module is arranged by the second substrate attaching of first substrate and the logic module, and the dynamic with First metallic conductor of machine memory module and the second metallic conductor conducting of the logic module;
The described method includes:
It is formed by the first metallic conductor of dynamic random memory module and the second metallic conductor of the logic module Access, controls the logic module and the dynamic random memory module carries out data interaction.
Fpga chip and data interactive method provided by the embodiment of the present invention, can be by logic module and dynamic random Memory module links together, and logic module can be by access that the first metallic conductor and the second metallic conductor are formed and dynamic State random storage module carries out data interaction;It is deposited since dynamic random memory module carries out data using the charge in grid capacitance Storage, the metal-oxide-semiconductor used is less, and the area for occupying chip is few, and integrated level is higher;Therefore, fpga chip energy provided in this embodiment The area occupied of fpga chip is enough effectively reduced;Meanwhile dynamic RAM is capable of providing a large amount of memory space, data Interaction can carry out inside fpga chip, saved the time of data transmission, improved the efficiency of data processing.
Detailed description of the invention
Fig. 1 is a kind of structure composition schematic diagram for FPGA based on SRAM memory that the embodiment of the present invention provides;
Fig. 2 is the structure composition schematic diagram for another FPGA that the embodiment of the present invention provides;
Fig. 3 is a kind of structure composition schematic diagram for COMS wafer that the embodiment of the present invention provides;
Fig. 4 is a kind of structure composition schematic diagram for DRAM wafer that the embodiment of the present invention provides;
Fig. 5 is the structure composition schematic diagram for another FPGA that the embodiment of the present invention provides.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation description.
It will be appreciated that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Base Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts it is all its His embodiment, shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of fpga chip, as shown in Figure 2: the fpga chip includes: dynamic random storage Module, logic module;Wherein,
The dynamic random memory module includes that the first substrate 11 and the first metal being set on first substrate are led Body 12;
It substrate 13 and the second metallic conductor 14 for being set on second substrate that the logic module, which includes second,;
First substrate of the dynamic random memory module and the second substrate attaching of the logic module are arranged, and described First metallic conductor of dynamic random memory module and the second metallic conductor conducting of the logic module;
The dynamic random memory module, for shape to be connected by first metallic conductor and second metallic conductor At access and the logic module carry out data interaction.
As used in this article, term " substrate " is directed to increase the material of subsequent material thereon.Substrate may include width Semiconductor material of range, such as silicon, germanium, GaAs, indium phosphide etc..Alternatively, substrate can be by such as glass, plastics or indigo plant The non-conducting material of jewel wafer is made.
In other embodiments of the invention, the dynamic random memory module can be is stored by independent dynamic random The chip that device (Dynamic Random Access Memory, DRAM) is constituted.It further include DRAM electricity on the dram chip Road;The DRAM circuit is set on the first substrate, for carrying out data storage.Wherein, first metallic conductor can pass through First substrate is worn, one end of the first metallic conductor is connect with the basic DRAM storage circuit on the first substrate.
In addition, the logic module can be independent CLB chip.The CLB chip further includes CLB circuit, the CLB Circuit is set on second substrate.Wherein, the second metallic conductor can run through second substrate, the second metallic conductor One end and the CLB circuit connection being set on the second substrate.
In other embodiments of the invention, the first substrate of the dynamic random memory module is laminated in the logic mould Second substrate of block, the first substrate and the second substrate attaching simultaneously connect;Preferably, first substrate and second substrate are logical The connection of mixing bonding pattern is crossed, so that the first substrate and the second substrate are closely linked, in addition, through in the first substrate The first metallic conductor and interconnect through the second metallic conductor in the second substrate so that dynamic random store CLB circuit connection in DRAM circuit and logic module in module;Also, the first metallic conductor and the second metallic conductor are being led The data path between connection dynamic random memory module and logic module is formed after logical.In this way, dynamic random memory module The access to be formed can be connected by the first metallic conductor and second metallic conductor and the logic module carries out data Interaction.
It should be noted that fpga chip provided in this embodiment further includes IOB, DCM, interconnection resource, embedded bottom Functional unit and embedded application specific hardware modules, wherein IOB, DCM, interconnection resource, embedded bottom functional unit and embed dedicated Similarly to the prior art, this embodiment is not repeated for the function and structure of hardware module.
Logic module and dynamic random memory module can be connected to by fpga chip provided by the embodiment of the present invention Together, and logic module can pass through the access and dynamic random memory module of the first metallic conductor and the formation of the second metallic conductor Carry out data interaction;Since dynamic random memory module carries out data storage, the metal-oxide-semiconductor used using the charge in grid capacitance Less, the area for occupying chip is few, and integrated level is higher;Therefore, fpga chip provided in this embodiment can be effectively reduced FPGA The area occupied of chip;Meanwhile dynamic RAM is capable of providing a large amount of memory space, the interaction of data can be in FPGA Chip interior carries out, and has saved the time of data transmission, has improved the efficiency of data processing.
The embodiment of the present invention provides a kind of fpga chip, and the fpga chip includes: dynamic random memory module, logic mould Block;Wherein,
The dynamic random memory module includes that the first substrate 11 and the first metal being set on first substrate are led Body 12;
It substrate 13 and the second metallic conductor 14 for being set on second substrate that the logic module, which includes second,;
First substrate of the dynamic random memory module and the second substrate attaching of the logic module are arranged, and described First metallic conductor of dynamic random memory module and the second metallic conductor conducting of the logic module;
The dynamic random memory module, for shape to be connected by first metallic conductor and second metallic conductor At access and the logic module carry out data interaction.
Specifically, the dynamic random memory module includes DRAM wafer, wherein as shown in figure 3, in the DRAM wafer Including multiple DRAM circuits.The DRAM circuit is set to the side of the first substrate.Here, each DRAM circuit is both provided with one A first metallic conductor.Wherein, the material of first metallic conductor is preferably copper.
In addition, the logic module includes COMS wafer.Wherein, as shown in figure 4, including multiple on the COMS wafer CLB circuit.The CLB circuit is set to second one side of substrate.Here, each CLB circuit is both provided with second gold medal Belong to conductor.Wherein, the material of the second metallic conductor is preferably copper.
Further, as shown in figure 5, the first substrate in DRAM wafer is connected with the second substrate of COMS wafer, the company of being formed Junction.Here, the first substrate and the second substrate are closely joined together by hybrid bonded mode.Wherein, in DRAM wafer DRAM circuit be located at the first substrate and the side far from joint face, the CLB circuit in COMS wafer is located at the second substrate and far Side from joint face.It should be noted that each DRAM circuit can correspond to a CLB circuit.
In addition, in embodiment provided by the invention, as shown in figure 5, each DRAM circuit is led with first metal One end of body connects, and first metallic conductor can run through first substrate.In addition, each CLB circuit and one One end of second conductor connects, and second metallic conductor can be through second substrate.In this way, each first metal The other end one end of DRAM circuit (i.e. not connected) of conductor can with the other end of corresponding second metallic conductor (i.e. not Connect one end of CLB circuit) it is connected with each other.
In this way, each DRAM circuit in DRAM wafer can be with a CLB circuit connection in COMS wafer;First Metallic conductor and the second metallic conductor form the data between connection dynamic random memory module and logic module after being turned Access forms the fpga chip of three-dimensional architecture.In this way, dynamic random memory module, it will be able to pass through the first metallic conductor and institute It states the second metallic conductor and the access to be formed and logic module progress data interaction is connected.
In other embodiments of the invention, the dynamic random memory module is configured as the inside of the fpga chip Storage array.That is, the data stored in DRAM circuit can be used to CLB circuit in fpga chip provided in this embodiment It is programmed, so that it is determined that the state of CLB realizes corresponding function.In addition, will can directly be counted when FPGA carries out data storage In memory space according to write-in DRAM circuit, so that the storage and exchange of data can be carried out in the inside of fpga chip.In this way, energy The time for enough saving mass data transmission, improve data-handling efficiency.It, can especially for the convolution algorithm of artificial intelligence AI A large amount of intermediate result is stored, the speed of processing data is effectively promoted.
It in another embodiment, further include imput output circuit in the dynamic random memory module, input here Output circuit can be with IOB.Specifically, the first lining in the dynamic random memory module can be set in the imput output circuit On bottom.This is because DRAM wafer and CMOS wafer are conductings, therefore imput output circuit can be integrated in the dynamic In random storage module;In addition, the imput output circuit also can be set in logic module, this embodiment is not repeated.
The COMS chip and dram chip of different manufacture crafts can be integrated in one by fpga chip provided by the invention Body.In practical applications, three configurable logic blocks in FPGA, input/output module and interconnector module parts be by Stand CMOS completes;And COMS chip fabrication technique and dram chip manufacture craft are incompatible, therefore be difficult by Dram chip and the insertion of COMS chip are integrally formed.So existing fpga chip can only use SRAM, ROM etc. with it is cmos compatible Storage unit is embedded in.And dram chip is not embedded in COMS chip by the embodiment of the present invention, but by DRAM wafer It is combined as a whole by hybrid bonded technique and CLB wafer.
It should be noted that fpga chip provided in this embodiment further includes DCM, interconnection resource, embedded bottom function Unit and embedded application specific hardware modules, wherein DCM, interconnection resource, embedded bottom functional unit and embedded application specific hardware modules Function and structure similarly to the prior art, this embodiment is not repeated.
It should be noted that in the present embodiment with the explanation of same steps in other embodiments and identical content, Ke Yican According to the description in other embodiments, details are not described herein again.
Logic module and dynamic random memory module can be connected to by fpga chip provided by the embodiment of the present invention Together, and logic module can pass through the access and dynamic random memory module of the first metallic conductor and the formation of the second metallic conductor Carry out data interaction;Since dynamic random memory module carries out data storage, the metal-oxide-semiconductor used using the charge in grid capacitance Less, the area for occupying chip is few, and integrated level is higher;Therefore, fpga chip provided in this embodiment can be effectively reduced FPGA The area occupied of chip;Meanwhile dynamic RAM is capable of providing a large amount of memory space, the interaction of data can be in FPGA Chip interior carries out, and has saved the time of data transmission, has improved the efficiency of data processing.
The embodiment of the invention also provides a kind of data interactive method, the method is applied to fpga chip, the FPGA Chip includes dynamic random memory module and logic module, and the dynamic random memory module includes the first substrate and is set to institute State the first metallic conductor on the first substrate;The logic module include the second substrate and be set on second substrate the Two metallic conductors;The dynamic random memory module is set by first substrate and the second substrate attaching of the logic module It sets, and the first metallic conductor of the dynamic random memory module and the conducting of the second metallic conductor of the logic module;
It the described method comprises the following steps:
It is formed by the first metallic conductor of dynamic random memory module and the second metallic conductor of the logic module Access, controls the logic module and the dynamic random memory module carries out data interaction.
In other embodiments of the invention, the dynamic random memory module can be is stored by independent dynamic random The chip that device (Dynamic Random Access Memory, DRAM) is constituted.It further include DRAM electricity on the dram chip Road;The DRAM circuit is set on the first substrate, for carrying out data storage.Wherein, first metallic conductor can pass through First substrate is worn, one end of the first metallic conductor is connect with the DRAM circuit on the first substrate.
In addition, the logic module can be independent configurable logic (Configurable Logic Block, CLB) Chip.The CLB chip further includes configurable logic CLB circuit, and the CLB circuit is set on second substrate.Wherein, Second metallic conductor can run through second substrate, one end of the second metallic conductor and the CLB electricity being set on the second substrate Road connection.
In other embodiments of the invention, the first substrate of the dynamic random memory module is laminated in the logic mould Second substrate of block, the first substrate and the second substrate attaching simultaneously connect;Preferably, first substrate and second substrate are logical The connection of mixing bonding pattern is crossed, so that the first substrate and the second substrate are closely linked, in addition, through in the first substrate The first metallic conductor and interconnect through the second metallic conductor in the second substrate so that dynamic random store CLB circuit connection in DRAM circuit and logic module in module;Also, the first metallic conductor and the second metallic conductor are being led The data path between connection dynamic random memory module and logic module is formed after logical.In this way, dynamic random memory module The access to be formed can be connected by the first metallic conductor and second metallic conductor and the logic module carries out data Interaction.
It should be noted that fpga chip provided in this embodiment further includes IOB, DCM, interconnection resource, embedded bottom Functional unit and embedded application specific hardware modules, wherein IOB, DCM, interconnection resource, embedded bottom functional unit and embed dedicated Similarly to the prior art, this embodiment is not repeated for the function and structure of hardware module.
Data interactive method provided by the embodiment of the present invention is applied in fpga chip, wherein in fpga chip Logic module and dynamic random memory module link together, and control logic module is led by the first metallic conductor and the second metal The access and dynamic random memory module that body is formed carry out data interaction;Since dynamic random memory module is using in grid capacitance Charge carry out data storage, the metal-oxide-semiconductor used is less, and the area for occupying chip is few, and integrated level is higher;Therefore, the present embodiment The fpga chip of offer can be effectively reduced the area occupied of fpga chip;Meanwhile dynamic RAM is capable of providing largely Memory space, the interaction of data can carry out inside fpga chip, saved the time of data transmission, improved at data The efficiency of reason.
It should be understood by those skilled in the art that, the embodiment of the present invention can provide as method, system or computer program Product.Therefore, the shape of hardware embodiment, software implementation or embodiment combining software and hardware aspects can be used in the present invention Formula.Moreover, the present invention, which can be used, can use storage in the computer that one or more wherein includes computer usable program code The form for the computer program product implemented on medium (including but not limited to magnetic disk storage and optical memory etc.).
The present invention be referring to according to the method for the embodiment of the present invention, the process of equipment (system) and computer program product Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates, Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one The step of function of being specified in a box or multiple boxes.
The foregoing is only a preferred embodiment of the present invention, is not intended to limit the scope of the present invention.

Claims (8)

1. a kind of field programmable gate array fpga chip, comprising: dynamic random memory module, logic module;Wherein,
The dynamic random memory module includes the first substrate and the first metallic conductor for being set on first substrate;
The logic module includes the second substrate and the second metallic conductor for being set on second substrate;
First substrate of the dynamic random memory module and the second substrate attaching of the logic module are arranged, and the dynamic First metallic conductor of random storage module and the second metallic conductor conducting of the logic module;
The dynamic random memory module to be formed for being connected by first metallic conductor and second metallic conductor Access and the logic module carry out data interaction.
2. fpga chip according to claim 1, which is characterized in that first substrate and second substrate are by mixing Close bonding pattern connection.
3. fpga chip according to claim 1, which is characterized in that first metallic conductor and the second metallic conductor Material is copper.
4. fpga chip according to claim 1, which is characterized in that the dynamic random memory module is configured as described The internal memory array of fpga chip.
5. fpga chip according to claim 1, which is characterized in that the logic module includes: complementary metal oxide Semiconductor CMOS wafer.
6. fpga chip according to claim 1, which is characterized in that the dynamic memory module includes: that dynamic random is deposited Reservoir DRAM wafer.
7. fpga chip according to claim 1, which is characterized in that in the dynamic random memory module further include: defeated Enter output circuit.
8. a kind of data interactive method is applied to fpga chip, the fpga chip includes dynamic random memory module and logic Module, the dynamic random memory module include the first substrate and the first metallic conductor for being set on first substrate;Institute State the second metallic conductor that logic module includes the second substrate He is set on second substrate;The dynamic random stores mould Block is arranged by the second substrate attaching of first substrate and the logic module, and the of the dynamic random memory module One metallic conductor and the conducting of the second metallic conductor of the logic module;
The described method includes:
The access formed by the first metallic conductor of dynamic random memory module and the second metallic conductor of the logic module, It controls the logic module and the dynamic random memory module carries out data interaction.
CN201910351369.XA 2019-04-28 2019-04-28 On-site programmable logic gate array chip and data interaction method Active CN110162494B (en)

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CN117807940A (en) * 2023-12-29 2024-04-02 苏州异格技术有限公司 Chip layout design method and device, computer equipment and chip

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CN113626372A (en) * 2021-09-02 2021-11-09 西安紫光国芯半导体有限公司 Integrated chip integrating storage and calculation
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