JPH10111864A - Semi-conductor integrated circuit device and its producing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the develope period of a semi-conductor integrated circuit device, to make circuit performance high and to reduce a cost. SOLUTION: Pads 51a, 51b and 52a which are electrically connected to respective integrated circuits are respectively formed in a RAM substrate 11A, an MPU(microprocessor unit substrate 11B as an LSI core, and an FPGA(field programable gate array) substrate 12 specifying the circuit after packaging. Through the use of technique for adhearing semi-conductor chips, the main surface 11a of the RAM substrate 11A, the main surface 11b of the MPU substrate 11B and the main surface 12a of the FPGA substrate 12 respectively pinch balls 14 consisting of solderirng or steel, etc., in the respective pads 51a, 51b and 52a and facing-connected so that RAM, MPU and FPGA are respectively connected electrically.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an application specific semiconductor integrated circuit (= ASIC) device and a method of manufacturing the same, and more particularly, to a specific application semiconductor integrated circuit device manufactured in a short period of time and at low cost and its manufacture. About the method.

[0002]

2. Description of the Related Art As a method of realizing a semiconductor substrate integrated circuit having a high function, six manufacturing methods having the following advantages or disadvantages have been proposed.

(1) Manufacturing method using a microprocessor (MPU) This is a method for manufacturing a circuit for a specific application by using a high-performance microprocessor to write a program in its memory unit.

The advantages are that a high-speed and low-power-consumption product can be provided, and that specifications can be flexibly dealt with by rewriting a program from an external terminal.

[0005] On the other hand, a disadvantage is that since the functions are mounted in a circuit assuming all functions, unnecessary circuits are included in a specific application, and the manufacturing cost is increased. If a dedicated microprocessor is newly developed to reduce the manufacturing cost, the development cost and the development period become enormous.

(2) Digital signal processor (DS)
Manufacturing Method Using P) A DSP is an LSI in which circuits required for digital signal processing are mounted at a high density, and is a method of manufacturing a circuit for a specific application by writing a program in a memory portion thereof.

Advantages are that a high-speed, low-power and low-cost product can be provided, and that a program can be rewritten from an external terminal to flexibly cope with a change in use.

On the other hand, the disadvantage is that the DSP is an L
Because of the SI, the circuit lacks flexibility. If a dedicated DSP with additional functions is newly developed, the period and development costs become enormous.

(3) Manufacturing Method Using Field Programmable Gate Array (FPGA) In an FPGA, transistors and wiring layers for connecting all the transistors as much as possible are formed on a substrate.
This is a method of manufacturing a circuit for a specific use by applying a high voltage from an external terminal to cut off unnecessary wiring or connecting necessary wiring after a designer determines a logical configuration.

An advantage is that a desired circuit can be flexibly provided because a transistor and a wiring connecting the transistors can be variously combined.
Since the time required to apply the voltage to the wiring layer in the FPGA is completed in a matter of seconds or minutes, it is possible to provide the user with a semiconductor circuit almost at the same time as the specification of the circuit is completed. Because it is not limited, the development cost is low.

On the other hand, a disadvantage is that it is necessary to manufacture in advance a transistor and a wiring layer for connecting all of the transistors as much as possible. That is not possible. Therefore, the cost of the LSI becomes enormous because it includes useless circuits. Further, since the transistor size and the wiring shape cannot be set optimally, circuit characteristics are inferior to those of a normal custom LSI.

For example, if the FPGA circuit has a logical scale of 1
4 of K gate, 2K gate, 4K gate or 8K gate
FIG. 10 is a graph showing the correlation between the circuit scale and the manufacturing cost in the case where the configuration is made up of different types. In FIG. 10, C1 is used for a circuit having a logic scale of 1K gates or less.
Cost is required, and similarly from 1K gate or more to 2K
The circuit below the gate requires C2, the circuit from 2K gates to 4K gates requires C3, and the circuit from 4K gates to 8K gates requires C4 cost.
For example, if the specific application circuit is a 5K gate, FP
According to the conventional method, 8
It is necessary to use a K-gate FPGA, and a 3K-gate redundant area is generated on a large scale.
Redundant costs.

After defining the circuit according to the user's request,
A programming device is connected to an external terminal of the package for the determined circuit to perform programming.

FIG. 11 shows a standard development period D0 required to develop an FPGA.

As shown in FIG. 11, a function design step D1 for selecting and deciding a component of a function based on a specification is performed by 6 steps.
It takes about four months for the logic design process D2 for embodying the functional design level at the gate level configuration of NAND or NOR, and about several days for the specific circuitization process D6 for specifying the circuit at the request of the user. However, since the design periods overlap, the development period D0 is about eight months.

(4) Gate Array (GA) In GA, up to a transistor is built on a substrate.
This is a method of manufacturing an application-specific integrated circuit by manufacturing a wiring layer on a substrate after a designer has determined a logical configuration.

The advantages are that the transistor can be developed not only for a specific application but in large quantities, so that the development cost is low.
Various combinations of wiring enable flexible provision of high-performance circuits. Furthermore, the time required to manufacture only the wiring layers is completed within a few days. A circuit can be provided.

On the other hand, the disadvantage is that it is necessary to manufacture the transistor portion in advance, and therefore, it is not possible to provide a gate array of an optimum size after a desired circuit size is determined. Therefore, since it includes useless circuits, LSI
Costs are huge. Further, since the transistor size cannot be set to an optimum size, circuit characteristics are slightly inferior to those of a normal custom LSI.

After determining the circuit according to the user's request,
A wiring layout designing step D3 is performed, and an LSI is completed through a wiring mask manufacturing and wiring processing step D4 and a packaging step D5. FIG. 12 shows the time required for the development of the GA.

The GA circuit has a logical scale of 1K gates, 2
In the case of four types of K gates, 4K gates, and 8K gates, the redundant cost Cd for a required circuit size of 5K gates is the same as that of the FPGA described with reference to FIG.

(5) Standard Cell After the designer has determined the logical configuration, a transistor and a wiring layer are manufactured to manufacture an application-specific integrated circuit.

An advantage is that a transistor and a wiring can be variously combined, so that a high-performance circuit can be flexibly provided.

On the other hand, the disadvantages are that since the manufacture of the transistor section and the wiring section is performed after the completion of the logical design according to each LSI, the development cost becomes high and the development time after the process processing is several months. Is required.

After the circuit is determined, the layout design process D
3 is performed, and an LSI is completed through a mask manufacturing and processing step D4 and a packaging step D5. FIG. 13 shows the lapse of time required for the development of the standard cell.

(6) Embedded Array As a method of making use of the advantages of the standard cell and the gate array, a circuit portion determined during design is manufactured as a standard cell and a logic undefined portion is manufactured as a gate array up to a transistor portion in advance. In a few weeks after the design is completed, only the wiring layer is manufactured,
This is a method for producing I.

The advantages are that the LSI can be provided in a short time after the completion of the design, and that part of the circuit can be provided with high density and high performance by manufacturing a part of the circuit as a standard cell.

On the other hand, disadvantages are that a useless circuit is generated in the gate array portion, and that the development cost is as high as the standard cell.

The process processing step D4 is performed in the middle of the function design step D1 and the logic design step D2, and after the circuit is determined, the wiring layout design step D3 is performed. The subsequent wiring process processing step D4 and the packaging step D5
After that, the LSI is completed. FIG. 14 shows a time course required for the development of the embedded array.

In addition to the above-described design technique for developing a high-density and high-performance LSI by using only the LSI, the LS
Numerous prior arts have been proposed for realizing high-density and high-performance LSIs by using new mounting methods for I semiconductor integrated circuits. In particular, a semiconductor integrated circuit manufacturing technology called a multi-chip module (MCM) has features that are superior to a conventional printed circuit board in terms of small packaging, weight reduction of equipment, and improvement of circuit characteristics. Improving mounting density.

A brief description will now be given of the two mainstream realization methods.

(1) Deposit (MCM-D) Method One thin film substrate made of metal, semiconductor or ceramic is continuously deposited, and a semiconductor layer is formed on each thin film substrate.
Assemble the SI chip.

(2) Stacking (MCM-L) Method A plurality of thin film substrates made of metal, semiconductor or ceramic are stacked and deposited, and finally a semiconductor LSI chip is assembled on a multilayer thin film substrate.

However, these MCM techniques have the following problems.

I) The manufacturing cost of the substrate used for the MCM is high.

Ii) Due to the increase in the scale of the circuit, the manufacturing period of the substrate of the MCM, that is, the manufacturing period of the LSI for a specific application is lengthened.

In recent years, in order to further reduce the cost, fine processing technology for mounting on a printed circuit board has been advanced, and as a mounting method which has further developed the MCM-L, ball-shaped solder or gold is formed on pads of a plurality of LSI chips. A COC (chip-on-chip) method has been proposed, which is a mounting method of arranging and making surface contact. This is because the above-mentioned thin film substrate for MCM is L
Since an SI chip is used, it helps to reduce costs.

[0037]

However, the conventional COC method has the following disadvantages. (1) The mounting cost is high, and no remarkable advantage is recognized as compared with the cost when it is realized by one chip.

(2) It cannot contribute to shortening the LSI development period.

There are the following problems.

An object of the present invention is to solve the conventional problems at once, to shorten the development period, and to improve the performance of a semiconductor integrated circuit.

[0041]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a first integrated circuit formed on a main surface of a first semiconductor substrate; A second integrated circuit, which is formed on the main surface of the semiconductor substrate, has a redundant wiring, and a circuit is specified by connecting or disconnecting the redundant wiring by an electric signal input from an external terminal; A first pad formed on a main surface of the first semiconductor substrate and electrically connected to the first integrated circuit; and a first pad formed on a main surface of the second semiconductor substrate. A second pad electrically connected to the second integrated circuit, wherein a main surface of the first semiconductor substrate and a main surface of the second semiconductor substrate face each other, and By connecting a first pad and the second pad, the first pad is connected to the first pad. Wherein the integrated circuit and the second integrated circuit in which a configuration that is electrically connected.

According to the structure of the first aspect, the first semiconductor substrate and the second semiconductor substrate are opposed to each other on the principal surfaces of the substrates on which the integrated circuits are formed, and are electrically connected via pads. Therefore, a high-density mounting mode is achieved.

Further, since the second integrated circuit is configured so that the circuit is specified by connecting or disconnecting the redundant wiring by an electric signal input from an external terminal, the second integrated circuit is developed after the logic design process. The period will be very short.

According to a second aspect of the present invention, in the first aspect, the second integrated circuit has a configuration in which a circuit is specified by an electric signal input from an external terminal.

According to a third aspect of the present invention, in addition to the first or second aspect, a configuration in which the second integrated circuit is formed of a field programmable gate array is added.

According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a first integrated circuit formed on a main surface of a first semiconductor substrate; and a main surface of a second semiconductor substrate. A second integrated circuit, which is formed on the first semiconductor substrate and has a pre-formed active element and whose circuit is specified by forming a wiring layer; and a second integrated circuit formed on the main surface of the first semiconductor substrate. A first pad electrically connected to the first integrated circuit; and a first pad formed on a main surface of the second semiconductor substrate and electrically connected to the second integrated circuit. And a main surface of the first semiconductor substrate and a main surface of the second semiconductor substrate are opposed to each other, and the first pad and the second pad are connected to each other. Thereby, the first integrated circuit and the second integrated circuit are electrically connected. It is an Configurations.

According to the structure of the fourth aspect, the first semiconductor substrate and the second semiconductor substrate have their main surfaces on which the integrated circuits are formed facing each other, and are electrically connected via pads. Therefore, a high-density mounting mode is achieved.

Further, since the second integrated circuit is configured so that the circuit is specified by forming the wiring layer, the development period after the logic design process is shortened.

According to a fifth aspect of the present invention, in addition to the configuration of the fourth aspect, a configuration in which the second integrated circuit comprises a gate array is added.

According to a sixth aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a first integrated circuit formed on a main surface of a first semiconductor substrate; and a main surface of a second semiconductor substrate. A second integrated circuit formed of a versatile cell and a main surface of the first semiconductor substrate and electrically connected to the first integrated circuit. And a second pad formed on a main surface of the second semiconductor substrate and electrically connected to the second integrated circuit. When the main surface of the substrate and the main surface of the second semiconductor substrate face each other and the first pad and the second pad are connected, the first integrated circuit and the second integrated circuit are connected to each other. The circuit is configured to be electrically connected.

According to the sixth aspect of the present invention, the first semiconductor substrate and the second semiconductor substrate have their main surfaces on which the integrated circuits are formed facing each other and are electrically connected via pads. Therefore, a high-density mounting mode is achieved.

Further, since the second integrated circuit is constituted by a circuit composed of cells having general versatility, the second integrated circuit can be designed with high performance and flexibility.

According to a seventh aspect of the present invention, in addition to the configuration of the sixth aspect, a configuration in which the second integrated circuit comprises a standard cell is added.

According to another aspect of the present invention, a semiconductor integrated circuit device includes a first integrated circuit formed on a main surface of a first semiconductor substrate and a main surface of a second semiconductor substrate. A second rewritable memory formed on
And a first pad formed on the main surface of the first semiconductor substrate and electrically connected to the first integrated circuit; and a main surface of the second semiconductor substrate. A second pad formed on the first semiconductor substrate and electrically connected to the second integrated circuit, wherein a main surface of the first semiconductor substrate and a main surface of the second semiconductor substrate are connected to each other. The first integrated circuit and the second integrated circuit are electrically connected to each other by connecting the first pad and the second pad so as to face each other. .

According to the eighth aspect of the present invention, the first semiconductor substrate and the second semiconductor substrate are electrically connected via pads, with the main surfaces of the substrates on which the integrated circuits are formed facing each other. Therefore, a high-density mounting mode is achieved.

Further, since the second integrated circuit is composed of a rewritable memory, the development period after the logic design process becomes extremely short as in the case of the FPGA.

According to a ninth aspect of the present invention, the first integrated circuit has a configuration in which the first integrated circuit is formed of a field programmable gate array.

According to the tenth and ninth aspects of the present invention, the field programmable gate array has a configuration in which a logic circuit is specified by an electric signal input from an external terminal.

According to an eleventh aspect of the present invention, the first integrated circuit has a configuration in which the first integrated circuit comprises a gate array.

According to a twelfth aspect of the present invention, in addition to the first to eighth aspects, a configuration in which the first integrated circuit comprises a standard cell is added.

According to a thirteenth aspect of the present invention, in addition to the first to eighth aspects, a configuration in which the first integrated circuit comprises a rewritable memory is added.

According to a fourteenth aspect of the present invention, in addition to the configuration of the first to eighth aspects, a configuration is provided in which the first integrated circuit is an integrated circuit that is standard-produced and includes, for example, a memory, an MPU or a DSP. It is.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device, comprising: forming a first integrated circuit having a determined function and circuit scale on a main surface of a first semiconductor substrate. A first integrated circuit forming step, a second integrated circuit determining step of determining a circuit scale of a second integrated circuit from a circuit scale of the first integrated circuit, and a step of forming a second integrated circuit on a main surface of the second semiconductor substrate. A second integrated circuit whose circuit size is determined and which has a redundant wiring and whose circuit is specified by connecting or disconnecting the redundant wiring by an electric signal input from an external terminal; Forming a first pad electrically connected to the first integrated circuit on a main surface of the first semiconductor substrate, and forming a first pad on the main surface of the first semiconductor substrate; Electrically connected to the second integrated circuit A pad forming step of forming a second pad, wherein the main surface of the first semiconductor substrate and the main surface of the second semiconductor substrate face each other, and the first pad is connected to the second pad. The first semiconductor substrate and the second semiconductor substrate are packaged in a state where external terminals electrically connected to the first integrated circuit or the second integrated circuit protrude outside the package. And a packaging step for packaging.

According to the fifteenth aspect, pads electrically connected to each integrated circuit are formed on each of the main surfaces of the first semiconductor substrate and the second semiconductor substrate, respectively. By connecting the pads with the main surfaces of the two semiconductor substrates facing each other and enclosing them in one package, a high-density mounting mode is achieved.

The circuit scale of the second integrated circuit is determined by the circuit scale of the first integrated circuit, and the redundant wiring is connected or disconnected by an electric signal input from an external terminal. Is specified, the development period after the logic design process becomes extremely short.

According to a sixteenth aspect of the present invention, in the configuration of the fifteenth aspect, after the packaging step, a function determining step for determining a logical function of the second integrated circuit, and an electric signal from an external terminal of the package is provided. The second integrated circuit is specified by inputting and connecting or disconnecting the redundant wiring provided in the second integrated circuit so that the logical function of the second integrated circuit is realized. And a circuit specifying step.

The invention of claim 17 is the invention of claim 15 or 16
The second integrated circuit adds a configuration comprising a field programmable gate array to the above configuration.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device, comprising: forming a first integrated circuit having a determined function and circuit scale on a main surface of a first semiconductor substrate. Forming a first integrated circuit, and determining a circuit size of a second integrated circuit from a circuit size of the first integrated circuit, and determining a logical function of the second integrated circuit.
Forming the wiring layer on the main surface of the second semiconductor substrate so that the determined logic function of the second integrated circuit is realized. Forming a first pad electrically connected to the first integrated circuit on the main surface of the first semiconductor substrate, and forming the second pad on the main surface of the second semiconductor substrate. A pad forming step of forming a second pad electrically connected to the integrated circuit, wherein a main surface of the first semiconductor substrate and a main surface of the second semiconductor substrate face each other; The first semiconductor substrate in a state where a pad is connected to the second pad and an external terminal electrically connected to the first integrated circuit or the second integrated circuit projects outside the package; And a packaging step of packaging the second semiconductor substrate and It is an arrangement which comprises comprises.

According to the eighteenth aspect, pads electrically connected to each integrated circuit are formed on each of the main surfaces of the first semiconductor substrate and the second semiconductor substrate, respectively. By connecting the pads with the main surfaces of the two semiconductor substrates facing each other and enclosing them in one package, a high-density mounting mode is achieved.

Further, the circuit scale of the second integrated circuit is determined by the circuit scale of the first integrated circuit, and by forming a wiring layer on the second integrated circuit of the second semiconductor substrate. Is specified, the development period after the logic design process is shortened.

A nineteenth aspect of the present invention is that the second integrated circuit has a configuration of a gate array in addition to the configuration of the eighteenth aspect.

According to a twentieth aspect of the present invention, in the configuration of the fifteenth to nineteenth aspects, the first integrated circuit is provided with a redundant wiring,
A configuration is added that includes a field programmable gate array in which a circuit is specified by connecting or disconnecting the redundant wiring by an electric signal input from an external terminal.

According to a twenty-first aspect of the present invention, in the configuration of the twentieth aspect, after the packaging step, a function determining step of determining a logical function of the first integrated circuit, and an electric signal from an external terminal of the package is provided. A circuit for specifying the first integrated circuit by connecting or disconnecting a redundant line provided in the first integrated circuit so that the logic function of the first integrated circuit is realized by inputting A configuration further including a specific step is added.

The invention of claim 22 is the one in which the first integrated circuit is added to a structure of a gate array to the structure of claims 15 to 19.

In a twenty-third aspect of the present invention, the configuration of the first integrated circuit is added to a configuration of a fifteenth to nineteenth aspect, wherein the first integrated circuit comprises a standard cell.

According to a twenty-fourth aspect of the present invention, a configuration in which the first integrated circuit comprises a rewritable memory is added to the configuration of the fifteenth to nineteenth aspects.

According to a twenty-fifth aspect of the present invention, in addition to the configuration of the fifteenth to nineteenth aspects, the first integrated circuit is added to a configuration in which the first integrated circuit is, for example, an integrated circuit including a memory, an MPU, or a DSP. It is.

[0078]

DETAILED DESCRIPTION OF THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention, wherein FIG.
(B) is sectional drawing of the II line in (a). FIG.
In (a), 11A is a RAM substrate as a first semiconductor substrate on which a random access memory produced as standard as a first integrated circuit is formed, and 11B is a standard substrate as a first integrated circuit. MPU substrate 11B as a first semiconductor substrate on which a formed microprocessor is formed, and 12 is a field programmable gate array as a second integrated circuit, which can be programmed by an electric signal input from an external terminal. Is an FPGA substrate as a second semiconductor substrate on which is formed. Also, 1
3 is a RAM board 11A, MPU board 11B and FPGA
This is a package for enclosing the substrate 12.

As shown in FIG. 1B, the RAM substrate 11
A RAM substrate pad 51a as a first pad electrically connected to the RAM circuit is formed on the main surface 11a of A, and the MPU substrate is formed on the main surface 11b of the MPU substrate 11B.
MPU as first pad electrically connected to circuit
A board pad 51b is formed, and on the main surface 12a of the FPGA board 12, an FPGA board pad 52a as a second pad electrically connected to the FPGA circuit is formed. The main surfaces 11a and 11b of the RAM substrate 11A and the MPU substrate 11B and the main surface 12a of the FPGA substrate 12 are bonded to the pads 51a, 51b and 52a by using a semiconductor chip bonding technique. Or bumps) 14 to face each other and to be connected, so that the RAM, the MPU and the FPG
Each circuit of A is electrically connected.

Further, an external terminal 15 having one end connected to the FPGA circuit on the FPGA substrate 12 and the other end protruding outside the package 13 is provided.

The pads 51a, 51b, 52a
Are the RAM board 11A, the MPU board 11B and the FPGA
It is assumed that the design rule, the structure, and the pitch are previously unified on the substrate 12.

The semiconductor integrated circuit device according to the present embodiment
High-performance, high-density RAM board 11A and MPU board 11B produced as standard, and mass-producible FPGA board 12
And the FPGA board 12 includes:
Redundant wiring is provided in advance on the wiring layer, and external terminals 15 are provided.
Since the desired circuit is specified by connecting or disconnecting the redundant wiring by an electric signal input from the circuit, the operation of specifying the circuit after completing the logic circuit can be performed in a short time using a program device. Can be terminated. Thereby, a low-cost, high-performance ASIC can be realized in a short period of time.

The FPGA as the second semiconductor substrate
The substrate 12 may be an EPROM which is a rewritable memory.

Further, a cell-based standard cell may be used for the second integrated circuit on the second semiconductor substrate. In this case, the performance of the second integrated circuit can be improved.

Hereinafter, a method for manufacturing a semiconductor integrated circuit device according to the first embodiment of the present invention will be described with reference to the drawings.

First, a conventional development process and its development period will be described. As shown in FIG. 13, for example, a cell-based ASI
Taking C as an example, in the development process of this semiconductor integrated circuit, a function design D1 for selecting and determining a function component based on a user's specification and a function design level of NAND or NOR are set.
Logic design D2, which is embodied as a gate-level configuration, layout design step D3 for deciding arrangement and wiring of standard cells and the like using a cell library, manufacturing of elements according to the design on a substrate made of a semiconductor or the like, and wiring It comprises a process step D4 for forming a layer to form a predetermined circuit, and a packaging step D5 for packaging a substrate on which the predetermined circuit is formed.

Each process is carried out in parallel by a plurality of personnel because of the need to perform development in a short time. Therefore, as shown in FIG. 13, for example, from the middle of the function design process D1, it is possible to proceed in parallel with the logic design process D2 for the part where the function is determined. Logical design process D2
Is completed, the final step of the layout design step D3 is performed. Now, as typical development periods, the function design process D1 is 6 months, the logic design process D2 is 4 months, the layout design process D3 is 2 months, and the process processing process D4 is 2 months. Assuming that it is possible to proceed to the next step almost at the midpoint of each development stage, as shown in FIG. 8, it is understood that the development period D0 requires 10 months.
If this is performed by the embedded array method, as shown in FIG. 14, the process after the wiring layer forming process in the process process process D4 is 0.5 month, and the development period D0 is 8.5 months. , 1.
It can be seen that development can be performed in a period of less than 5 months.

Hereinafter, a method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention will be described.

FIG. 2 is a flowchart showing a method of manufacturing a semiconductor integrated circuit device according to the first embodiment of the present invention.
Is a time chart showing a development period of the present apparatus. First, as shown in FIG. 2, in a ready-manufactured circuit determining step ST1 as a first integrated circuit forming step, a ready MPU and a ready RAM as the first integrated circuit are determined.

Next, in the remaining circuit scale determining step ST2 as a second integrated circuit forming step, the MPU determined
Then, the circuit size required for the FPGA is determined from the circuit size of the RAM.

Next, in the pad forming step, the main surface of the semiconductor substrate (MPU substrate) on which the MPU is formed and the RAM
A first pad electrically connected to each integrated circuit is formed on a main surface of a semiconductor substrate (RAM substrate) on which is formed, and a semiconductor substrate (FP) on which an FPGA is formed.
A second pad electrically connected to the FPGA circuit is formed on the main surface of the (GA substrate). Thereafter, in a device manufacturing process ST3 including a packaging process, the main surfaces of the MPU substrate and the RAM substrate and the main surface of the FPGA substrate face each other, the first pad and the second pad are connected, and the FPGA circuit and the electrical circuit are electrically connected. The MPU substrate, the RAM substrate, and the FPGA substrate are packaged in a state where the external terminals that are physically connected protrude outside the package.

At this stage, the semiconductor integrated circuit device is an FPGA.
The integrated circuit of the substrate has not been determined for a specific application. In the next circuit determination step ST4, after the logic function according to the user's request has been determined, as shown in the specific circuitization step D6 in FIG. By inputting an electric signal for a program from an external terminal, specific use of the device can be performed in a few hours.

Therefore, since each period of the layout design process and the process processing process can be omitted, as shown in FIG. 3, the development period D0 is about 8.0 months, which is two months as compared with the conventional method. In addition, the time can be shortened by about 0.5 months as compared with the embedded array method.

Further, a mass-produced MP which is a circuit already manufactured is used.
Since an LSI composed of a U or a RAM is used for a part of an integrated circuit, it can be manufactured at a lower cost than the embedded array system.

This can be checked as follows. FIG. 4 shows the relationship between the circuit scale to be developed and the manufacturing cost. The cost C per semiconductor chip is represented by C = K / N + C0, where N is the number of products manufactured, K is the design and development cost, and C0 is the process processing cost per chip. Therefore, assuming that the cost per chip required for COC mounting is B, the integrated circuit device according to the present embodiment can be expressed as C = K / N + C0 + B.

Thus, if the number of manufactured integrated circuit devices according to the present embodiment is the same as that of the embedded array type integrated circuit device, the integrated circuit device according to the present embodiment can be embedded in the embedded array type. The cost is higher than the integrated circuit device.

However, as shown in FIG. 4, the MPU or RAM as the first integrated circuit already manufactured to be incorporated in the integrated circuit device according to the present embodiment integrates the number N of products manufactured by the embedded array method. Since the cost of the integrated circuit device of the embedded array system is C2, and the cost of the integrated circuit device according to the present embodiment is C1, RAM
Has the cost advantage of Cd, which is the difference between C2 and C1, so that the integrated circuit device according to the present embodiment is inexpensive.

Note that the effect of the present invention does not change even if any of the application-specific LSI cores such as the EPROM, the ROM, and the DSP besides the MPU or the RAM is used as the first integrated circuit.

The same effect can be obtained by using an FPGA, a GA, or a standard cell for the first integrated circuit.

(Second Embodiment) A semiconductor integrated circuit device according to a second embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 shows a configuration of a semiconductor integrated circuit device according to a second embodiment of the present invention, wherein FIG.
(B) is a sectional view taken along line II-II in (a). FIG.
In (a), reference numeral 21A denotes a RAM substrate as a first semiconductor substrate on which a random access memory manufactured as standard as a first integrated circuit is formed, and 21B is manufactured as standard as a first integrated circuit. MPU substrate 21B as a first semiconductor substrate on which a microprocessor is formed, and 22 is a gate array that can obtain a desired circuit by forming a wiring layer as a second integrated circuit. GA as the formed second semiconductor substrate
It is a substrate. A package 23 encloses the RAM board 21A, the MPU board 21B, and the GA board 22.

As shown in FIG. 5B, the RAM substrate 21
A RAM substrate pad 61a as a first pad electrically connected to the RAM circuit is formed on the main surface 21a of A, and the MPU is formed on the main surface 21b of the MPU substrate 21B.
MPU as first pad electrically connected to circuit
The substrate pad 61b is formed, and the main surface 2 of the GA substrate 22 is formed.
On the 2a, a GA board pad 62a is formed as a second pad electrically connected to the GA circuit.
The main surfaces 21a of the RAM substrate 21A and the MPU substrate 21B,
21b and the main surface 22a of the GA substrate 22 are connected to each pad 61a, 61b,
The circuits of RAM, MPU and GA are electrically connected to and connected to the ball 62a (or bump) 24 made of solder, gold, or the like, respectively.

Further, one end of the GA substrate 22
An external terminal 25 connected to the circuit and having the other end protruding outside the package 23 is provided.

The pads 61a, 61b, 62a
Is formed on the RAM board 21A, the MPU board 21B, and the GA board 22 in advance by unifying design rules, structures, and pitches.

The method of manufacturing a semiconductor integrated circuit device according to the present embodiment includes a step of determining a manufactured MPU and a manufactured RAM as a first integrated circuit as a first integrated circuit forming step as a first integrated circuit forming step; From the determined MPU and the RAM circuit size, a circuit size required for the GA integrated circuit is determined, and a second integrated circuit defining step of performing a logic design is performed. A second semiconductor substrate wiring layer forming step of forming a wiring layer according to a user's request on a GA substrate) and a semiconductor substrate (RAM) on which a main surface of a semiconductor substrate on which an MPU is formed (MPU substrate) and a RAM are formed A first pad electrically connected to each integrated circuit is formed on the main surface of the substrate, and a second pad electrically connected to the GA circuit is formed on the main surface of the GA substrate. And the pad forming step, a major surface and GA main surface of the substrate of the MPU board and RAM board faces that,
Packaging in which the MPU substrate, the RAM substrate, and the GA substrate are packaged in a state in which the first pad and the second pad are connected, and external terminals electrically connected to the GA circuit protrude outside the package. And a device manufacturing process including a process.

The semiconductor integrated circuit device according to the present embodiment
Since it is composed of the high-performance, high-density RAM board 21A and the MPU board 21B produced as standard and the GA board 22 which can be mass-produced, it can be realized at low cost. Also,
Since the GA is used, the process for specifying the application for the user performed after the completion of the logic circuit can be performed in a short time only by the process for forming the wiring layer.

Note that the effect of the present invention does not change even if any of the special purpose LSI cores such as the EPROM, the ROM, and the DSP besides the MPU or the RAM is used as the first integrated circuit.

The same effect can be obtained by using an FPGA, GA, or standard cell for the first integrated circuit.

(Third Embodiment) Hereinafter, a semiconductor integrated circuit device according to a third embodiment of the present invention will be described with reference to the drawings.

FIG. 6 shows a configuration of a semiconductor integrated circuit device according to the third embodiment of the present invention, wherein FIG.
(B) is a sectional view taken along line III-III in (a). In FIG. 6A, reference numeral 31A denotes an FPGA substrate as a first semiconductor substrate on which a standard-produced field programmable gate array as a first integrated circuit is formed, and 31B denotes a first integrated circuit. An MPU substrate 31B as a first semiconductor substrate on which a microprocessor manufactured according to the standard is formed, 32 is a standard cell type integrated circuit as a second integrated circuit,
A standard cell substrate as a second semiconductor substrate. 33 denotes an FPGA substrate 31A, an MPU substrate 31
B and a package for enclosing the standard cell substrate 32.

As shown in FIG. 6B, the FPGA substrate 3
FPGA substrate pad 71 as a first pad electrically connected to the FPGA circuit on main surface 31a of 1A.
a is formed, and on the main surface 31b of the MPU substrate 31B, an MPU substrate pad 71b as a first pad electrically connected to the MPU circuit is formed, and on the main surface 32a of the standard cell substrate 32. Is formed with a standard cell substrate pad 72a as a second pad electrically connected to the standard cell circuit. FPGA
Main surfaces 31a and 31b of the substrate 31A and the MPU substrate 31B
The main surface 32a of the standard cell substrate 32 is connected to the pads 71a, 7a by using a bonding technique of a semiconductor chip.
The circuits of the FPGA, the MPU, and the standard cell are electrically connected to each other by connecting and connecting the balls (or bumps) 34 made of solder, gold, or the like, respectively, to the 1b and 72a. .

Further, one end of the standard cell substrate 32
And an external terminal 35 whose other end protrudes outside the package 33 is provided.

The pads 71a, 71b, 72a
Is formed on the FPGA substrate 31A, the MPU substrate 31B, and the standard cell substrate 32 in advance by unifying design rules, structures, and pitches.

Hereinafter, a method for manufacturing a semiconductor integrated circuit device according to the third embodiment of the present invention will be described.

FIG. 7A is a flowchart showing a method of manufacturing a semiconductor integrated circuit device according to the third embodiment of the present invention, and FIG. 7B is a time chart showing a development period of the device.

First, as shown in FIG. 7A, in an already-manufactured circuit determining step ST31 as a first integrated circuit forming step, an off-the-shelf FPGA and an off-the-shelf MPU as the first integrated circuit are determined.

Next, in the manufacturing circuit determination step ST32, after determining the circuit scale of the entire device from the determined MPU, the logic function of the standard cell portion as the second integrated circuit is determined.

Next, in the remaining circuit scale determining step ST33A, the remaining FPGA is determined based on the determined overall circuit scale.
In addition to determining the circuit scale of the part, in the second integrated circuit manufacturing process ST33B, layout design and process processing are performed to complete a second integrated circuit composed of standard cells on a second semiconductor substrate.

Next, in a device manufacturing process ST34 including a pad forming process and a packaging process, the main surface of the semiconductor substrate (FPGA substrate) on which the FPGA is formed and the MP
A first pad electrically connected to each integrated circuit is formed on a main surface of a semiconductor substrate (MPU substrate) on which U is formed, and a first pad of a semiconductor substrate (standard cell substrate) on which standard cells are formed. A second pad electrically connected to the standard cell circuit is formed on the main surface. Next, the main surfaces of the FPGA substrate and the MPU substrate face the main surface of the standard cell substrate, and the first pad and the second pad are connected to each other.
The FPGA substrate, the MPU substrate, and the standard cell substrate are packaged with the external terminals electrically connected to the standard cell circuit protruding outside the package.

In the next circuit determination step ST35, after the logic function according to the user's request has been determined, as shown in the specific circuitization step D6 of FIG. By inputting an electric signal for a program from an external terminal by using the device, a specific use of the device can be performed in a few hours.

Therefore, the FPGA board can omit the respective periods of the layout design process and the process processing process. As shown in FIG. 7B, the development period D0 is about 8.0 months. The method can be shortened to about two months as compared with the method of the above, and about 0.5 months as compared with the embedded array method.

The FP mass-produced as an already manufactured circuit
Since the GA or MPU is used, it can be manufactured at a lower cost as compared with the embedded array method.

Note that the first integrated circuit is an FPGA
Or MPU, EPROM, RAM, ROM or D
The effect of the present invention does not change even if any of the application-specific LSI cores such as SP is used.

The first integrated circuit has an EPROM, GA
Alternatively, a similar effect can be obtained by using a standard cell.

(Fourth Embodiment) Hereinafter, a semiconductor integrated circuit device according to a fourth embodiment of the present invention will be described with reference to the drawings.

FIG. 8 shows a configuration of a semiconductor integrated circuit device according to a fourth embodiment of the present invention, wherein FIG.
(B) is a sectional view taken along the line IV-IV in (a). In FIG. 8A, reference numerals 41A and 41B denote field-programmable field-programmable products as a first integrated circuit.
A first FPGA substrate and a second FPGA substrate as a first semiconductor substrate on which a gate array is formed;
Is a standard produced field as a second integrated circuit.
A third FPGA substrate, which comprises a programmable gate array and serves as a second semiconductor substrate. A package 43 encloses each of the FPGA boards 41A, 41B, and 42.

As shown in FIG. 8B, the first FPGA
The FPG on the main surface 41a is provided on the main surface 41a of the substrate 41A.
A first pad as a first pad electrically connected to circuit A
FPGA substrate pad 81a is formed, and the second FP
On the main surface 41b of the GA substrate 41B, the F
A second FPGA substrate pad 81b as a first pad electrically connected to the PGA circuit is formed, and on the main surface 42a of the third FPGA substrate 42, the FPGA circuit on the main surface 42a is electrically connected. A third FPGA substrate pad 82a is formed as a second pad that is electrically connected. The main surfaces 41a and 41b of the first FPGA substrate 41A and the second FPGA substrate 41B and the third FPGA substrate 42
The main surface 42a is opposed to and connected to each of the pads 81a, 81b, 82a with a ball (or bump) 44 made of solder, gold or the like interposed therebetween using a semiconductor chip bonding technique. Thus, the circuits of each FPGA are electrically connected to each other.

Further, one end is connected to the FPGA circuit on the third FPGA substrate 42, and the other end is connected to the package 43.
An external terminal 45 protruding to the outside is provided.

The pads 81a, 81b, 82a
Are the first FPGA board 41A and the second FPGA board 4
It is assumed that design rules, structures, and pitches are formed in advance in the 1B and third FPGA boards 42 in a unified manner.

A circuit desired as a semiconductor integrated circuit device can be realized by performing programming from the external terminal 45 using a program device.

As described above, according to the present embodiment, by complementing the circuit scale of the FPGA manufactured in series during mass production, it is possible to realize a reduction in cost according to the circuit scale.

In this embodiment, the FPGA is used for each semiconductor substrate. However, the above-described circuit division based on the circuit scale is performed according to the type (series) of the gate array so that the redundant area is minimized. The selected and logically designed gate arrays may be connected face-to-face and packaged.

In the conventional FPGA, it is not possible to prepare an FPGA of any gate scale for economic reasons. As shown in FIG. 10 described above, it is assumed that four types of 1K gates, 2K gates, 4K gates, and 8K gates are prepared for the FPGA used in the semiconductor integrated circuit device according to this embodiment.

In the present embodiment, as shown in FIG. 9B, by changing the combination of the numbers of these gates, the available gate scale can be changed in 1K units, so that redundant gates are generated. Therefore, the redundancy cost Cd can be made substantially zero.

Hereinafter, a method for manufacturing a semiconductor integrated circuit device according to the fourth embodiment of the present invention will be described.

FIG. 9A is a flowchart showing a method for manufacturing a semiconductor integrated circuit device according to the fourth embodiment of the present invention. First, as shown in FIG.
At 41, the function of the semiconductor integrated circuit to be designed is designed.

Next, in a circuit scale determining step ST42, after estimating the circuit scale and determining the circuit scale from the estimated scale, in a device manufacturing step ST43, based on the determined circuit scale, the circuit scale becomes 7K gates. Then
For example, the first FPGA substrate 41A shown in FIG.
The existing 2K gate is assigned to the second FPGA substrate 4
Allocate an existing 1K gate to 1B, and further add a third FP
By allocating an existing 4K gate to the GA substrate 42, a circuit having a total of 7K gates is formed, and pads are formed on each substrate by the same method as that described in the device manufacturing process ST34 in the third embodiment. Performing

Next, in a circuit determination step ST44, an electric signal is inputted from an external terminal using a program device,
A semiconductor integrated circuit device in which a desired circuit is specified by programming is obtained.

In each of the embodiments of the present invention, the number of the first semiconductor substrates is two. However, the number of the first semiconductor substrates is not limited to two, and may be only one such as RAM or MPU. An off-the-shelf LSI such as a DSP or an EPROM may be added as the first semiconductor substrate, and the number may be three or more.

The circuits are connected with the main surfaces of the substrates facing each other. However, the present invention is not limited to this. The positions of the pads are changed so that the back surfaces are connected to each other or the main surface and the back surface are connected. It doesn't matter.

Further, the external terminals are taken out of the package from the second semiconductor substrate. However, the present invention is not limited to this, and the external terminals may be taken out of the first semiconductor substrate.

[0143]

According to the semiconductor integrated circuit device of the first aspect of the present invention, the circuit of the second integrated circuit is specified by connecting or disconnecting the redundant wiring by an electric signal input from an external terminal. With such a configuration, the development period after the completion of the logic design can be extremely shortened, so that the cost can be reduced.

According to the semiconductor integrated circuit device of the second aspect of the present invention, the effect of the semiconductor integrated circuit device of the first aspect of the present invention is obtained, and the logic circuit of the second integrated circuit is specified. , Can be used for specific applications.

According to the semiconductor integrated circuit device according to the third aspect of the present invention, the effects of the semiconductor integrated circuit device according to the first or second aspect of the present invention can be obtained, and in addition, the second integrated circuit can be formed by a field programmable gate array. Therefore, a desired circuit can be reliably specified in a short time after packaging is completed.

According to the semiconductor integrated circuit device of the fourth aspect of the present invention, the second integrated circuit is configured so that the circuit is specified by forming the wiring layer. Since the development period can be shortened,
Cost reduction can be achieved.

According to the semiconductor integrated circuit device of the fifth aspect of the present invention, the effect of the semiconductor integrated circuit device of the fourth aspect of the present invention is obtained, and the second integrated circuit is constituted by a gate array. By forming a wiring layer, a desired circuit can be reliably specified.

According to the semiconductor integrated circuit device of the present invention, since the second integrated circuit is composed of versatile cells, the second integrated circuit can be designed with high performance and flexibility. , Can enhance the performance of the device.

According to the semiconductor integrated circuit device of the seventh aspect of the present invention, the effect of the semiconductor integrated circuit device of the sixth aspect of the present invention is obtained, and the second integrated circuit is constituted by standard cells. , The performance of the second integrated circuit can be reliably improved.

According to the semiconductor integrated circuit device of the present invention, since the second integrated circuit is composed of a rewritable memory, the development period after completion of the logic design can be extremely shortened, so that the cost can be reduced. Can be achieved.

According to the semiconductor integrated circuit device of the ninth aspect, the effects of the semiconductor integrated circuit devices of the first to eighth aspects can be obtained, and the first integrated circuit can be a field programmable gate array. , The development period after the logic design can be further reduced.

When the first and second semiconductor substrates connected face-to-face are all composed of FPGAs, redundant gates are not generated by combining pre-fabricated gate-scale substrates. Cost can be reduced.

According to the semiconductor integrated circuit device of the tenth aspect, the effect of the semiconductor integrated circuit device of the ninth aspect can be obtained, and the logic circuit of the FPGA of the first integrated circuit is specified. Therefore, it can be used for specific applications.

According to the semiconductor integrated circuit device of the eleventh aspect, the effects of the semiconductor integrated circuit devices of the first to eighth aspects can be obtained, and the first integrated circuit is constituted by a gate array. Therefore, the development period after logic design can be further reduced.

When the first and second semiconductor substrates connected face-to-face are all composed of a gate array, redundant gates are not generated by constructing a combination of off-the-shelf gate-scale substrates. The cost can be reduced accordingly.

According to the semiconductor integrated circuit device of the twelfth aspect, the effects of the semiconductor integrated circuit devices of the first to eighth aspects can be obtained, and the first integrated circuit is constituted by standard cells. Therefore, the performance of the second integrated circuit can be reliably improved.

According to the semiconductor integrated circuit device of the thirteenth aspect, the effects of the semiconductor integrated circuit devices of the first to eighth aspects can be obtained, and the first integrated circuit is constituted by a rewritable memory. Therefore, the development period after the logic design can be further reduced.

According to the semiconductor integrated circuit device of the fourteenth aspect, the effects of the semiconductor integrated circuit devices of the first to eighth aspects can be obtained, and the first integrated circuit is standard-produced. , A core circuit including a memory, an MPU, a DSP, and the like, it is possible to simultaneously achieve high performance and low cost.

According to the method of manufacturing a semiconductor integrated circuit device according to the fifteenth aspect, the second integrated circuit is configured so that the circuit is specified by an electric signal input from an external terminal. Since the development period of the device can be extremely shortened, the cost can be reduced.

According to the method of manufacturing a semiconductor integrated circuit device of the sixteenth aspect, the effect of the method of manufacturing a semiconductor integrated circuit device of the fifteenth aspect can be obtained, and the logic circuit of the second integrated circuit can be obtained. Can be used for a specific application.

According to the method for manufacturing a semiconductor integrated circuit device according to the seventeenth aspect of the present invention, the effect of the method for manufacturing a semiconductor integrated circuit device according to the fifteenth or sixteenth aspect can be obtained, and the second integrated circuit can be manufactured Since the circuit is constituted by the field programmable gate array, a desired circuit can be reliably specified in a short time after the completion of the packaging.

According to the method for manufacturing a semiconductor integrated circuit device of the eighteenth aspect, the second integrated circuit is configured so that the circuit is specified by forming the wiring layer, and therefore, after completion of the logical design. Since the development period of the device can be shortened, the cost can be reduced.

According to the method of manufacturing a semiconductor integrated circuit device according to the nineteenth aspect of the present invention, the effect of the method of manufacturing a semiconductor integrated circuit device according to the eighteenth aspect of the present invention can be obtained, and the second integrated circuit can be formed by a gate array. Therefore, a desired circuit can be reliably specified by forming a wiring layer.

According to the method of manufacturing a semiconductor integrated circuit device according to the twentieth aspect, the effects of the method of manufacturing a semiconductor integrated circuit device according to the fifteenth to nineteenth aspects can be obtained.
Since the first integrated circuit is constituted by the field programmable gate array, the development period after logic design can be further reduced.

In the case where the first and second semiconductor substrates to be connected face to face are all FPGA substrates on which FPGAs are formed, redundant gates are not generated by combining substrates of a ready-made gate size. Therefore, the cost can be reduced accordingly.

According to the method of manufacturing a semiconductor integrated circuit device according to the twenty-first aspect of the present invention, the effects of the method of manufacturing a semiconductor integrated circuit device according to the twentieth aspect of the invention can be obtained, and the FPGA of the first integrated circuit can Because the logic circuit is specified,
Can be used for specific applications.

According to the method of manufacturing a semiconductor integrated circuit device according to the twenty-second aspect, the effects of the method of manufacturing a semiconductor integrated circuit device according to the fifteenth to nineteenth aspects can be obtained.
Since the first integrated circuit is constituted by the gate array, the development period after the logic design can be further reduced.

When the first and second semiconductor substrates to be connected face-to-face are all GA substrates on which a gate array is formed, redundant gates are generated by combining existing gate-sized substrates. Since it is eliminated, the cost can be reduced accordingly.

According to the method of manufacturing a semiconductor integrated circuit device according to the twenty-third aspect of the present invention, the effects of the method of manufacturing a semiconductor integrated circuit device according to the fifteenth to nineteenth aspects can be obtained.
Since the first integrated circuit is composed of the standard cells, the performance of the second integrated circuit can be reliably improved.

According to the method of manufacturing a semiconductor integrated circuit device according to the twenty-fourth aspect, the effects of the method of manufacturing a semiconductor integrated circuit device according to the fifteenth to nineteenth aspects can be obtained.
Since the first integrated circuit is configured by a rewritable memory, the development period after logic design can be further reduced.

According to the method of manufacturing a semiconductor integrated circuit device according to the twenty-fifth aspect of the present invention, the effects of the method of manufacturing a semiconductor integrated circuit device of the fifteenth to nineteenth aspects can be obtained.
The first integrated circuit is standard-produced, for example, a memory, M
Since it is configured by a PU or a DSP, it is possible to achieve high performance and low cost at the same time.

[Brief description of the drawings]

FIGS. 1A and 1B show a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention, wherein FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along line II in FIG.

FIG. 2 is a flowchart illustrating a method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 3 is a time chart illustrating a development period of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 4 is a correlation diagram of a manufacturing cost of a semiconductor integrated circuit device according to the first embodiment of the present invention and a manufacturing cost of a conventional embedded array type integrated circuit device with respect to a circuit size of a developed circuit.

5A and 5B show a configuration of a semiconductor integrated circuit device according to a second embodiment of the present invention, wherein FIG. 5A is a plan view, and FIG. 5B is a cross-sectional view taken along line II-II in FIG.

6A and 6B show a configuration of a semiconductor integrated circuit device according to a third embodiment of the present invention, wherein FIG. 6A is a plan view, and FIG. 6B is a cross-sectional view taken along line III-III in FIG.

FIG. 7A is a flowchart illustrating a method for manufacturing a semiconductor integrated circuit device according to a third embodiment of the present invention. (B)
FIG. 11 is a time chart illustrating a development period of the semiconductor integrated circuit device according to the third embodiment of the present invention.

8A and 8B show a configuration of a semiconductor integrated circuit device according to a fourth embodiment of the present invention, wherein FIG. 8A is a plan view, and FIG. 8B is a cross-sectional view taken along the line IV-IV in FIG.

FIG. 9A is a flowchart illustrating a method for manufacturing a semiconductor integrated circuit device according to a fourth embodiment of the present invention. (B)
FIG. 14 is a correlation diagram of a manufacturing cost of the semiconductor integrated circuit device according to the fourth embodiment of the present invention with respect to a development scale.

FIG. 10 is a correlation diagram of a manufacturing cost of a semiconductor integrated circuit device with respect to a conventional development scale.

FIG. 11 is a time chart showing a development period of a conventional field programmable gate array.

FIG. 12 is a time chart showing a development period of a conventional gate array.

FIG. 13 is a time chart showing a development period of a conventional standard cell.

FIG. 14 is a time chart showing a development period of a conventional embedded array.

[Explanation of symbols]

11A RAM substrate (first semiconductor substrate) 11a main surface 11B MPU substrate (first semiconductor substrate) 11b main surface 12 FPGA substrate (second semiconductor substrate) 12a main surface 13 package 14 ball 15 external terminal 51a RAM substrate Pad (first pad) 51b MPU substrate pad (first pad) 52a FPGA substrate pad (second pad) ST1 Already-manufactured circuit determination step (first integrated circuit formation step) ST2 Remaining circuit scale determination step (Second integrated circuit forming step) ST3 Device manufacturing step ST4 Circuit determination step 21A RAM substrate (first semiconductor substrate) 21a Main surface 21B MPU substrate (first semiconductor substrate) 21b Main surface 22 GA substrate (second substrate) Semiconductor substrate) 22a Main surface 23 Package 24 Ball 25 External terminal 61a Pad for RAM substrate (No. 61b MPU substrate pad (first pad) 62a GA substrate pad (second pad) 31A FPGA substrate (first semiconductor substrate) 31a main surface 31B MPU substrate (first semiconductor substrate) 31b main Surface 32 Standard cell substrate (second semiconductor substrate) 32a Main surface 33 Package 34 Ball 35 External terminal 71a Pad for FPGA substrate (first pad) 71b Pad for MPU substrate (first pad) 72a Pad for standard cell substrate (Second pad) ST31 Existing circuit determination step (first integrated circuit forming step) ST32 Manufacturing circuit determination step ST33A Remaining circuit scale determination step ST33B Second integrated circuit manufacturing step ST34 Device manufacturing step ST35 Circuit determination step 41A 1 FPGA substrate (first semiconductor substrate) 41a main surface 41B Second FPGA substrate (first semiconductor substrate) 41b Main surface 42 Third FPGA substrate (second semiconductor substrate) 42a Main surface 43 Package 44 Ball 45 External terminal 81a First FPGA substrate pad (First 81b Second FPGA board pad (first pad) 82a Third FPGA board pad (second pad) ST41 Function design decision step ST42 Circuit size decision step ST43 Device manufacturing step ST44 Circuit decision step

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Kazuo Tsuzuki 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd.

Claims (25)

[Claims] A first integrated circuit formed on a main surface of a first semiconductor substrate; and a first integrated circuit formed on a main surface of a second semiconductor substrate, the first integrated circuit having redundant wiring and being connected to an external terminal. A second integrated circuit whose circuit is specified by connecting or disconnecting the redundant wiring by an input electric signal; and a second integrated circuit formed on a main surface of the first semiconductor substrate, A first pad electrically connected to a circuit; and a second pad formed on a main surface of the second semiconductor substrate and electrically connected to the second integrated circuit. A main surface of the first semiconductor substrate and a main surface of the second semiconductor substrate are opposed to each other, and the first pad and the second pad are connected to each other, whereby the first Wherein the integrated circuit and the second integrated circuit are electrically connected. That the semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the circuit of the second integrated circuit is specified by an electric signal input from an external terminal. 3. The semiconductor integrated circuit device according to claim 1, wherein said second integrated circuit comprises a field programmable gate array. 4. A semiconductor device comprising: a first integrated circuit formed on a main surface of a first semiconductor substrate; and an active element formed on a main surface of a second semiconductor substrate and formed in advance. And a second integrated circuit whose circuit is specified by forming a wiring layer; and a second integrated circuit formed on a main surface of the first semiconductor substrate and electrically connected to the first integrated circuit. A first pad, and a second pad formed on a main surface of the second semiconductor substrate and electrically connected to the second integrated circuit, wherein the first semiconductor When the main surface of the substrate and the main surface of the second semiconductor substrate face each other and the first pad and the second pad are connected, the first integrated circuit and the second integrated circuit are connected to each other. A semiconductor integrated circuit device electrically connected to a circuit. 5. The semiconductor integrated circuit device according to claim 4, wherein said second integrated circuit comprises a gate array. 6. A first integrated circuit formed on a main surface of a first semiconductor substrate, and a second integrated circuit formed on a main surface of a second semiconductor substrate and comprising a versatile cell. An integrated circuit, a first pad formed on a main surface of the first semiconductor substrate, and electrically connected to the first integrated circuit, and a main surface of the second semiconductor substrate A second pad formed on the second integrated circuit and electrically connected to the second integrated circuit, wherein a main surface of the first semiconductor substrate and a main surface of the second semiconductor substrate are connected to each other. A semiconductor, wherein the first integrated circuit and the second integrated circuit are electrically connected to each other by connecting the first pad and the second pad so as to face each other; Integrated circuit device. 7. The semiconductor integrated circuit device according to claim 1, wherein said second integrated circuit comprises a standard cell. 8. A first integrated circuit formed on a main surface of a first semiconductor substrate, and a second integrated circuit formed on a main surface of a second semiconductor substrate and comprising a rewritable memory. An integrated circuit; a first pad formed on a main surface of the first semiconductor substrate and electrically connected to the first integrated circuit; and a main pad of the second semiconductor substrate. And a second pad electrically connected to the second integrated circuit, wherein a main surface of the first semiconductor substrate and a main surface of the second semiconductor substrate are opposed to each other. And the first integrated circuit is electrically connected to the second integrated circuit by connecting the first pad and the second pad. Circuit device. 9. The semiconductor integrated circuit device according to claim 1, wherein said first integrated circuit comprises a field programmable gate array. 10. The semiconductor integrated circuit device according to claim 9, wherein a logic circuit of the field programmable gate array is specified by an electric signal input from an external terminal. 11. The semiconductor integrated circuit device according to claim 1, wherein said first integrated circuit comprises a gate array. 12. The semiconductor device according to claim 1, wherein said first integrated circuit comprises a standard cell.
Item 13. The semiconductor integrated circuit device according to Item 1. 13. The semiconductor integrated circuit device according to claim 1, wherein said first integrated circuit comprises a rewritable memory. 14. The semiconductor integrated circuit device according to claim 1, wherein said first integrated circuit is an integrated circuit manufactured in a standard manner. 15. A first integrated circuit for forming a first integrated circuit having a function and a circuit scale determined on a main surface of a first semiconductor substrate.
An integrated circuit forming step; a second integrated circuit determining step of determining a circuit scale of a second integrated circuit from a circuit scale of the first integrated circuit; and a circuit scale on a main surface of the second semiconductor substrate. And a second integrated circuit forming a second integrated circuit having a redundant wiring and having a circuit specified by the connection or disconnection of the redundant wiring by an electric signal input from an external terminal A circuit forming step, forming a first pad electrically connected to the first integrated circuit on a main surface of the first semiconductor substrate, and forming a first pad on the main surface of the second semiconductor substrate. A pad forming step of forming a second pad electrically connected to a second integrated circuit; and a main surface of the first semiconductor substrate and a main surface of the second semiconductor substrate facing each other; The first pad is connected to the second pad, and the first pad is connected to the first pad. Packaging the first semiconductor substrate and the second semiconductor substrate with external terminals electrically connected to the integrated circuit or the second integrated circuit protruding outside the package And a method of manufacturing a semiconductor integrated circuit device. 16. A function determining step of determining a logical function of the second integrated circuit after the packaging step; and inputting an electric signal from an external terminal of the package, and determining the logic of the second integrated circuit. And a circuit specifying step of specifying the second integrated circuit by connecting or disconnecting the redundant wiring provided in the second integrated circuit so that the function is realized. The method for manufacturing a semiconductor integrated circuit device according to claim 15, wherein: 17. The method according to claim 15, wherein the second integrated circuit comprises a field programmable gate array. 18. A first integrated circuit for forming a first integrated circuit having a function and a circuit scale determined on a main surface of a first semiconductor substrate.
An integrated circuit forming step of: determining a circuit scale of a second integrated circuit from a circuit scale of the first integrated circuit, and determining a logical function of the second integrated circuit; A second semiconductor substrate wiring layer forming step of forming a wiring layer on a main surface of the second semiconductor substrate so as to realize a determined logical function of the second integrated circuit; Forming a first pad electrically connected to the first integrated circuit on a main surface of the semiconductor substrate, and electrically connecting the second integrated circuit to a main surface of the second semiconductor substrate. Forming a second pad connected to the first semiconductor substrate; and a main surface of the first semiconductor substrate and a main surface of the second semiconductor substrate are opposed to each other. A pad, and electrically connected to the first integrated circuit or the second integrated circuit. A semiconductor integrated circuit device comprising: a packaging step of packaging the first semiconductor substrate and the second semiconductor substrate in a state where the connected external terminals protrude outside the package. Manufacturing method. 19. The method according to claim 18, wherein the second integrated circuit comprises a gate array. 20. A field programmable gate array, wherein the first integrated circuit is provided with redundant wiring, and a circuit is specified by connecting or disconnecting the redundant wiring by an electric signal input from an external terminal. 20. The method of manufacturing a semiconductor integrated circuit device according to claim 15, further comprising: 21. A function determining step of determining a logical function of the first integrated circuit after the packaging step; and inputting an electric signal from an external terminal of the package to define the logical function of the first integrated circuit. A circuit specifying step of specifying the first integrated circuit by connecting or disconnecting a redundant wiring provided in the first integrated circuit so that a function is realized. The method for manufacturing a semiconductor integrated circuit device according to claim 20. 22. The semiconductor device according to claim 15, wherein the first integrated circuit comprises a gate array.
13. The method for manufacturing a semiconductor integrated circuit device according to the above item. 23. The method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein said first integrated circuit comprises a standard cell. 24. The method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein said first integrated circuit comprises a rewritable memory. 25. The method according to claim 15, wherein the first integrated circuit is a standard-produced integrated circuit.