CN108595748A - A kind of three dimensional topology of anti-fuse FPGA programmable logic array - Google Patents
A kind of three dimensional topology of anti-fuse FPGA programmable logic array Download PDFInfo
- Publication number
- CN108595748A CN108595748A CN201810193681.6A CN201810193681A CN108595748A CN 108595748 A CN108595748 A CN 108595748A CN 201810193681 A CN201810193681 A CN 201810193681A CN 108595748 A CN108595748 A CN 108595748A
- Authority
- CN
- China
- Prior art keywords
- dimensional
- programmed logical
- programmable logic
- wiring channel
- logical module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Architecture (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The present invention designs a kind of novel three-dimensional topological structure can be applied to anti-fuse FPGA programmable logic array.Compared to the programmable logic array of conventional two-dimentional anti-fuse FPGA, which has the advantages such as capacity is big, performance is high.The invention firstly uses two kinds of programmed logical modules to complete from programmable logic row to programmable logic layer, then building to programmable logic array, constructs a kind of programmed logical module arrangement architecture of three-dimensional.For a variety of wiring channels of the structure design, and the different interconnection strategies that different wire laying modes is set to wiring channel, while being used between adjacent and apart from each other programmed logical module, so as to complete the interconnection of programmable logic array.It is expansible in all directions that finally obtained three dimensional topology has the characteristics that space three-dimensional, interconnection resource are abundant, wire laying mode flexibly, between programmed logical module interconnects convenience, overall structure, with the application of the invention, large capacity, high performance anti-fuse FPGA can be designed.
Description
Technical field
The invention belongs to integrated circuit fields, design is a kind of to can be applied to the novel of anti-fuse FPGA programmable logic array
Three dimensional topology.
Background technology
FPGA as a kind of typical programmable logic device, be broadly divided into anti-fuse type FPGA, SRAM type FPGA,
EEPROM/FLASH types FPGA etc..Wherein, anti-fuse FPGA is a kind of utilization anti-fuse technology programmable FPGA of realization, it has
There are non-volatile, disposable programmable, radioresistance and highly reliable.The programmed logical module of typical anti-fuse FPGA is logical
Often it is divided into Programmable Combinational Logic module (hereinafter referred to as PCM) and programmable timing sequence logic module (hereinafter referred to as PSM).
The programmable logic array of traditional FPGA is distributed with two-dimension plane structure, increasing with the scale of FPGA, mark
The fpga chip area of quasi- two-dimensional structure is also increasing, and area is excessive to often result in that chip yield is low, performance declines, even
Encapsulation is cannot achieve beyond encapsulating package size.Contradiction between the capacity of FPGA, performance and chip area is more and more significant.
For anti-fuse FPGA, this contradiction is more prominent.The programmable logic array of the large capacity FPGA of two-dimensional structure is flat
Extension on face causes routing path increasingly longer, since anti-fuse cell itself has apparent dead resistance and parasitism electricity
Hold, thus the degree that becomes negatively affected of the performance of anti-fuse FPGA than performance of other types without apparent ghost effect FPGA by negative
Face effect is more prominent.In addition, antifuse needs high pressure to program, high voltage bearing characteristic determine anti-fuse cell itself and
High tension apparatus size in programmed circuit should not be too small, and the degree scaled with process modification is also just limited.Having
Limit area two dimensional surface in, anti-fuse FPGA than using SRAM structures as other type FPGA of representative in terms of capacity extensions by
Limit becomes apparent from.Therefore, large capacity, high performance anti-fuse FPGA to be realized, architecturally innovation is particularly important.
With the rapid development of electronic information technology, the complexity of system is higher and higher, and the scale of circuit is increasing, is
The requirement united to performance is also higher and higher, and for the continuous promotion of adaptive system demand, three dimensional integrated circuits come into being and obtain
Fast development is arrived, the three-dimensional packaging technology that representative is integrated into multi-chip package is increasingly extensively and ripe, is to carry with single-chip
Density three-dimensional circuit integration technique is also concerned and obtains preferable development in the piece of body.
Based on three-dimensional integration technology, framework innovation is carried out to anti-fuse FPGA, structure three-dimensional anti-fuse FPGA is to solve greatly
The effective solution of capacity, high-performance anti-fuse FPGA design bottleneck problem.First, by anti-fuse FPGA by two-dimensional expansion to
Three-dimensional, can the longitudinal development in limited area increase the scale of anti-fuse FPGA design to crack capacity limit；Its
Secondary, the programmed logical module of three-dimensional anti-fuse FPGA is compacter, and interconnection resource is more abundant on three dimensions, logic mould
Interconnection between block is more convenient flexibly, and the interconnection line length of arrangement wire of practical application in a disguised form shortens because three dimensional stress is distributed, therefore compares
Conventional two-dimensional structure FPGA can be significantly improved in speed ability.
Three dimensional stress encapsulates integrated and single between current existing integrated circuit three-dimensional integration technology is broadly divided into multi-chip piece
Three dimensional stress circuit integrates two classes in piece piece.If three dimensional stress encapsulation is integrated between three-dimensional anti-fuse FPGA uses multi-chip piece, core
To be attached based on chip pin between piece, need between the programmed logical module in different chips by I/O circuits and
Chip pin bridge joint establishes interconnection, and bridges Xing Hu joint conferences and brings additional ghost effect, though therefore the technology can effectively improve
The scale of FPGA, but the performance of FPGA can not be obviously improved.If three-dimensional anti-fuse FPGA is using three dimensional stress in single-chip piece
Circuit is integrated, then is needed not move through between programmed logical module and bridge and directly interconnected in piece between piece, to promote FPGA rule
The abundant promotion of FPGA performances can be effectively ensured while mould.Three dimensional stress encapsulation is integrated between multi-chip piece only lays particular emphasis on simple expansion
Hold, and three dimensional stress circuit is integrated in single-chip piece is related to essential framework innovation, has taken into account dilatation and performance boost.
The present invention proposes a kind of anti-fuse FPGA programmable logic array of can be applied under the background analyzed above
Novel three-dimensional topological structure, the structural wiring is resourceful, and wire laying mode is flexible and changeable.Further, since the structure using
Circuit level it is three-dimensionally integrated, rather than package level is three-dimensionally integrated, thus its for anti-fuse FPGA in scale and performance
On promotion effect it is more notable.Present invention can apply to design large capacity, high performance anti-fuse FPGA.
Invention content
The present invention designs a kind of novel three-dimensional topological structure applied to anti-fuse FPGA programmable logic array, with routine
Two-dimentional FPGA is compared, and three-dimensional anti-fuse FPGA has a variety of advantages such as capacity is big, performance is high.
The technical scheme is that a three-dimensional arrangement structure is constructed using multiple PCM and PSM, it is more for the structure design
Kind wiring channel, and pass through different interconnection sides between the programmed logical module of adjacent programmed logical module and distance farther out
Case makes modules realize interconnection, to obtain final topological structure.Structure proposed by the invention ensure that programmable patrol
Volume intermodule interconnection resource is abundant, wire laying mode is various, and substantially increases the speed of anti-fuse FPGA, expands antifuse
The scale of FPGA.
Topological structure described above includes at least the three-dimensional arrangement structure and programmable logic mould of programmed logical module
Wiring channel between block and cabling scenario.It is characterized in that there is following steps：
1) three-dimensional arrangement using Programmable Combinational Logic module and programmable timing sequence logic module in space forms one kind
The multi-layer three-dimension arrangement architecture of programmed logical module；
2) for the multi-layer three-dimension arrangement architecture of programmed logical module, in layer and the adjacent programmable logic mould of interlayer
A variety of wiring channels are set between block；
3) by different wire laying modes, the interconnection between adjacent programmed logical module is realized, farther out for distance
Programmed logical module realizes interconnection by half long line and long line.
It is expansible in x, y, z all directions for the multi-layer three-dimension arrangement architecture of programmed logical module.The structure is most
Simple application is the structure for only having two layers in the directions z, and require the design of bigger can be used chip-scale has in the directions z
The structure of 3 layers or more layers.
It can be according to reality between one programmed logical module and all other programmed logical modules adjacent thereto
Demand chooses whether setting wiring channel；Wiring channel has four types：Axial wiring channel, the wiring of layer inner opposite angle line are logical
Road, interlayer plane diagonal line wiring channel and interlayer space diagonal line wiring channel；Cloth between adjacent programmed logical module
There is line passage the wiring of saturation type short-term and simple type short-term to connect up two ways, any one cloth can be used in each wiring channel
Line mode, to ensure the abundant and wire laying mode flexible of interconnection resource.
The structure should take the mode that three dimensional stress circuit is integrated in single-chip piece to be manufactured in actually manufacturing, without
It is that the mode that three dimensional stress encapsulation is integrated between taking multi-chip piece manufactures.
The structure do not limit to applied to anti-fuse FPGA three dimensional stress design, apply also for SRAM type FPGA and
The three dimensional stress of EEPROM/FLASH types FPGA designs.
Description of the drawings
Fig. 1 is the multi-layer three-dimension arrangement architecture of programmed logical module in the present invention.
Fig. 2 is the complete wiring channel distributed in three dimensions schematic diagram of the present invention.
Fig. 3 is that the wiring channel in the present invention between an adjacent programmed logical module of programmed logical module is three-dimensional
Distribution schematic diagram.
Fig. 4 is the wiring channel distribution schematic diagram for having exemplary two dimensional FPGA.
Fig. 5 is the axial wiring channel distributed in three dimensions schematic diagram of the present invention.
Fig. 6 is the complete wiring channel distribution schematic diagram of layer inner opposite angle line of the present invention.
Fig. 7 is the layer inner opposite angle line wiring channel Class1 of the present invention.
Fig. 8 is the layer inner opposite angle line wiring channel type 2 of the present invention.
Fig. 9 is the complete wiring channel distributed in three dimensions schematic diagram of interlayer plane diagonal line of the xz planes of the present invention.
Figure 10 is the interlayer plane diagonal line wiring channel Class1 of the xz planes of the present invention.
Figure 11 is the interlayer plane diagonal line wiring channel type 2 of the xz planes of the present invention.
Figure 12 is the interlayer space pair between a programmed logical module and neighbouring programmed logical module in the present invention
Linea angulata wiring channel schematic diagram.
Figure 13 is the saturation type short-term interconnection resource schematic diagram of wiring channel.
Figure 14 is the simple type short-term interconnection resource schematic diagram of wiring channel.
Figure 15 is the mixing interconnection resource schematic diagram across multiple programmed logical modules.
Figure 16 is the wiring example effects comparison diagram of the present invention and existing exemplary two dimensional structure.
Figure 17 is a kind of three dimensional wiring example effects figure of preferable typical case of the present invention.
Specific implementation mode
To keep technical scheme of the present invention, structure and advantage clearer, with reference to the attached drawing in the embodiment of the present invention
Clear, complete description is carried out to the technical solution in embodiment in the present invention.Based on the embodiments of the present invention, this field is general
All other embodiment that logical technical staff is obtained without making creative work belongs to what the present invention protected
Range.
Fig. 1 is the multi-layer three-dimension arrangement architecture of programmed logical module in the present invention.First in the directions x, two kinds can be compiled
Journey logic module is successively respectively with PCM-PSM-PCM ... and the sequence of PSM-PCM-PSM ... (or being carried out with reverse order) arrangement,
Programmable logic row L1 and L2 are constituted, then by L1 and L2 in y-direction respectively with L1L2L1L2 ... and L2L1L2L1's ... is suitable
Sequence is arranged to make up two kinds of programmable logic layer F1 and F2, both programmable logic layers are located at x/y plane, similar conventional two dimension
The programmable logic array of FPGA.Finally by two kinds of programmable logic layers with F1F2F1F2 ... or the sequence of F2F1F2F1 ... is arranged
Row, you can constitute a multi-layer three-dimension arrangement architecture.In figure for simplicity, only drawing three in three directions of x, y, z can
Programmed logic module distance is illustrated, and in practical manufacture, all directions can be extended.For x, y, z side shown in FIG. 1
To only there are three the three-dimensional structure of programmed logical module distance, we call it as a programmable logic structure cell.
The manufacture of three-dimensional FPGA should first produce one layer, then manufacture the second layer on the first layer, and so on.For
Facilitate discussion, it will be assumed that the present invention always first manufactures the programmable logic layer of x/y plane in practical applications, then in the directions z
It is stacked, and the identical programmed logical module of each group of z coordinate is known as a programmable logic layer (hereinafter referred to as layer).
For a programmable logic structure cell, in the directions z, there are three layers for it.
Fig. 2 is the complete wiring channel distributed in three dimensions schematic diagram of the present invention.Maximum feature of the invention is any one
It all can designing wiring channel between programmed logical module and its all adjacent programmed logical module.It is so-called adjacent programmable
Logic module refers in the three-dimensional centre of the programmable logic unit cell dimension centered on a programmed logical module except should
All other programmed logical module other than logic module.
Fig. 3 is that the wiring channel in the present invention between an adjacent programmed logical module of programmed logical module is three-dimensional
Distribution schematic diagram.These wiring channels are divided into four major class by us, will be apparent from below.
Fig. 4 is the wiring channel distribution schematic diagram for having exemplary two dimensional FPGA.Its feature is, between programmed logical module
Wiring channel be located at the directions x and the directions y, and there is no wiring channel in other directions.
Fig. 5 is the axial wiring channel distributed in three dimensions schematic diagram of the present invention.Axial wiring channel is first in the present invention
Class wiring channel, it is similar with the conventional two dimension wiring channel of FPGA, and difference lies in it is on the basis of two-dimentional wiring channel
Also add wiring channel in a z-direction.Since these wiring channels are all parallel with reference axis, we are by this kind of cloth
Line passage is known as axial wiring channel.
Fig. 6 is the complete wiring channel distribution schematic diagram of layer inner opposite angle line of the present invention.Layer inner opposite angle line wiring channel is this
The second class wiring channel in invention.By taking a programmable logic structure cell as an example, layer inner opposite angle line wiring channel is located at each layer
On the diagonal line of the four small rectangles determined by programmed logical module.Due to this kind of wiring channel will not cross-layer occur and be in
Diagonal line be distributed, still this wiring channel is known as layer inner opposite angle line wiring channel.This wiring channel can there are two
Direction, therefore there are two types.
Fig. 7 is the layer inner opposite angle line wiring channel Class1 of the present invention.
Fig. 8 is the layer inner opposite angle line wiring channel type 2 of the present invention.
Fig. 9 is the complete wiring channel distributed in three dimensions schematic diagram of interlayer plane diagonal line of the xz planes of the present invention.Interlayer is flat
Face diagonal wiring channel is the third class wiring channel in the present invention, it is located between layers, with a programmable logic
For structure cell, some are similar for interlayer plane diagonal line wiring channel and layer inner opposite angle line wiring channel, it is located at xz planes and yz
On the diagonal line of the four small rectangles determined by programmed logical module in plane, similarly, the interlayer in each plane is flat
There are two types for face diagonal wiring channel.
Figure 10 is the interlayer plane diagonal line wiring channel Class1 of the xz planes of the present invention.
Figure 11 is the interlayer plane diagonal line wiring channel type 2 of the xz planes of the present invention.
The case where yz planes, is similar, is not repeated herein.
Figure 12 is that the interlayer space in the present invention between a programmed logical module and neighbouring programmed logical module is diagonal
Line wiring channel schematic diagram.Interlayer space diagonal line wiring channel is the 4th class wiring channel in the present invention, in addition to above three
Other wiring channels other than class wiring channel are known as interlayer space diagonal line wiring channel.It can be seen from the figure that positioned at crystalline substance
Wiring channel between eight vertex of programmed logical module at born of the same parents center and structure cell is exactly interlayer space diagonal line wiring channel.
It, can be according to practical need between the adjacent programmed logical module of any two in three-dimensional structure proposed by the invention
It asks and chooses whether designing wiring channel.
For the distribution connected up in wiring channel between adjacent programmed logical module, we devise two kinds of wire laying modes,
Respectively saturation type short-term wire laying mode and simple type short-term wire laying mode.Below with wiring channel between PCM and PSM
For, description of the drawings.
Figure 13 is the saturation type short-term interconnection resource schematic diagram of wiring channel, its main feature is that, with conventional two dimension FPGA wirings
Wiring distribution in channel is similar, under the premise of will not cause area loss, more short-term of arranging in wiring channel, specifically
The item number of short-term can determine that purpose exists according to the design and input and output quantity of the framework and PCM and PSM of anti-fuse FPGA
Between fully ensuring that programmed logical module can interconnectivity.
Figure 14 is the simple type short-term interconnection resource schematic diagram of wiring channel.The wiring bar number that such wire laying mode uses compared with
It is few, it only arranges in wiring channel minimum one, typical 3-5 items, preferably no more than 10 short-terms.
In both the above wire laying mode, every short-term all can be defeated by the input of anti-fuse structures and programmed logical module
Go out connected, programs specific antifuse, short-term just realizes with the specific input and output of programmed logical module and connect that here it is anti-
The embodiment of the programmability of fuse FPGA.
For the three-dimensional arrangement structure of programmed logical module, according to the difference of FPGA specific framework and design complexities,
Only can design axial direction wiring channel for it, or increase on the basis of axial wiring channel other three classes wiring channels one kind or
It is a variety of.Each wiring channel can all apply any one in two kinds of wire laying modes described above.So as to utmostly
It is upper to ensure the abundant and wire laying mode flexible of interconnection resource.In practical manufacturing process, due to each layer and conventional two dimension
The programmable logic array of FPGA is similar, and therefore, relatively good scheme is to be all made of saturation type short-term wire laying mode in each layer
With fully ensure that can interconnectivity.For axial wiring channel between layers, we can be applied to the wiring of saturation type short-term
Mode.And for interlayer plane diagonal line wiring channel and interlayer space diagonal line wiring channel, can both it apply saturation type short
Line wire laying mode can also apply simple type short-term wire laying mode.It is using the advantages of saturation type short-term wire laying mode available
Abundant interconnection resource realizes various somewhat complex designs between adjacent programmed logical module；And apply simple type short-term wire laying mode
The advantage is that such structure technique in practical manufacturing process is more simple, three-dimensional synthesis between layers is also more convenient.
Meanwhile taking the wiring of simple type short-term that can also reduce the requirement to Routing Algorithm.
It is discussed above be only adjacent programmed logical module between interconnection, and for across several modules or it is longer away from
From programmed logical module between interconnection, half long line can be used and long line is interconnected.
Figure 15 is the mixing interconnection resource schematic diagram across multiple programmed logical modules, can between adjacent programmed logical module
It is realized and is interconnected by short-term and antifuse, the programmed logical module across several modules can be realized by half long line and antifuse
Interconnection, and for the interconnection of longer distance, then it can be realized by long line and antifuse.Half long line and long line technology are applied to three
Dimension space, you can realize the interconnection between programmed logical module apart from each other in this structure.
For structure proposed by the invention, Routing Algorithm can be improved in the Routing Algorithm to conventional two dimension FPGA
After realized.
Below by two specific examples come the advantages of embodying novel topological structure proposed by the invention.
Figure 16 is the wiring example effects comparison diagram of the present invention and existing exemplary two dimensional structure.It can be found that utilizing this hair
Bright proposed structure, 3 × 3 × 3 structures, i.e., in the three-dimensional structure of 27 programmed logical modules, the two of lie farthest away
A programmed logical module is located at two of this structure to angular vertex, behind diagonal designing wiring channel, the two
Programmed logical module only needs that interconnection can be realized across a programmed logical module.And the two dimension of a routine can be compiled
Journey logic array, in 5 × 5 structures, even if the negligible amounts of its programmed logical module, realize lie farthest away two
The interconnection of programmed logical module but needs to complete to interconnect across 7 other programmed logical modules.As it can be seen that using this hair
Bright proposed structure can greatly reduce the distance between programmed logical module due to its three-dimensional character, reduce programmable logic
The length of the interconnection line of intermodule more easily interconnects to realize, while the reduction for interconnecting line length can also weaken various post
It comes into force and answers, improve the operating rate of chip.For larger anti-fuse FPGA, using structure proposed by the invention, also
Package dimension can be greatly reduced, with smaller one large-scale F PGA chip of case package.
Figure 17 is a kind of three dimensional wiring example effects figure of preferable typical case of the present invention.It can be seen from the figure that working as
When one design needs the more particular kind of programmed logical module of a certain kind to realize interconnection, it might as well assume this programmable
Logic module is PCM, using structure proposed by the invention, utilizes interlayer plane diagonal line wiring channel, it is only necessary to seldom cloth
The interconnection of multiple PCM can be realized in line resource, and completely dispenses with across arbitrary PSM.As it can be seen that due to structure proposed by the invention
Wiring channel is abundant, and wire laying mode is flexible, therefore less interconnection resource can be utilized to realize the fast direct between programmed logical module
Even, and the interconnection between the programmed logical module of same type will not be by the excessive of different types of programmed logical module
It influences.
In conclusion this invention proposed this can be applied to novel the three of anti-fuse FPGA programmable logic array
Tie up topological structure have space three-dimensional type, interconnection resource is rich and varied, wire laying mode is flexible and changeable, between programmed logical module mutually
The advantage that connection is convenient, overall structure is expansible in all directions.Using the present invention, extensive, high speed and encapsulation ruler can be easily realized
Very little small FPGA.The most simple application of structure proposed by the invention is the structure for only having two layers in the directions z, for chip-scale
It is required that the structure that higher design can be used 3 layers or 3 layers or more is realized.The structure should take single in actually manufacturing
The integrated mode of three dimensional stress circuit is manufactured in piece piece, rather than takes the mode system that three dimensional stress encapsulation is integrated between multi-chip piece
It makes.
The present invention is using anti-fuse FPGA as typical case, it is proposed that the three dimensional topology with versatility, the structure
It can be applied to the three dimensional stress design of SRAM type FPGA and EEPROM/FLASH type FPGA.When there are two types of programmable logic moulds in FPGA
When block, directly it can add the three-dimensional structure modeling of PSM by PCM using the present invention；When in FPGA only have a kind of programmed logical module
When, then by the present invention PCM and PSM be considered as after same programmed logical module directly three-dimensional structure using the present invention.
Claims (5)
1. a kind of novel three-dimensional topological structure can be applied to anti-fuse FPGA programmable logic array, wherein the topology knot
Structure includes at least the wiring channel and cloth between the three-dimensional arrangement structure and programmed logical module of programmed logical module
Line mode；It is characterized in that there is following steps：
1) three-dimensional arrangement using Programmable Combinational Logic module and programmable timing sequence logic module in space forms one kind and can compile
The multi-layer three-dimension arrangement architecture of journey logic module；
2) for the multi-layer three-dimension arrangement architecture of programmed logical module, in layer between the adjacent programmed logical module of interlayer
A variety of wiring channels are set；
3) by different wire laying modes, the interconnection between adjacent programmed logical module is realized, for distance compiling farther out
Journey logic module realizes interconnection by half long line and long line.
2. it can be applied to the novel three-dimensional topological structure of anti-fuse FPGA programmable logic array according to claim 1,
It is characterized in that, it is expansible in x, y, z all directions for the multi-layer three-dimension arrangement architecture of programmed logical module；The structure
Simplest application is the structure for only having two layers in the directions z, requires the design of bigger can be used chip-scale and has in the directions z
Have three layers or more the structure of layer.
3. it can be applied to the novel three-dimensional topological structure of anti-fuse FPGA programmable logic array according to claim 1,
It is characterized in that, it can be according to reality between a programmed logical module and all other programmed logical modules adjacent thereto
Demand chooses whether setting wiring channel；Wiring channel has four types：Axial wiring channel, the wiring of layer inner opposite angle line are logical
Road, interlayer plane diagonal line wiring channel and interlayer space diagonal line wiring channel；Cloth between adjacent programmed logical module
There is line passage the wiring of saturation type short-term and simple type short-term to connect up two ways, any one cloth can be used in each wiring channel
Line mode, to ensure the abundant and wire laying mode flexible of interconnection resource.
4. it can be applied to the novel three-dimensional topological structure of anti-fuse FPGA programmable logic array according to claim 1,
It is characterized in that, which should take the mode that three dimensional stress circuit is integrated in single-chip piece to be manufactured in actually manufacturing, and
It is not that the mode that three dimensional stress encapsulation is integrated between taking multi-chip piece manufactures.
5. it can be applied to the novel three-dimensional topological structure of anti-fuse FPGA programmable logic array according to claim 1,
Be characterized in that, the structure do not limit to applied to anti-fuse FPGA three dimensional stress design, apply also for SRAM type FPGA and
The three dimensional stress of EEPROM/FLASH types FPGA designs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810193681.6A CN108595748B (en) | 2018-03-09 | 2018-03-09 | Three-dimensional topological structure of antifuse Field Programmable Gate Array (FPGA) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810193681.6A CN108595748B (en) | 2018-03-09 | 2018-03-09 | Three-dimensional topological structure of antifuse Field Programmable Gate Array (FPGA) |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108595748A true CN108595748A (en) | 2018-09-28 |
| CN108595748B CN108595748B (en) | 2022-08-09 |
Family
ID=63625968
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810193681.6A Active CN108595748B (en) | 2018-03-09 | 2018-03-09 | Three-dimensional topological structure of antifuse Field Programmable Gate Array (FPGA) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108595748B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113033138A (en) * | 2021-03-08 | 2021-06-25 | 电子科技大学 | Novel FPGA structure based on power gating technology controlled by anti-fuse device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070235708A1 (en) * | 2006-03-30 | 2007-10-11 | International Business Machines Corporation | Programmable via structure for three dimensional integration technology |
| US20090009215A1 (en) * | 2004-05-12 | 2009-01-08 | Matsumoto Yohei | Integrated Circuit with Multidimensional Switch Topology |
| CN102116841A (en) * | 2011-01-04 | 2011-07-06 | 复旦大学 | Method for evaluating FPGA (Field Programmable Gata Array) interconnection structure based on quantization of model |
| CN103366028A (en) * | 2012-03-31 | 2013-10-23 | 中国科学院微电子研究所 | Field programmable gate array chip layout method |
| CN103678817A (en) * | 2013-12-20 | 2014-03-26 | 清华大学 | Hierarchical design method for three-dimensional field-programmable gate array based on three-dimensional reunion |
-
2018
- 2018-03-09 CN CN201810193681.6A patent/CN108595748B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090009215A1 (en) * | 2004-05-12 | 2009-01-08 | Matsumoto Yohei | Integrated Circuit with Multidimensional Switch Topology |
| US20070235708A1 (en) * | 2006-03-30 | 2007-10-11 | International Business Machines Corporation | Programmable via structure for three dimensional integration technology |
| CN102116841A (en) * | 2011-01-04 | 2011-07-06 | 复旦大学 | Method for evaluating FPGA (Field Programmable Gata Array) interconnection structure based on quantization of model |
| CN103366028A (en) * | 2012-03-31 | 2013-10-23 | 中国科学院微电子研究所 | Field programmable gate array chip layout method |
| CN103678817A (en) * | 2013-12-20 | 2014-03-26 | 清华大学 | Hierarchical design method for three-dimensional field-programmable gate array based on three-dimensional reunion |
Non-Patent Citations (3)
| Title |
|---|
| C. ABABEI ET AL.: "Placement and Routing in 3D Integrated Circuits", 《IEEE DESIGN & TEST OF COMPUTERS》 * |
| 王敏等: "三维结构可重构阵列在线自诊断与容错方法", 《仪器仪表学报》 * |
| 隋文涛等: "力驱动三维FPGA布局算法", 《计算机辅助设计与图形学学报》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113033138A (en) * | 2021-03-08 | 2021-06-25 | 电子科技大学 | Novel FPGA structure based on power gating technology controlled by anti-fuse device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108595748B (en) | 2022-08-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9515008B2 (en) | Techniques for interconnecting stacked dies using connection sites | |
| TWI745626B (en) | 3d compute circuit with high density z-axis interconnects | |
| US9825843B2 (en) | Die-stacked device with partitioned multi-hop network | |
| US6417690B1 (en) | Floor plan for scalable multiple level tab oriented interconnect architecture | |
| US20100140750A1 (en) | Parallel Plane Memory and Processor Coupling in a 3-D Micro-Architectural System | |
| CN104657535B (en) | Layout designs system, layout design method and the semiconductor device using its manufacture | |
| US20230378061A1 (en) | Fabric Die to Fabric Die Interconnect for Modularized Integrated Circuit Devices | |
| CN1128589A (en) | Architecture and interconnect scheme for programmable logic circuits | |
| WO2023030051A1 (en) | Stacked chip | |
| US6600341B2 (en) | Integrated circuit and associated design method using spare gate islands | |
| CN108595748A (en) | A kind of three dimensional topology of anti-fuse FPGA programmable logic array | |
| US9400762B2 (en) | Integrated device with memory systems accessible via basic and bypass routes | |
| US6696856B1 (en) | Function block architecture with variable drive strengths | |
| CN110162494A (en) | A kind of field programmable gate array chip and data interactive method | |
| CN104425000A (en) | Memory structure with multiple chips connected in series in sequence | |
| CN113722268A (en) | Storage and calculation integrated stacking chip | |
| CN113626373A (en) | Integrated chip | |
| Daneshtalab et al. | CMIT—A novel cluster-based topology for 3D stacked architectures | |
| CN113793632A (en) | Non-volatile programmable chip | |
| CN216118778U (en) | Stacking chip | |
| CN113626372B (en) | Integrated chip integrating memory and calculation | |
| CN216118777U (en) | Integrated chip | |
| CN105122227A (en) | High performance system topology for nand memory systems | |
| JPH01187666A (en) | Superconducting parallel processing processor | |
| CN113986813B (en) | Method, system, device and storage medium for network-on-chip architecture construction and use |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |