CN216118777U

CN216118777U - Integrated chip

Info

Publication number: CN216118777U
Application number: CN202122113256.1U
Authority: CN
Inventors: 郭一欣; 周骏; 左丰国; 马亮
Original assignee: Xian Unilc Semiconductors Co Ltd
Current assignee: Xian Unilc Semiconductors Co Ltd
Priority date: 2021-09-02
Filing date: 2021-09-02
Publication date: 2022-03-22
Anticipated expiration: 2031-09-02

Abstract

The utility model provides an integrated chip, wherein the integrated chip comprises: a first logic component, the first logic component comprising: a first logic component comprising: a first programmable gate array assembly comprising at least one first programmable gate array component; a first application specific integrated circuit array component located at the same layer as the at least one first programmable gate array component; a first interface module including a first bonding lead-out region; the first application specific integrated circuit array component and at least one first programmable gate array component are connected with the first interface module through the internal metal layer; the first memory array component is provided with a second bonding lead-out region, and the second bonding lead-out region and the first bonding lead-out region form three-dimensional heterogeneous integrated interconnection so as to connect the programmable gate array combination, the first application specific integrated circuit array component and interconnection signals on the first memory array component together. The purposes of high bandwidth and low power consumption of storage access are achieved.

Description

Integrated chip

Technical Field

The present invention relates to the field of integrated circuit technology, and more particularly, to an integrated chip.

Background

Fast technology iterations and evolution in the fields of artificial intelligence and 5G NR, etc., present challenges to the flexibility of Application Specific Integrated Circuits (ASICs). The existing solution is that an ASIC is collocated with a Field Programmable Gate Array (FPGA) or a part of a programmable architecture of an ASIC embedded field programmable gate array (effpga): implementing relatively fixed system functions on the ASIC; and realizing the variable system function of technical iteration and evolution lines on the FPGA or the eFPGA.

FPGAs or efgas carry system critical functions, usually requiring both extensive connections to ASICs and high bandwidth connections to external mass storage. Prior art as in fig. 1a, a partially programmable architecture for independent memory access: on the basis of establishing connection between the FPGA or the effpga and the ASIC (fig. 1a. am1) and connection between the ASIC and a large-scale memory such as a DRAM (fig. 1a. am2), and adding the FPGA or the effpga and the large-scale memory (fig. 1a. am3), it is necessary to use more IO interfaces of the FPGA or the effpga, and power consumption is increased. In the prior art, as shown in fig. 1b, a bus is used to establish connection between an ASIC, a large-scale memory and an FPGA or an effpga, thereby avoiding simultaneous generation of multiple sets of IO interfaces and power consumption overhead (as shown in fig. 1a. am1 and 1a. am3) on the FPGA or the effpga with independent memory access, but reducing interconnection between the ASIC and the FPGA or the effpga and reducing memory access efficiency.

SUMMERY OF THE UTILITY MODEL

The utility model provides an integrated chip which can improve the memory access efficiency and reduce the power consumption.

In order to solve the technical problems, the utility model provides a technical scheme that: providing an integrated chip comprising: a first logic component, the first logic component comprising: a first programmable gate array assembly comprising at least one first programmable gate array component; a first application specific integrated circuit array component, the first application specific integrated circuit array component and the at least one first programmable gate array component being located on the same layer; a first interface module including a first bonding lead-out region; the first application specific integrated circuit array component and at least one first programmable gate array component are connected with the first interface module through the internal metal layer; the first memory array component is provided with a second bonding lead-out region, and the second bonding lead-out region and the first bonding lead-out region form three-dimensional heterogeneous integrated interconnection so as to connect the programmable gate array combination, the first application specific integrated circuit array component and interconnection signals on the first memory array component together.

The integrated chip has the beneficial effects that the integrated chip is different from the prior art, and the first logic assembly and the first storage array assembly are bonded together through the first bonding lead-out area and the second bonding lead-out area of the first interface module. Wherein the first logic assembly comprises a first programmable gate array assembly and a first application specific integrated circuit array assembly, and the first interface module is located outside the first programmable gate array assembly. The high-density near memory access interconnection of the programmable gate array and the memory array is realized through a three-dimensional heterogeneous integrated structure, and the purposes of high bandwidth and low power consumption of memory access are realized.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:

FIGS. 1a and 1b are schematic structural diagrams of an integrated chip in the prior art;

FIG. 2 is a schematic structural diagram of a first embodiment of an integrated chip according to the present invention;

FIG. 3 is a schematic diagram of a first programmable gate array assembly according to the present invention;

FIG. 4 is a schematic diagram of a memory access structure of the first programmable gate array assembly of FIG. 2 to the first memory array assembly;

FIG. 5 is a schematic structural diagram of a second embodiment of an integrated chip according to the present invention;

FIG. 6 is a schematic diagram of the first programmable gate array assembly and the second programmable gate array assembly of FIG. 5 showing the shared memory access of the first memory array assembly;

FIG. 7 is a schematic diagram of the first programmable gate array assembly and the second programmable gate array assembly of FIG. 5 with independent memory accesses to the first memory array assembly;

FIG. 8 is a schematic structural diagram of a third embodiment of an integrated chip according to the present invention;

FIG. 9 is a block diagram illustrating the shared memory access of the first programmable gate array assembly to the first memory array assembly and the second memory array assembly of FIG. 8;

FIG. 10 is a schematic diagram of the independent memory access of the first programmable gate array assembly of FIG. 8 to the first memory array assembly and the second memory array assembly;

FIG. 11 is a diagram illustrating a fourth embodiment of an integrated chip according to the present invention;

FIG. 12 is a block diagram illustrating the shared memory access of the first programmable gate array assembly to the first memory array assembly and the second memory array assembly of FIG. 11;

FIG. 13 is a schematic diagram of the independent memory access of the first programmable gate array assembly of FIG. 11 to the first memory array assembly and the second memory array assembly;

FIG. 14 is a schematic diagram of the structure of a programmable routing network and programmable logic blocks;

fig. 15 is a schematic diagram of a three-dimensional heterogeneous integrated structure between the

functional elements

210, 220, 230.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 2 is a schematic structural diagram of an integrated chip according to a first embodiment of the utility model. Specifically, the integrated chip includes a first logic assembly 100 and a first memory array assembly 2. In the present application, the first logic assembly 100 and the first memory array assembly 2 are integrated by bonding in a three-dimensional heterogeneous integration manner. Thereby enabling high bandwidth, low power interconnect of the integrated chip.

Specifically, as shown in fig. 2, the first logic assembly 100 includes a first programmable gate array assembly 1, a first asic array assembly 10, and a first interface module 11. In the present embodiment, the first programmable gate array assembly 1 includes at least one first programmable gate array component, and the first programmable gate array assembly 1 includes two first programmable

gate array components

131 and 132 as an example for explanation. Specifically, the first asic array assembly 10 is located at the same layer as the first programmable gate array assembly 131 and the first programmable gate array assembly 132. The first interface module 11 includes and interconnects a first bond lead out region 111. The first asic array assembly 10, the first programmable gate array assembly 131, and the first programmable gate array assembly 132 are connected to the first interface module 11 through the chip internal metal layer.

The first programmable gate array assembly 131 and the first programmable gate array assembly 132 include: part or all of programmable function modules such as a Logic unit LAB (Logic Array Block)/CLB (configurable Logic Block), a storage unit BRAM (Block Random Access Memory, BRAM), a multiplication unit DSP (digital Signal processor), a multiply accumulation unit MAC (multiply Acculate) and a user unit for realizing a customized calculation function are combined randomly to realize general programmable processing. The first programmable gate array component 131 and the first programmable gate array component 132 contain a programmable routing network therein, which broadly interconnects the first programmable gate array component 131 and the first programmable gate array component 132 through internal metal layers of the chip, providing high bandwidth, programmable interconnections between the first programmable gate array component 131 and the first programmable gate array component 132.

The first asic array assembly 10 includes one or more arbitrary combinations of multiply-add calculation arrays, systolic processor arrays, hash calculation arrays, various encoder arrays, machine learning dedicated layer arrays, search function arrays, image/video processing arrays, and hard core arithmetic/processing units such as CPUs and MCUs. The first asic array assembly 10 has limited or no programmability, and is applied to compute/process acceleration for specific requirements, with much higher compute/process density than any programmable functional module, significantly increasing the compute/process density of the ic. The first memory array assembly 2 includes and interconnects a second bond lead out region 12. The second bonding lead-out area 12 and the first bonding lead-out area 111 form a three-dimensional heterogeneous integrated interconnection, so as to connect the first programmable gate array assembly 131, the first programmable gate array assembly 132 and the first application specific integrated circuit array assembly 10 in the programmable gate array assembly 1 with the first memory array assembly 2. And further, a programmable storage and calculation integrated structure with high bandwidth and low power consumption of the integrated chip is realized.

In an embodiment, the first Memory array component 2 may be a DRAM (Dynamic Random Access Memory), in another embodiment, the first Memory array component 2 may also be a Static Random Access Memory (SRAM), and in consideration of the iterative development of the technology, the first Memory array component 2 may also be other types of memories or a combination of SRAMs and other types of memories, such as a Flash Memory (Flash), a resistance Random Access Memory (RRAM or ReRAM), a magnetoresistive Memory (MRAM), a ferroelectric Memory (FeRAM), an oxide resistive Memory (OxRAM), a bridge Memory (CBRAM), a Phase Change Memory (PCM), a spin transfer torque Memory (STT-MRAM), an electrically erasable Memory (EEPROM), and the like, which are not limited in particular. The memory has respective characteristic advantages, and may require a memory controller as a memory access interface, where the memory controller is used to implement functions such as a physical interface, data read/write, data buffering, data prefetching, data refreshing, and data block remapping, and is not particularly limited.

Specifically, in the present application, the first interface module 11 is located outside the first programmable gate array assembly 1 and the first asic array assembly 10. The first interface module 11 is provided with interface routing units 137, which are extended from the programmable routing network, near the first programmable gate array component 131 and both sides of the first programmable gate array component 132, and it can be understood that, if the first programmable gate array assembly 1 includes only one first programmable gate array component, then only one side of the first interface module 11 near the one first programmable gate array component has the interface routing unit 137. And the programmable routing network interconnecting the programmable function modules in this one first programmable gate array assembly is connected to the adjacent interface routing unit 137 through the chip internal metal layers. In this embodiment, two sides of the first interface module 11 are respectively provided with a first programmable gate array component, and then both sides of the first interface module 11 close to the first programmable gate array component 131 and the first programmable gate array component 132 are respectively provided with an interface routing unit 137. The programmable function modules of the first programmable gate array component 131 and the first programmable gate array component 132 are led out to one side of the first programmable gate array component 131 and the first programmable gate array component 132 close to the first interface module 11 through the metal layer inside the chip and are connected with the interface routing unit 137. In this embodiment, the first interface module 11 is disposed outside the first programmable gate array component 131 and the first programmable gate array component 132, and the programmable function modules of the first programmable gate array component 131 and the first programmable gate array component 132 need to be connected to the interface routing unit 137 of the first interface module 11 through a metal layer inside a chip. And further, the first interface module 11 also forms a three-dimensional heterogeneous integrated interconnection with the second bonding lead-out region 12 of the first memory array assembly 2 through the first bonding lead-out region 111, and the first asic array assembly 10 is connected with the first interface module 11 through a chip internal metal layer. Therefore, the programmable static memory integrated structure with high bandwidth and low power consumption of the integrated chip is realized. Specifically, the first programmable gate array assembly 1, the first application specific integrated circuit array component 10 and the first storage array component 2 are interconnected in a three-dimensional heterogeneous integrated interconnection mode, so that the interconnection density is greatly improved; and the interconnection distribution parameters are reduced, namely, the interconnection speed is increased, and the interconnection power consumption is reduced. The first programmable gate array component can realize general calculation through reconstruction, and further realize system universality.

Different from the existing interconnection of the IO interface and/or the IO circuit, the first asic array module 10, the first programmable gate array module 131, and the first programmable gate array module 132 are connected to the first interface module 11 through the internal metal layer of the chip, and do not need the functions of driving, external level boosting (during output), external level reducing (during input), tri-state controller, ESD protection and surge protection circuit provided by the IO circuit in the prior art, and do not need to be interconnected through the IO interface and/or the IO circuit in the prior art, and the interconnection of the internal high-density metal layer of the chip is directly established.

The first programmable gate array component 131 and the first programmable gate array component 132 do not need to lead out interconnection lines through an IO interface and/or an IO circuit of the programmable gate array, but extend the extended interface routing unit through the programmable routing network, extend the programmable routing network widely interconnected with the programmable gate array component, extend and interconnect to the first asic array component 10 and the first interface module 11. Thereby extending the programmable routing network of the programmable gate array assembly to the first asic array assembly 10 and forming a wide interconnection, and scheduling high density computing units on the first asic array assembly 10 by the internal resources of the programmable gate array assembly in a high bandwidth, programmable manner to achieve high density, programmable computing/processing; thereby extending the programmable routing network of programmable gate array components to the first interface module 11 and forming a wide interconnect, the first interface module 11 is accessed in a high bandwidth, programmable manner by the internal resources of the programmable gate array components. Further, the first programmable gate array component 131 and/or the first programmable gate array component 132 extends the programmable routing network of the programmable resources extensively interconnected inside the programmable gate array component through the interface routing unit 137, extends and interconnects to the first interface module 11, and further interconnects to the mass storage array on the first storage array component 2 through three-dimensional heterogeneous integration. The three-dimensional heterogeneous integrated interconnection is realized in a three-dimensional device, functions of driving, external level boosting (output), external level reducing (input), a tri-state controller, an electrostatic protection ESD (electro-static discharge) and a surge protection circuit and the like provided by an IO circuit in the prior art are not needed, interconnection of an IO interface and/or an IO circuit in the prior art is not needed, and cross-chip high-density metal layer interconnection is directly established. Three-dimensional heterogeneous integrated interconnection, namely, the stacked interconnection among chips is realized through a semiconductor metal manufacturing process, so that the physical and electrical parameters of interconnection lines among the chips follow the characteristics of the semiconductor manufacturing process, the use of holes, interconnection lines and IO structures is reduced, and the interconnection density and the interconnection speed among the chips are increased; meanwhile, the three-dimensional heterogeneous integrated interconnection does not pass through the traditional IO structure, and the interconnection distance is short, so that the communication power consumption between chips is reduced; and further, the integration level and the interconnection frequency of the integrated chip are improved, and the interconnection power consumption is reduced. The programmable routing network of the programmable gate array component extends to the large-capacity storage array on the first storage array component 2 across the chip and forms wide interconnection, and the programmable function module of the programmable gate array component realizes three-dimensional heterogeneous integrated storage access of the large-capacity storage array on the first storage array component 2 in a high-bandwidth and programmable mode. The three-dimensional integrated chip has the large capacity of an external memory and the key advantages of large bit width and high bandwidth of a similar programmable gate array component extending a programmable routing network interconnection memory unit BRAM (the prior art has small capacity) through a memory routing unit, and fundamentally breaks through the bottleneck of expanding the IO number, the bottleneck of memory access bandwidth and the bottleneck of memory access power consumption of a large-scale memory of the programmable gate array component in the prior art.

In one embodiment, as shown in fig. 3, the programmable functional modules of the first programmable gate array component 131 and/or the first programmable gate array component 132 include: a programmable Logic Block (Logic Array Block, LAB/Configurable Logic Block, CLB)133, a storage Block (Block Random Access Memory, BRAM)134, a multiplication unit (Digital Signal processor) 135, a multiplication and addition unit (multi Access, MAC)138, and a user unit for implementing a customized computing function. It should be noted that the multiplication unit 135 is not a digital signal processor chip, but is an embedded programmable multiplication unit.

In this embodiment, the first bonding lead-out region 111 is a cross-chip interconnection resource in the first programmable gate array assembly 1, that is, the first programmable gate array assembly 1 is directly interconnected to the first storage array component 2 through a cross-chip metal layer, so that storage access is realized, and interconnection between an IO interface of the first programmable gate array assembly 1 and the first storage array component 2 is avoided, thereby achieving the purposes of high bandwidth and low power consumption, and having the advantages of high density and low distribution parameters.

In one embodiment, as shown in FIG. 3, the storage unit 134 is connected to the logic unit 133 through the storage routing unit 136, and further connected to the entire programmable routing network. The first interface module 11 interconnecting the mass storage arrays across the chip is connected to the logic unit 133 through the interface routing unit 137, which in turn is connected to the entire programmable routing network.

As shown in fig. 3, the integrated chip of this embodiment is designed with an interface routing unit 137, the interface routing unit 137 is widely interconnected with the programmable routing network inside the programmable function module of the first programmable gate array combination 1, and the interface routing unit 137 is directly connected to a first interface module (the first interface module 11 of figure 2) external to the first programmable gate array assembly 1, and further connected with the first memory array component 2 through the first interface module to realize the programmable function module of the first programmable gate array combination 1, through the extensive extension of the programmable routing network, into the mass storage array on the first storage array assembly 2, the programmable function module of the first programmable gate array assembly 1 is established to have programmable, large-capacity, high-bandwidth and low-power consumption memory access to the large-capacity memory array on the first memory array component 2.

The integrated chip of this embodiment implements storage access of the first programmable gate array assembly 1 and the first asic array assembly 10 to the first storage array assembly 2, and is different from a mode in which the first programmable gate array assembly 1 and the first asic array assembly 10 are connected to the first storage array assembly 2 through an IO interface in the conventional technology.

In an embodiment, a global bus, such as NOC AXI AHB, may also be provided on the first programmable gate array combination 1, and the programmable logic cross-region memory access on the first programmable gate array combination 1 may be implemented. Specifically, the global bus may be striped near the first interface module 11, or may also be disposed at other storage access associated positions, which is not limited in particular.

In one embodiment, the first asic array assembly 10 includes one or more arbitrary combinations of multiply-add computing arrays, systolic processor arrays, hash computing arrays, various encoder arrays, machine learning specialized layer arrays, search function arrays, image/video processing arrays, and hard core computing/processing units such as CPUs and MCUs. The first asic array assembly 10 has limited or no programmability, and is applied to compute/process acceleration for specific requirements, with much higher compute/process density than any programmable functional module, significantly increasing the compute/process density of the ic. The first asic array assembly 10 may further configure the configuration circuit and the phase-locked loop of the first fpga group 1, which are a programmable gate array configuration module and a programmable clock module, respectively, independent of the first fpga group 1. In one embodiment, the programmable function modules in the programmable gate array assembly are arranged in stripes, and the function modules in the asic assembly are also arranged in stripes, so as to improve the scheduling efficiency of the programmable function modules.

In the integrated chip, adjacent components are interconnected through three-dimensional heterogeneous integration, high-density metal layer interconnection in the chip is established layer by layer, components in the integrated chip are designed and packaged in the same integrated chip in a stacked mode, functions such as driving, external level boosting (during output), external level voltage reduction (during input), a tri-state controller, electrostatic protection ESD and surge protection circuits and the like provided by an IO circuit in the prior art are not needed, and cross-component high-density metal layer interconnection is directly established without interconnection through an IO interface and/or an IO circuit in the prior art. Therefore, the use of IO structures of the programmable gate array assembly is reduced, and the interconnection density and the interconnection speed of the application-specific integrated circuit assembly, the programmable gate array assembly and the storage array assembly are increased; meanwhile, the three-dimensional heterogeneous integrated interconnection does not pass through the traditional IO structure, and the interconnection distance is short, so that the communication power consumption between chips is reduced; and furthermore, the integration level of the integrated chip and the interconnection frequency of the application specific integrated circuit component, the programmable gate array component and the memory array component are improved, and the interconnection power consumption is reduced. Therefore, the programmable routing network of the programmable resources widely interconnected on the programmable gate array component extends to the large-capacity storage array on the storage chip across the chip and forms wide interconnection, and the three-dimensional heterogeneous integrated storage access of the programmable resources to the large-capacity storage array on the storage chip in a high-bandwidth and programmable mode is realized. The multilayer chip has the large capacity of an external memory and the key advantages of large bit width and high bandwidth of a similar programmable gate array component which is interconnected with a memory block BRAM (in the prior art, the capacity is small) through a programmable routing network. The bottleneck of IO quantity, the bottleneck of memory access bandwidth and the bottleneck of memory access power consumption of the large-scale memory expanded by the programmable gate array chip in the prior art are fundamentally broken through.

In one embodiment, the integrated chip further comprises: a storage control unit 113, wherein the storage control unit 113 may be disposed on the first interface module 11, as shown in fig. 2; or in another embodiment, the storage control unit 113 may also be disposed outside the first interface module 11 and near the first interface module 11, for example, the storage control unit 113 is disposed on the first asic assembly 10, or the storage control unit 113 is disposed on the first storage array assembly 2. The memory control unit 113 is used to control memory access of the first programmable gate array assembly 1 to the first memory array assembly 2, and the first memory control unit 113 may also control memory access of the first asic assembly 10 to the first memory array assembly 2 (interconnect is established by the programmable routing network in the programmable gate array assembly 1). The integrated chip of the embodiment can avoid interconnection through a physical IO interface and/or a physical IO circuit, so IO resources are saved, interconnection density far higher than the IO interface is provided, memory access bandwidth is improved, and memory access power consumption is reduced. High density, close proximity interconnection of signals internal to the first programmable gate array assembly 1 and the first asic array assembly 10 to the first memory array assembly 2 is achieved.

In a preferred embodiment, the storage control unit 113 is provided on the first interface module 11. This is advantageous for data flow since both the programmable gate array components and the application specific integrated circuit components need to access the memory array components through the first interface module 11. In a preferred embodiment, the memory control unit is disposed on an ASIC assembly, which can achieve higher density and speed due to the superior process performance of ASIC assemblies over memory array assemblies. In a preferred embodiment, the memory control unit is disposed on the memory array device, which can reduce the implementation cost and relatively increase the density of the asic device because the memory array device process is cheaper per unit area than the asic device.

In an embodiment, a physical layer is further disposed on the integrated chip for implementing level translation between the first logic component 100 and the first memory array component 2, because the three-dimensional heterogeneous integration between the first logic component 100 and the first memory array component 2 is an intra-chip metal-layer cross-chip interconnection, no IO circuit performs level translation, and when core voltages of the first logic component 100 and the first memory array component 2 are different, the physical layer needs to be disposed for level translation. The physical layer may be provided on the first logic component 100, e.g. on or near the first interface module 11; or may be disposed on the first storage array assembly 2, which is not limited in particular.

In the present application, physical and electrical parameters of the three-dimensional heterogeneous integrated interconnection between the first interface module 11 and the first memory array component 2 follow the process characteristics of the semiconductor process, and compared with the traditional PCB or 2.5D package, the interconnection number (memory access bandwidth) between the first programmable gate array assembly 1 and the first memory array component 2 is increased by 4 to 2 orders of magnitude. Compared with the traditional PCB or 2.5D packaging, the direct interconnection of the first programmable gate array assembly 1 and the first storage array component 2 is realized, and the interconnection distance is shorter without an IO interface, so that the power consumption expense of storage access is obviously reduced. A distributed and decentralized memory access architecture of the first programmable gate array combination 1 and the first memory array component 2 is formed, so that the nearby and independent memory access of the programmable function modules on the first programmable gate array combination 1 is realized, and the memory access conflict and the efficiency reduction of a traditional shared bus are avoided; the IO overhead for interconnecting the first programmable gate array assembly 1 with the first memory array component 2 in the conventional art is saved.

It should be noted that, in this embodiment, in the same layer, the number of the first interface modules 11 is at least two, and at least two first interface modules 11 are arranged at intervals with the first programmable gate array component.

In one embodiment of the present application, as shown in FIG. 4, FIG. 4 provides a memory access structure for a first programmable gate array assembly to a first memory array assembly 2. Specifically, as shown in fig. 4, the first interface module is connected to only one first programmable gate array component. In this embodiment, a case where the memory control unit is disposed on the first interface module is taken as an example for description. Specifically, the storage control unit H21 is disposed on the first interface module H17. The first memory array module 2 includes a memory cell G13 thereon, a second bond pad out region G14 is provided on the memory cell G13, a memory control unit H21 is connected to the first bond pad out region H19, and a first bond pad out region H19 is connected to the second bond pad out region G14 on the first memory array module 2.

Furthermore, a programmable logic unit K23 is arranged on the first programmable gate array component, and the programmable logic unit K23 is connected with a storage control unit H21 through an interface routing unit H22. The programmable logic unit K23 derives logic signals, and the storage control unit H21 controls the first programmable gate array assembly to perform storage access to the first storage array assembly 2 based on the logic signals.

Further, if a plurality of first programmable gate array elements are connected to the first interface module 11 in the same layer, the plurality of first programmable gate array elements may share the memory control unit H21 to implement memory access to the first memory array element 2. It will be appreciated that, in order to avoid access conflicts, the memory control unit H21 may selectively select one of the first programmable gate array elements to perform memory access to the first memory array element 2 in a time-sharing manner. In another embodiment, two memory control units H21 may be further disposed on the first interface module 11, wherein one memory control unit H21 controls one programmable gate array component to perform memory access to the first memory array component 2, and the other memory control unit H21 controls the other programmable gate array component to perform memory access to the first memory array component 2. It should be noted that, if the two memory control units H21 are capable of controlling all the memory cells of the first memory array assembly 2, when the two first programmable gate array assemblies access the same memory cell of the first memory array assembly 2, the two memory control units H21 selectively select one of the first programmable gate array assemblies to perform memory access on the first memory array assembly 2 in a time-sharing manner. It is understood that if two memory control units H21 control different memory cells of the first memory array assembly 2 respectively, then two first programmable gate array assemblies access different memory cells of the first memory array assembly 2, and the two different memory cells are controlled by two memory control units H21 respectively, then two memory control units H21 can control two first programmable gate array assemblies to access different memory cells of the first memory array assembly 2 simultaneously.

It is understood that the two first programmable gate array components described above may be replaced by the first asic array component 10, that is, the first interface module 11 is connected to a first programmable gate array component and a first asic array component 10, and the first programmable gate array component and the first asic array component 10 may also share the same memory control unit H21 to implement time-sharing memory access to the first memory array component 2 according to the method described above. Alternatively, according to the above method, different storage control units H21 may be used to implement time-sharing storage access or simultaneous storage access to the first storage array assembly 2, and the specific process is the same as above, and is not described herein again.

In the present application, the number and the positions of the first logic elements 100 and the first memory array elements 2 may be set according to the requirement, as shown in fig. 5, fig. 5 is a schematic structural diagram of a second embodiment of the integrated chip of the present invention. Compared with the first embodiment shown in fig. 2, the difference is that the integrated chip of this embodiment further includes: a second logic component 200. The second logic element 200 is disposed on a side of the first logic element 100 remote from the first memory array element 2. Specifically, the second logic assembly 200 includes a second programmable gate array assembly 3, a second application specific integrated circuit array assembly 30, a second interface module 31, and an interface routing unit 312. In the present embodiment, the second programmable gate array assembly 3 includes at least one second programmable gate array component, and the second programmable gate array assembly 3 includes two second programmable

gate array components

341 and 342 as an example for explanation. Specifically, the second asic array component 30 is located in the same layer as the second programmable gate array component 341 and the second programmable gate array component 342, and is interconnected with the programmable routing network in the second programmable gate array component 341 and/or the second programmable gate array component 342; the interface routing unit 312 is an extension of the programmable routing network in the second programmable gate array component 341 and/or the second programmable gate array component 342 to establish an interconnection, and the second interface module 31 establishes an interconnection with the programmable routing network in the second programmable gate array component 341 and/or the second programmable gate array component 342 through the interface routing unit 312. The second interface module 31 includes a third bonded lead-out region 311, in this embodiment, the first interface module 11 further includes a fourth bonded lead-out region 32, and the third bonded lead-out region 311 and the fourth bonded lead-out region 32 form a three-dimensional heterogeneous integrated interconnection; the interface routing unit 312 is an interconnection resource of the second programmable gate array component 341 and/or the second programmable gate array component 342, and is connected to the first interface module 11 on the first logic component 100 across the chip through the interface routing unit 312 and the second interface module 31, and the third bonding lead-out area 311 and the fourth bonding lead-out area 32, and further connected to the large-capacity storage array on the first storage array component 2; the programmable function module of the second programmable gate array assembly 3 is established to have programmable, large-capacity, high-bandwidth and low-power consumption storage access to the large-capacity storage array on the first storage array component 2.

In the integrated chip, adjacent components are interconnected through three-dimensional heterogeneous integration, high-density metal layer interconnection in the chip is established layer by layer, components in the integrated chip are designed and packaged in the same integrated chip in a stacked mode, functions such as driving, external level boosting (during output), external level voltage reduction (during input), a tri-state controller, electrostatic protection ESD and surge protection circuits and the like provided by an IO circuit in the prior art are not needed, and cross-component high-density metal layer interconnection is directly established without interconnection through an IO interface and/or an IO circuit in the prior art. Therefore, the use of IO structures of the programmable gate array assembly is reduced, and the interconnection density and the interconnection speed of the programmable gate array assembly and the storage array assembly are increased; meanwhile, the three-dimensional heterogeneous integrated interconnection does not pass through the traditional IO structure, and the interconnection distance is short, so that the communication power consumption between chips is reduced; and furthermore, the integration level of the integrated chip and the interconnection frequency of the programmable gate array component and the memory array component are improved, and the interconnection power consumption is reduced. Therefore, the programmable routing network of the programmable resources widely interconnected on the programmable gate array component extends to the large-capacity storage array on the storage chip across the chip and forms wide interconnection, and the three-dimensional heterogeneous integrated storage access of the programmable resources to the large-capacity storage array on the storage chip in a high-bandwidth and programmable mode is realized. The multilayer chip has the large capacity of an external memory and the key advantages of large bit width and high bandwidth of a similar programmable gate array component which is interconnected with a memory block BRAM (in the prior art, the capacity is small) through a programmable routing network. The bottleneck of IO quantity, the bottleneck of memory access bandwidth and the bottleneck of memory access power consumption of the large-scale memory expanded by the programmable gate array chip in the prior art are fundamentally broken through.

Compared with the first embodiment shown in fig. 2, the integrated chip of the present embodiment can further improve the computation density, which is beneficial to more complex reconfigurable computation. In combination with the integrated chip of the embodiment, more programmable gate array components or more application specific integrated circuit array components can be arranged according to requirements, so as to improve the density of the programmable gate array components and the application specific integrated circuit array components in the integrated chip.

The second logic element 200 shown in this embodiment is the same as the first logic element 100, and is not described herein again.

The integrated chip of the present embodiment is provided with two layers of logic components, i.e. the second logic component 200 and the first logic component 100. Specifically, the integrated chip of the present embodiment includes two layers of asic array components, such as a first asic array component 10 and a second asic array component 30; the programmable gate array device comprises two layers of programmable gate array combinations, such as a first programmable gate array combination 1 and a second programmable gate array combination 3.

In this embodiment, the second programmable array assembly 3 can implement storage access to the first storage array assembly 2 through the first interface module 11 and the second interface module 31. The second asic assembly 30 realizes memory access to the first memory array assembly 2 through the second interface module 31 and the first interface module 11.

In an embodiment, the third bonding lead-out region 311 is a cross-chip interconnection resource in the second programmable gate array assembly 3, that is, the second programmable gate array assembly 3 establishes a metal layer direct interconnection with the first interface module 11 through the cross-chip interconnection resource, and further realizes interconnection with the first storage array component 2 through an interconnection resource (that is, the first bonding lead-out region 111) in the first programmable gate array assembly 1, so as to realize storage access, avoid interconnection with the first storage array component 2 by using an IO interface of the second programmable gate array assembly 3, and further realize the purposes of high bandwidth and low power consumption.

It should be noted that the second programmable gate array combination 3 may also be different from the first programmable gate array combination 1, and it may set different functions and/or different numbers of functional modules according to actual needs. For example, in one embodiment, the functional modules of the second programmable gate array combination 3 include, but are not limited to, any combination of programmable logic modules, embedded memory units, and embedded multiplication units. The first asic array assembly 10 and the second asic array assembly 30 include asic implemented hard core arithmetic/Processing units (Processing elements), such as one or more arbitrary combinations of multiply-add arithmetic arrays, systolic processor arrays, hash arithmetic arrays, various encoder arrays, machine learning dedicated layer arrays, search function arrays, image/video Processing arrays, and CPU and MCU. The first asic array element 10 and the second asic array element 30 have limited or no programmability, and are applied to compute/process acceleration for specific requirements, with much higher compute/process density, significantly increasing the compute/process density of the ic.

In this embodiment, the first interface module 11 is connected to the first memory array module 2, and is connected to the first programmable gate array assembly 1, and the first asic array module 10. The first interface module 11 provides memory access channels for the first programmable gate array assembly 1 to the first memory array assembly 2 and also provides memory access channels for the first asic array assembly 10 to the first memory array assembly 2. The second interface module 31 is connected to the first interface module 11 of the first programmable gate array assembly 1 and to the second programmable gate array sets and 3 and the second asic array block 30. The second interface module 31 and the first interface module 11 provide a memory access channel of the second programmable gate array assembly 3 to the first memory array assembly 2, and also provide a memory access channel of the second asic array assembly 30 to the first memory array assembly 2.

In this embodiment, the first logic element 100 and the second logic element 200 share the same memory control unit to access the same memory location of the first memory array element. Specifically, the first programmable gate array combination 1/the first asic array assembly 10 and the second programmable gate array combination 3/the second asic array assembly 30 share the same memory control unit 113 to access the same memory location of the first memory array assembly 2, so as to implement shared memory access. In the present embodiment, the first programmable gate array assembly 1 and the second programmable gate array assembly 3 share the same memory control unit 113 to access the same memory array of the first memory array assembly 2, so as to implement shared memory access. Specifically, the storage control unit 113 may be disposed on the first interface module 11; the storage control unit 113 may also be provided on the second interface module 31; alternatively, the storage control unit 113 may also be disposed on the first storage array assembly 2, which is not limited specifically.

Specifically, in an embodiment, the first logic assembly 100 further includes a first programmable logic unit, and in a specific embodiment, the first programmable logic unit is disposed on the first programmable gate array assembly 131 and/or the first programmable gate array assembly 132, and the first programmable logic unit is connected to the storage control unit 113 and derives the first logic signal. The second programmable gate array assembly 3 includes a second programmable logic unit, specifically, the second programmable logic unit is disposed on the second programmable gate array component 341 and/or the second programmable gate array component 342, and the second programmable logic unit is connected to the storage control unit 113 and derives a second logic signal. The memory control unit 113 selects the first programmable gate array combination 1 to access the first memory array cell 2 or selects the second programmable gate array combination 3 to access the first memory array cell 2 based on the first logic signal and the second logic signal.

Specifically, as shown in fig. 6, fig. 6 illustrates an example in which the first programmable gate array assembly 1 includes a first programmable gate array component, and the second programmable gate array assembly 3 includes a second programmable gate array component. Wherein, the storage control unit H21 is provided at the first interface module H17. Specifically, the first memory array unit 2 includes a memory array unit G13 thereon, the second bond lead-out region G14 is disposed on the memory array unit G13, the first bond lead-out region H19 is disposed on the first interface module H17, and the first bond lead-out region H19 is in bonding connection with the second bond lead-out region G14. The memory control unit H21 is provided on the first interface module H17, and the memory control unit H21 is connected to the first bond lead-out region H19. The first interface module H17 is further provided with a fourth bonding lead-out region H24, and the fourth bonding lead-out region H24 is connected to the memory control unit H21. The second interface module I27 is provided with a third bonding lead-out area I28, and the third bonding lead-out area I28 is connected with a fourth bonding lead-out area H24. Further, in this embodiment, the first programmable gate array assembly further includes a first programmable logic unit H23, and the first programmable logic unit H23 is connected to the memory control unit H21. The second programmable gate array component also comprises a second programmable logic unit I32, a second programmable logic unit I32 and a third bond lead-out area I28.

For example, in an embodiment, when the first programmable gate array device needs to access the first memory array device 2, the first programmable logic unit H23 outputs the first logic signal to the memory control unit H21, and at this time, the memory control unit H21 controls the first programmable gate array device to access the memory cell G13 on the first memory array device 2 through the first bond extraction region H19 and the second bond extraction region G14 based on the first logic signal. When the second programmable gate array component needs to access the first memory array component 2, the second programmable logic unit I32 extracts the second logic signal, and the third bonded extraction area I28 and the fourth bonded extraction area H24 are transmitted to the memory control unit H21. At this time, the memory control unit H21 controls the second programmable gate array assembly to access the memory cell G13 on the first memory array assembly 2 through the third bond lead-out region I28 and the fourth bond lead-out region H24 based on the second logic signal. Therefore, the memory control unit selects the first programmable gate array component to access the first memory array component 2 or the second programmable gate array component to access the first memory array component 2 based on the first logic signal and the second logic signal.

It should be noted that the first programmable gate array component and the second programmable gate array component may be replaced by a first asic array component and a second asic array component.

Furthermore, the number of the first programmable gate array component and the second programmable gate array component can be multiple. The memory access of the plurality of first programmable gate array components and the plurality of second programmable gate array components to the memory array components is determined according to the number of the memory control units, which is specifically described in fig. 4 above, and is not described herein again.

In this embodiment, only one storage control unit is designed, and the storage control unit may be located on or near the first interface module H17, may be located on or near the second interface module I27, and may be located on the first storage array assembly 2, which is not limited specifically. The memory unit G13 on the first memory array assembly 2 is connected to the memory control unit H21 through the second bond lead-out region G14 and the first bond lead-out region H19, and the memory control unit H21 can be directly connected to two sets of memory access interfaces (e.g., H19 and H24 in fig. 5) to control the multiple sets of programmable gate array assemblies to directly access through the interfaces.

In one embodiment, the first programmable logic unit H23 and the second programmable logic unit I32 include any combination of programmable logic blocks, memory blocks, multiplication units, multiply-accumulate units, and hard core operation/processing units, among others. The first programmable logic cell H23 derives a first logic signal and the second programmable logic cell I32 derives a second logic signal. The memory access interface of the memory control unit H21 is switched to the bonding direction of the first bonding lead-out area H19 and the second bonding lead-out area G14 or the bonding direction of the fourth bonding lead-out area H24 and the third bonding lead-out area I28 by the memory control unit H21 according to the first logic signal and the second logic signal, and the first programmable logic unit H23 and the second programmable logic unit I32 are used in a time sharing mode, so that shared memory access is achieved.

The first asic array assembly 10 and the second asic array assembly 30 share the same memory control unit 113 to access the same memory cell of the first memory array assembly 2, so as to implement the shared memory access in the same way as the first fpga assembly 1 and the second fpga assembly 3 share the shared memory access, which is not described herein again.

In this embodiment, the third bond lead-out area I28 is connected to the interface routing unit I30. And the interface routing unit I30 connects the second programmable logic unit I32 to the fourth bonded lead out region H24.

In this embodiment, the memory control unit is shared to implement memory access of the first programmable logic unit H23 and the second programmable logic unit I32 to the same address space of the mass storage array on the first storage array assembly 2, that is, shared memory access, which is convenient for data sharing and synchronization between the first programmable logic unit H23 and the second programmable logic unit I32, and the occupied area is small.

In another embodiment, the first programmable gate array combination 1/first application specific integrated circuit array assembly 10 in the first logic assembly 100 and the second programmable gate array combination 3/second application specific integrated circuit array assembly 30 in the second logic assembly 200 access the memory cells of the first memory array assembly 2 using separate memory control cells, respectively. Specifically, the integrated chip includes a first memory control unit and a second memory control unit, and the first programmable gate array combination 1/the first asic unit 10 accesses the memory cells of the first memory array unit 2 by using the first memory control unit. The second programmable gate array combination 3/second asic unit 30 accesses the memory cells of the first memory array unit 2 using a second memory control unit.

In this embodiment, the second storage control unit is disposed on or near the second interface module 31, and the first storage control unit is disposed on or near the first interface module 11. In this embodiment, the first logic assembly 100 further includes a first programmable logic unit, specifically, the first programmable logic unit is disposed on the first programmable gate array assembly 1, and the first programmable logic unit is connected to the storage control unit to extract the first logic signal. The second logic component 200 further comprises: and a second programmable logic unit, specifically, the second programmable logic unit is arranged on the second programmable gate array assembly 3, and the second programmable logic unit is connected with the storage control unit to extract a second logic signal.

When the first programmable gate array component and the second programmable gate array component access the same memory cell simultaneously in response to the first memory control unit and the second memory control unit both controlling all the memory cells of the first memory array component 2, the first memory control unit controls the first programmable gate array component to access the memory cell at the first time based on the first logic signal; the second memory control unit controls the second programmable gate array assembly to access the memory unit at a second time based on the second logic signal. In response to the first and second memory control units controlling different memory cells of the first memory array assembly, respectively, the first and second memory control units simultaneously control the first and second programmable gate array assemblies to access different memory cells of the first memory array assembly 2.

Specifically, in this embodiment, if the first memory control unit and the second memory control unit both control all the memory cells of the first memory array assembly 2, and if the first programmable gate array assembly and the second programmable gate array assembly access the same memory cell at the same time, the first memory control unit and the second memory control unit respectively control the first programmable gate array assembly and the second programmable gate array assembly to access the memory cell. Specifically, the first storage control unit controls the first programmable gate array component to access the storage unit at a first time based on the first logic signal, and the second storage control unit controls the second programmable gate array component to access the storage unit at a second time based on the second logic signal, so that time-sharing access of different programmable gate arrays to the same storage unit is realized, that is, access conflicts are eliminated.

Specifically, the first logic component 100 may include arbitration logic for memory cells, and the memory control units on the first logic component 100 and the second logic component 200 are selected to be accessed based on the first logic signal and the second logic signal. Specifically, when the memory control unit of the first logic component 100 and the memory control unit of the second logic component 200 respectively access different memory cells of the first memory array component 2 at the same time, since the respective memory control units are independent, the arbitration logic in the memory cell of the first logic component 100 can establish the access of the memory control unit of the first logic component 100 and the memory control unit of the second logic component 200 to the memory cell of the first memory array component 2 at the same time based on the first logic signal and the second logic signal; when the memory control unit of the first logic component 100 and the memory control unit of the second logic component 200 simultaneously access the same area of the memory unit of the first memory array component 2, respectively, the arbitration logic in the memory unit of the first logic component 100 time-divisionally establishes the memory control unit of the first logic component 100 or the memory control unit of the second logic component 200 to access based on the first logic signal and the second logic signal. The arbitration logic for the memory cells in the first logic component 100 may also be provided on the first memory array component 2 or the second logic component 200.

In another embodiment, when the first memory control unit and the second memory control unit respectively control different memory cells of the first memory array assembly, the first memory control unit and the second memory control unit simultaneously control the first programmable gate array assembly and the second programmable gate array assembly to access different memory cells of the first memory array assembly 2.

Specifically, when the first memory control unit of the first programmable gate array assembly and the second memory control unit of the second programmable gate array assembly access different memory cells of the first memory array assembly 2 simultaneously, respectively, since the respective memory control units are independent, the arbitration logic in the memory cell of the first programmable gate array assembly can establish access of the first memory control unit of the first programmable gate array assembly and the second memory control unit of the second programmable gate array assembly to the memory cell of the first memory array assembly 2 simultaneously based on the first logic signal and the second logic signal.

In the embodiment, each logic component is provided with an independent storage access interface, the access bandwidth is highest, and the logic components can be accessed simultaneously when the specific units accessing the storage array are different; when the specific units are the same, conflict occurs, and arbitration and time-sharing access are needed. Specifically, when the first memory control unit and the second memory control unit both control all the memory cells of the first memory array module 2, if the same memory cell is accessed at the same time, time-sharing access is required. When the storage units controlled by the first storage control unit and the second storage control unit are different, time-sharing access is not needed.

In one embodiment, the second storage control unit is disposed on or near the second interface module 31 and the first storage control unit is disposed on or near the first interface module 11. In the present embodiment, the first memory control unit controls the first programmable gate array assembly to access a part of the memory cells of the first memory array assembly 2 based on the first logic signal; the second storage control unit controls the second programmable gate array component to access the rest storage units of the first storage array component 2 based on the second logic signal; the memory cells of the second programmable gate array assembly accessing the first memory array assembly 2 do not overlap with the first programmable gate array assembly access area. The first programmable logic unit utilizes a first memory control unit and the second programmable logic unit utilizes a second memory control unit to independently and simultaneously access different memory cells on the respective corresponding first memory array components 2.

In the embodiment, each logic component is provided with an independent storage access interface, the access bandwidth is highest, and the first storage array component 2 is accessed and divided to different programmable logic units to utilize a storage control unit combination; the concurrent memory access of different programmable logic units is realized, and the memory access efficiency is not reduced due to arbitration and time-sharing access.

Specifically, referring to fig. 7, the first memory array assembly 2 includes a memory array cell G13, wherein two second bond-out regions, i.e., a second bond-out region G14 and a second bond-out region G12, are disposed on the memory array cell G13. Wherein the second bond pad out region G14 is connected to the first bond pad out region H19 on the first interface module H17 on the first programmable gate array assembly 1. The first interface module H17 of the first programmable gate array assembly 1 is provided with a first memory control unit H20, and the first memory control unit H20 is used for controlling the first programmable gate array assembly 1 to access the first memory array assembly 2. Specifically, the first memory control unit H20 is connected to the first bond lead-out region H19. The first programmable gate array assembly 1 is provided with a first programmable logic unit H23, and the first programmable logic unit H23 is connected to the first storage control unit H20 through an interface routing unit H22. When the first programmable gate array assembly 1 accesses the first memory array assembly 2, the first programmable logic unit H23 outputs a first logic signal to the first memory control unit H20, and the first memory control unit H20 controls the first programmable gate array assembly 1 to access a part of the memory cells G13 of the first memory array assembly 2 through the first bonding lead-out region H19 and the second bonding lead-out region G14 based on the first logic signal.

In addition, the second bond lead-out region G12 is connected to the first bond lead-out region H18 on the first interface module H17, and the first bond lead-out region H18 is connected to the third bond lead-out region I28 on the second programmable gate array combination 3. The second programmable gate array combination 3 further comprises a second programmable logic unit I32, and the second programmable logic unit I32 is connected to a second memory control unit I29 on a second interface module I27 of the second programmable gate array combination 3 through an interface routing unit I31. When the second programmable gate array assembly 3 accesses the first memory array assembly 2, the second programmable logic unit I32 outputs a second logic signal to the second memory control unit I29, and the second memory control unit I29 controls the second programmable gate array assembly 3 to access the rest of the memory cells G13 of the first memory array assembly 2 through the third bonding lead-out region I28, the first bonding lead-out region H18 and the second bonding lead-out region G14 based on the second logic signal.

Independent memory access to the first memory array component 2 by the first programmable gate array combination 1 and the second programmable gate array combination 3 is realized through the connection mode shown in fig. 7.

The first asic array assembly 10 and the second asic array assembly 30 access different memory cells of the first memory array assembly 2 by using different memory control units, so as to implement independent memory access in the same manner as the independent memory access of the first programmable gate array assembly 1 and the second programmable gate array assembly 3, which is not described herein again.

It should be noted that, the first programmable gate array component and the second programmable gate array component of the present application may be an FPGA (field programmable gate array) or an effpga (non-volatile field programmable gate array). In a preferred embodiment, the first programmable gate array component and the second programmable gate array component are FPGAs (field programmable gate arrays) or efgas (embedded field programmable gate arrays).

In the integrated chip of this embodiment, the memory access of the second programmable gate array component to the first memory array component does not pass through the IO interface and/or the IO circuit, so that the interconnection distance is closer, the interconnection distribution parameter is lower, and the power consumption overhead of the memory access is significantly reduced. In the chip manufacturing process, the second programmable gate array component and the first programmable gate array component can be produced simultaneously, and the second programmable gate array component and the first programmable gate array component are bonded and then bonded with the first storage array component 2, so that the process complexity can be reduced, and the cost can be saved. However, the memory access of the second programmable gate array assembly to the first memory array assembly 2 needs to pass through the first interface module 11 and the second interface module 31, which causes a slight area loss.

As can be seen from the above description, in the integrated chip of this embodiment, the memory access to the first memory array component 2 by the second programmable gate array combination 3/the second asic array component 30 and the first programmable gate array combination 1/the first asic array component 10 does not pass through an IO interface, and is connected by three-dimensional heterogeneous bonding, so that the interconnection distance is closer, and the power consumption overhead of the memory access is significantly reduced.

In the chip manufacturing process, the first logic assembly 100 and the second logic assembly 200 can be produced simultaneously, and the first logic assembly 100 and the second logic assembly 200 are bonded with the first memory array assembly 2 after being bonded and tested, so that the process complexity can be reduced, and the cost can be saved. With this structure, memory accesses to the first memory array assembly 2 by the second logic assembly 200 need to pass through the first interface module 11 and the second interface module 31, which may cause some power consumption loss.

In another embodiment, the second logic element 200 is disposed on a side of the first memory array element 2 away from the first logic element 100. That is, the first memory array element 2 is disposed between the first logic element 100 and the second logic element 200. The first memory array component 2 includes a fourth bonded lead-out region, and the third bonded lead-out region 311 and the fourth bonded lead-out region constitute a three-dimensional heterogeneous integrated interconnection. In this embodiment, the second logic component 100 and the second logic component 200 can be directly interconnected with the storage array component 2, which is beneficial to a larger storage access bandwidth.

In this embodiment, the first logic component 100 only needs to pass through the first interface module 11 for the storage access of the first storage array component 2, and the second logic component 200 only needs to pass through the second interface module 31 for the storage access of the first storage array component 2. This structure allows closer interconnection distance between the second logic assembly 200 and the first memory array assembly 2, which can further reduce memory access power consumption. However, in the manufacturing process of the integrated chip with such a structure, the first logic component 100 and the first memory array component 2 need to be bonded first, and then the first logic component and the second logic component 200 need to be bonded.

Referring to fig. 8, a schematic structural diagram of a third embodiment of the integrated chip of the present invention is shown, which is different from the first embodiment shown in fig. 2 in that the integrated chip of this embodiment further includes: a second storage array component 4. The second storage array element 4 is disposed on a side of the first storage array element 2 away from the first logic element 100, and the second storage array element 4 is disposed with a third bonding lead-out region 311, in this embodiment, the first storage array element 2 includes a fourth bonding lead-out region 32, and the third bonding lead-out region 311 and the fourth bonding lead-out region 32 form a three-dimensional heterogeneous integrated interconnection.

In the embodiment, more storage array components are integrated, which is beneficial to increasing the storage density and realizing larger storage access bandwidth. In this embodiment, more storage array components are integrated, which is beneficial to increasing the storage density, and after a plurality of storage array components are uniformly produced and tested to form a standard product, the standard product is integrated with the logic component, which is beneficial to reducing the cost.

In one embodiment, the first programmable gate array assembly accesses the first memory array assembly 2 and the second memory array assembly 4 using the same memory control unit. Specifically, when the first programmable gate array component shares the same memory control unit to access the first memory array component 2 and the second memory array component 4, in order to avoid access conflict, the memory control unit may selectively select the first programmable gate array component to access the first memory array component 2 or the second memory array component 4 in a time-sharing manner.

Referring to fig. 10, in the embodiment, the integrated chip further includes a memory control unit H21, and the memory control unit H21 is disposed on the first interface module H17. In this embodiment, the first interface module H17 includes two first bond pad out regions, i.e., a first bond pad out region H19 and a first bond pad out region H18. The first memory array module 2 is provided with a plurality of memory cells G13, and the memory cell G13 is provided with two second bond lead-out regions, namely a second bond lead-out region G12 and a second bond lead-out region G14. The second memory array module 4 is provided with a plurality of memory cells F01, and the memory cell F01 is provided with a third bond lead-out region I28.

Specifically, the first bond lead-out region H18 connects the second bond lead-out region G14. The memory control unit H21 is connected to the first bond lead-out region H18. Thus, the memory control unit H21 can control the first programmable gate array element to access the first memory array element 2 through the first bonding lead-out region H18 and the second bonding lead-out region G14.

The first bond lead-out region H19 connects to the second bond lead-out region G12, and the second bond lead-out region G12 connects to the third bond lead-out region I28. Thus, the memory control unit H21 can control the first programmable gate array element to access the second memory array element 4 through the first bonding lead-out region H19, the second bonding lead-out region G12, and the third bonding lead-out region I28. The second bond lead-out region G12 is not connected to the memory cell G13.

In this embodiment, the first programmable gate array component further includes a programmable logic unit K23, the programmable logic unit K23 is connected to the storage control unit H21 through an interface routing unit H22, and the programmable logic unit K23 derives logic signals. The memory control unit H21 selectively controls the first programmable gate array element to access the first memory array element 2 or controls the first programmable gate array element to access the second memory array element 4 in a time-sharing manner based on the logic signals. Specifically, the memory control unit H21 controls the first programmable gate array element to access the first memory array element 2 at a first time and controls the first programmable gate array element to access the second memory array element 4 at a second time based on the logic signals.

In one embodiment, a first programmable gate array assembly accesses a first memory array assembly 2 and a second memory array assembly 4 using two different memory control units, respectively. Specifically, the first programmable gate array component respectively utilizes two different memory control units to access the first memory array component 2 and the second memory array component 4, and since there is no access conflict, the memory control unit can simultaneously control the first programmable gate array component to access the first memory array component 2 and control the first programmable gate array component to access the second memory array component 4. Specifically, the first memory control unit controls the first programmable gate array component to access the first memory array component 2, and the second memory control unit controls the first programmable gate array component to access the second memory array component 4.

Referring to fig. 10, in the present embodiment, the integrated chip further includes a first memory control unit H20 and a second memory control unit I29, and the first memory control unit H20 and the second memory control unit I29 are disposed on the first interface module H17. In this embodiment, the first interface module H17 includes two first bond pad out regions, i.e., a first bond pad out region H19 and a first bond pad out region H18. The first memory array module 2 is provided with a plurality of memory cells G13, and the memory cell G13 is provided with two second bond lead-out regions, namely a second bond lead-out region G12 and a second bond lead-out region G14. The second memory array module 4 is provided with a plurality of memory cells F01, and the memory cell F01 is provided with a third bond lead-out region I28.

In the present embodiment, the first memory control unit H20 is connected to the first bond lead-out region H18, and the first bond lead-out region H18 is connected to the second bond lead-out region G14. Thus, the first memory control unit H18 can control the first programmable gate array device to access the first memory array device 2 through the first bonding lead-out region H18 and the second bonding lead-out region G14.

Further, the second memory control unit I29 is connected to the first bond lead-out region H19, the first bond lead-out region H19 is connected to the second bond lead-out region G12, and the second bond lead-out region G12 is connected to the third bond lead-out region I28. Thus, the second memory control unit I29 can control the first programmable gate array element to access the second memory array element 4 through the first bond lead-out region H19, the second bond lead-out region G12 and the third bond lead-out region I28. The second bond lead-out region G12 is not connected to the memory cell G13.

In this embodiment, the first programmable gate array component further includes: the programmable logic unit K23 and the programmable logic unit K23 are connected with the first storage control unit H20 and the second storage control unit I29, and logic signals are led out of the programmable logic unit K23. Specifically, the programmable logic unit K23 is connected to the first storage control unit H20 and the second storage control unit I29 through the interface routing unit H22. In this embodiment, the first memory control unit H20 controls the first programmable gate array element to access the first memory array element 2 based on logic signals, and the second memory control unit I29 simultaneously controls the first programmable gate array element to access the second memory array element 4 based on logic signals.

The present application also proposes another embodiment in which a plurality of memory array elements implement a hybrid memory access to at least one programmable gate array element by designing a multiplexed or independent memory control cell using a hybrid of the methods of fig. 9 and 10. In the same integrated chip, the programmable logic units in partial areas use the multiplexing storage control unit shown in fig. 9 to realize storage access; the programmable logic units in the partial area realize storage access by using the independent storage control unit shown in FIG. 10.

In another embodiment, as shown in FIG. 11, the second storage array component 4 may also be disposed on a side of the first logic component 100 away from the first storage array component 2. The second storage array component 4 is provided with a third bonded lead-out area 311, the first interface module 11 includes a fourth bonded lead-out area 32, and the third bonded lead-out area 311 and the fourth bonded lead-out area 32 form a three-dimensional heterogeneous integrated interconnection.

In this embodiment, more storage array components are integrated, which is beneficial to increasing the storage density, and after a plurality of storage array components are uniformly produced and tested to form a standard product, the standard product is integrated with the logic component, which is beneficial to reducing the cost. And because the first storage array component 2 and the second storage array component 4 are directly connected with the first programmable gate array component, the three-dimensional heterogeneous integration is reduced, the interconnection distance is closer, the storage access distance is short, the distribution parameters are small, and the storage access frequency and the power consumption are optimal.

Referring to fig. 12, in the embodiment, the integrated chip further includes a memory control unit H21, and the memory control unit H21 is disposed on the first interface module H17. In this embodiment, the first interface module H17 includes two first bond pad out regions, i.e., a first bond pad out region H19 and a first bond pad out region H18. A plurality of memory cells G13 are disposed on the first memory array module 2, and a second bond lead-out region G14 is disposed on the memory cell G13. The second memory array module 4 is provided with a plurality of memory cells F01, and the memory cell F01 is provided with a third bond lead-out region I28.

The memory control unit H21 may connect the third bond lead-out region I28 through the first bond lead-out region H19, the first bond lead-out region H19. Thus, the memory control unit H21 can control the first programmable gate array element to access the second memory array element 4 through the first bonding lead-out region H19 and the third bonding lead-out region I28.

In this embodiment, the first programmable gate array component further includes a programmable logic unit K23, the programmable logic unit K23 is connected to the storage control unit H21 through an interface routing unit H22, and the programmable logic unit K23 derives logic signals. The memory control unit H21 selectively controls the first programmable gate array element to access the first memory array element 2 or controls the first programmable gate array element to access the second memory array element 4 in a time-sharing manner based on the logic signals. Specifically, the memory control unit H21 controls the first programmable gate array element to access the first memory array element 2 at a first time and controls the first programmable gate array element to access the second memory array element 4 at a second time based on the logic signals

Referring to fig. 13, in the present embodiment, the integrated chip further includes a first memory control unit H20 and a second memory control unit I29, and the first memory control unit H20 and the second memory control unit I29 are disposed on the first interface module H17. In this embodiment, the first interface module H17 includes two first bond pad out regions, i.e., a first bond pad out region H19 and a first bond pad out region H18. A plurality of memory cells G13 are disposed on the first memory array module 2, and a second bond lead-out region G14 is disposed on the memory cell G13. The second memory array module 4 is provided with a plurality of memory cells F01, and the memory cell F01 is provided with a third bond lead-out region I28.

Further, the second memory control unit I29 is connected to the first bond lead-out region H19, and the first bond lead-out region H19 is connected to the third bond lead-out region I28. Thus, the second memory control unit I29 can control the first programmable gate array element to access the second memory array element 4 through the first bonding lead-out region H19 and the third bonding lead-out region I28.

The present application also proposes another embodiment in which a plurality of memory array elements implement a hybrid memory access to at least one programmable gate array element by designing a multiplexed or independent memory control cell using a hybrid of the methods of fig. 12 and 13. In the same integrated chip, the programmable logic units in partial areas use the multiplexing storage control unit shown in fig. 12 to realize storage access; the programmable logic units in the partial area realize storage access by using the independent storage control unit shown in FIG. 13.

In the application, the storage array component can be a multilayer chip and is combined through three-dimensional heterogeneous integrated bonding; the application specific integrated circuit array component can be provided with one or more arbitrary combinations of a multiplication and addition calculation array, a multiplication calculation array, a pulse processor array, a hash calculation array, various encoder arrays, a machine learning special layer array, a retrieval function array, an image/video processing array, and hard core operation/processing units such as a CPU (central processing unit), an MCU (microprogrammed control unit) and the like, and is used for being combined with a programming gate array component to improve the processing density of an integrated chip.

Specifically, the component may be at least one of a die or a chip and a wafer (wafer), but not limited thereto, and may be any alternative conceivable by those skilled in the art. The wafer (wafer) is a silicon wafer used for manufacturing a silicon semiconductor circuit, and the chip or die (chip or die) is a silicon wafer obtained by dividing the wafer on which the semiconductor circuit is manufactured. For example, the memory array component of the present application may be a memory array die (DRAM die or DRAM chip), a memory array wafer (DRAM wafer).

In the integrated chip provided by the application, the programmable gate array component and the application-specific integrated circuit array component do not access the storage of the storage array component through an IO interface, so that the interconnection distance is closer, and the power consumption overhead of the storage access is obviously reduced. And a programmable storage integrated structure with high bandwidth and low power consumption is realized by a three-dimensional heterogeneous integrated bonding mode.

Based on the same utility model concept as the method, the embodiment of the utility model also provides a three-dimensional heterogeneous integrated chip structure. The integrated chip is provided with layered stacked components, and the components can be any one of the components through three-dimensional heterogeneous integration interconnection. When the integrated chip is prepared, the integrated chip can also be directly prepared by taking a wafer (wafer) as a unit, and three-dimensional heterogeneous integration is carried out.

When the integrated chip is prepared, the integrated chip can be partially prepared by taking a wafer (wafer) as a unit and three-dimensional heterogeneous integration is carried out, and the method specifically comprises two methods: performing three-dimensional heterogeneous integration on part of wafer layers to form an intermediate product, and performing iteration on the rest of wafer layers and the intermediate product until the preparation is finished; or after three-dimensional heterogeneous integration is carried out on part of wafer layers, an intermediate product is formed, then the intermediate product is cut into crystal grains (die), and the die is subjected to three-dimensional heterogeneous integration of the crystal grains with the crystal grains of other components, so that the preparation is completed.

Specifically, the manufacturing process of the integrated chip composed of the multi-layer programmable gate array assembly and at least one layer of memory array assembly shown in fig. 5 includes two methods: carrying out three-dimensional heterogeneous integration on the multilayer programmable gate array component by taking a wafer as a unit to form an intermediate product so as to improve the interconnection density, and carrying out three-dimensional heterogeneous integration on the intermediate product and the intermediate product formed by at least one layer of storage array component to obtain an integrated chip; or, the multilayer programmable gate array component is subjected to three-dimensional heterogeneous integration by taking a wafer as a unit to form an intermediate product, the intermediate product is cut into crystal grains and tested, and then the crystal grains are integrated with the intermediate product after the cutting test formed by at least one layer of storage array component to obtain an integrated chip.

Similarly, the integrated chip of the multi-layer memory array module and the at least one layer of programmable gate array module shown in fig. 8 can be prepared by two methods: carrying out three-dimensional heterogeneous integration on the multilayer storage array component by taking a wafer as a unit to form an intermediate product so as to improve the interconnection density, and carrying out three-dimensional heterogeneous integration on the intermediate product and the intermediate product formed by at least one layer of programmable gate array component to obtain an integrated chip; or, the multilayer storage array component is integrated three-dimensionally and heterogeneously by taking a wafer as a unit to form an intermediate product, the intermediate product is cut into crystal grains and tested, and then the crystal grains are integrated with the intermediate product after the cutting test formed by at least one layer of programmable gate array component to obtain an integrated chip.

The number and the sequence of the layers of the programmable gate array component and the storage array component of the integrated chip depend on the application scene, engineering requirements, production cost and complex game of production yield, and the obtained optimal result is not single. Different target products with different layer numbers and layer sequences also have diversified production and preparation processes, and have obvious differences on the design and the reuse design of the memory controller.

In the Programmable Gate Array module, the Programmable function module is widely interconnected with the Programmable routing network, referring to fig. 14, the Programmable Gate Array module is based on the extension of Field-Programmable Gate Array (FPGA/Embedded Field-Programmable Gate Array, effpga) technology, and the Programmable Gate Array module includes a Programmable logic block 11A and a Programmable routing network 11b (interconnect); the programmable logic blocks 11A are interconnected with each other through the routing network 11B and configured as a plurality of programmable function modules, and at least a part of the programmable routing network 11B can be extended to the interface routing unit, so as to form large-capacity, high-bandwidth and programmable storage access by interconnecting large-capacity storage arrays in a cross-layer manner through three-dimensional heterogeneous integration.

Three-dimensional heterogeneous integration is a technology of stacked chip interconnection Bonding, such as Hybrid Bonding (Hybrid Bonding) process. The integrated chip is prepared by utilizing a three-dimensional heterogeneous integrated bonding layer manufactured by a back end of line (BEOL) on the basis of a prepared chip (such as a programmable gate array component or a storage array component) to realize high-density interconnection of signals between chips.

Specifically, fig. 15 is taken as an example for explanation. In fig. 15, the integrated chip includes a functional component 210, a functional component 220, and a functional component 230, and the functional component 210, the functional component 220, and the functional component 230 may be a programmable gate array component and/or a memory array component. The

functional components

210, 220 and 230 each comprise a top metal layer, an internal metal layer active layer and a substrate, wherein the top metal layer and the internal metal layer are used for intra-component signal interconnection; the active layer is used for realizing a transistor and forming a module function; the substrate serves to protect the module and provide mechanical support, etc. The

functional components

210 and 220 are close to one side of the top metal layer, and three-dimensional heterogeneous integrated bonding layers are manufactured through the subsequent process and are interconnected to form a face-to-face interconnection structure; the side of the functional element 220 close to the substrate and the side of the functional element 230 close to the top metal layer are subjected to a subsequent process to manufacture a three-dimensional heterogeneous integrated bonding layer and are interconnected to form a back-to-back (or back-to-back) interconnection structure. Between the

functional components

210, 220 and 230, cross-component signal interconnections can be arbitrarily established through three-dimensional heterogeneous integration. The difference is whether the core voltages of functional component 210, functional component 220, and functional component 230 are the same, corresponding to the two interconnect technologies.

When the core voltages of functional component 210 and functional component 230 are the same, taking functional circuit 1 in functional component 210, as an example, needing to establish cross-component interconnect with functional circuit 10 in functional component 230: leading-out signals of an internal metal layer of the functional component 210 of the functional circuit 1 are connected with a face-to-face three-dimensional heterogeneous integrated bonding structure between the functional component 210 and the functional component 220 through top metal of the functional component 210, and further are interconnected with the top metal of the functional component 220; interconnection signals interconnected to the back-to-face three-dimensional heterogeneous integrated bonding structure between the functional component 220 and the functional component 230 through the internal metal layers of the functional component 220 and Through Silicon Vias (TSVs) that penetrate the active layer of the functional component 220 and the thinned substrate, and further interconnected to the top metal layer of the functional component 230; the interconnect signals implement interconnecting the functional circuitry 10 in the functional component 230 across the components through the internal metal layers of the functional component 230.

When the core voltages of the functional component 210 and the functional component 230 are different, taking the functional circuit 2 in the functional component as an example, it is necessary to establish cross-component interconnection with the functional circuit 10 in the functional component 230: designing a level shift circuit 2 in the functional component 210, the level shift circuit 2 and the functional circuit 2 being interconnected in the functional component 210; after the level shifter circuit 2 converts the interconnect signal of the functional circuit 2 to match the core voltage of the functional component 230, the functional circuit 20 in the functional component 230 is interconnected across the components using the aforementioned method. Further, the level shift circuit 2 may be transferred to the functional module 230 or the functional module 220 by three-dimensional heterogeneous integration interconnection.

In the integrated chip provided by the application, the programmable gate array component and the application-specific integrated circuit array component do not access the storage of the storage array component through an IO interface and/or an IO circuit, so that the interconnection distance is shorter, and the power consumption overhead of the storage access is obviously reduced. And a programmable storage integrated structure with high bandwidth and low power consumption is realized by a three-dimensional heterogeneous integrated bonding mode.

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. An integrated chip, comprising:

a first logic component, the first logic component comprising:

a first programmable gate array assembly comprising at least one first programmable gate array component;

a first application specific integrated circuit array component located at the same layer as at least one of the first programmable gate array components;

a first interface module including a first bonding lead-out region; the first application specific integrated circuit array component and at least one first programmable gate array component are connected with the first interface module through an internal metal layer;

the first memory array assembly is provided with a second bonding lead-out region, and the second bonding lead-out region and the first bonding lead-out region form a three-dimensional heterogeneous integrated interconnection so as to connect the programmable gate array assembly, the first application specific integrated circuit array assembly and the interconnection signal on the first memory array assembly together.

2. The integrated chip of claim 1, wherein a side of the first interface module proximate to the first programmable gate array component has an interface routing unit;

the programmable function module of the first programmable gate array component is led out to one side, close to the first interface module, of the first programmable gate array component through the internal metal layer and is connected with the interface routing unit.

3. The integrated chip of claim 2, wherein the first programmable gate array component comprises: at least one first programmable gate array component is interconnected with the programmable routing network through an internal metal layer and is connected to the interface routing unit through the programmable routing network.

4. The integrated chip of claim 1, wherein the number of the first interface modules is at least two, and two of the first interface modules are spaced apart from the first programmable gate array component.

5. The integrated chip of claim 1, wherein the first Programmable Gate Array component is a Field-Programmable Gate Array (FPGA); or an Embedded Field-Programmable Gate Array (eFPGA).

6. The integrated chip according to any one of claims 1 to 5, further comprising:

a second storage array component disposed on a side of the first programmable gate array assembly away from the first storage array component;

the second storage array assembly is provided with a third bonding lead-out area;

the first interface module comprises a fourth bonding leading-out area, and the first programmable gate array component and the second storage array component are connected in a bonding mode through the third bonding leading-out area and the fourth bonding leading-out area.

7. The integrated chip according to any one of claims 1 to 5, further comprising:

a second storage array component disposed on a side of the first storage array component away from the first programmable gate array assembly;

the first storage array assembly comprises a fourth bonding leading-out area, and the first storage array assembly and the second storage array assembly are connected in a bonding mode through the fourth bonding leading-out area and the third bonding leading-out area.

8. The integrated chip of claim 6, further comprising:

the storage control unit is arranged on the first interface module;

the memory control unit controls the first programmable gate array component to access the first memory array component and the second memory array component.

9. The integrated chip of claim 8, wherein the first programmable gate array component further comprises:

the programmable logic unit is connected with the storage control unit and leads out logic signals;

the storage control unit selectively controls the first programmable gate array component to access the first storage array component or controls the first programmable gate array component to access the second storage array component in a time-sharing mode based on the logic signals.

10. The integrated chip of claim 6, further comprising:

the first storage control unit is arranged on the first interface module;

the second storage control unit is arranged on the first interface module;

the first storage control unit controls the first programmable gate array component to access the first storage array component, and the second storage control unit controls the first programmable gate array component to access the second storage array component.