CN110148563A - A kind of semiconductor devices and its manufacturing method - Google Patents
A kind of semiconductor devices and its manufacturing method Download PDFInfo
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- CN110148563A CN110148563A CN201910434970.5A CN201910434970A CN110148563A CN 110148563 A CN110148563 A CN 110148563A CN 201910434970 A CN201910434970 A CN 201910434970A CN 110148563 A CN110148563 A CN 110148563A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000000758 substrate Substances 0.000 claims description 37
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 22
- 229910021332 silicide Inorganic materials 0.000 claims description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 239000003989 dielectric material Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 238000010276 construction Methods 0.000 claims description 5
- 238000003475 lamination Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 18
- 230000000694 effects Effects 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 49
- 238000002955 isolation Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910019044 CoSix Inorganic materials 0.000 description 1
- 241000416536 Euproctis pseudoconspersa Species 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910005889 NiSix Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 229910008486 TiSix Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 206010000496 acne Diseases 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
Abstract
The present invention provides a kind of semiconductor devices and forming method thereof, is sequentially formed with inside wall and external wall on the sidewalls of the gate, and the thickness of external wall is greater than the thickness of inside wall, after forming source-drain area, external wall is removed, and cover stressor layers.In this way, after removing external wall, grid two sides are exposed by the part that thicker external wall covers, again after covering stressor layers, stressor layers can be being formed on the closer region of channel, thus, that realizes device closes on stress effect, bigger stress is generated to device, so that the speed and performance of device obtain bigger promotion.
Description
Technical field
The present invention relates to semiconductor devices and its manufacturing field, in particular to a kind of semiconductor devices and its manufacturing method.
Background technique
With the continuous reduction of device size, after entering nano-scale, the limit for closing on Semiconductor Physics device is asked
Topic is comed one after another, so that device performance is affected.
Stress engineering plays an important role the raising of device performance, can make MOS device by stress engineering
While speed is promoted, guarantee that element leakage does not increase, if stress engineering can be more directly applied to the channel of device,
Bigger stress can be then generated to device, so that the speed and performance of device obtain bigger promotion.
Summary of the invention
In view of this, realizing facing for device the purpose of the present invention is to provide a kind of semiconductor devices and its manufacturing method
Nearly stress effect promotes device speed and performance.
To achieve the above object, the present invention has following technical solution:
A kind of manufacturing method of semiconductor devices, comprising:
Substrate is provided, the side wall being formed on grid and gate lateral wall on the substrate, the side wall includes inside wall
And external wall, the thickness of the external wall are greater than the thickness of inside wall；
Source-drain area is formed in the substrate of the grid two sides；
Remove the external wall；
Form the stressor layers for covering the dielectric material of the source-drain area, inside wall and grid.
Optionally, between the step of removing the external wall and covering stressor layers, further includes:
Metal silicide layer is formed on the source-drain area.
Optionally, for the thickness of the inside wall less than 100 angstroms, the thickness range of the external wall is 300-1000 angstroms.
Optionally, the inside wall is laminated construction.
Optionally, the inside wall is the lamination of silica and silicon nitride layer thereon, and the external wall is silica.
Optionally, the stressor layers include tensile stress material.
Optionally, the tensile stress material is tensile stress silicon nitride.
A kind of semiconductor devices, comprising:
Substrate；
Grid on the substrate；
Source-drain area in the substrate of the grid two sides；
Inside wall on the gate lateral wall, and the inside wall extends to the source-drain area to the substrate；
Cover the stressor layers of the dielectric material of the source-drain area, inside wall and grid.
Optionally, further includes:
Metal silicide layer on the source-drain area.
Optionally, the stressor layers include tensile stress material.
Semiconductor devices provided in an embodiment of the present invention and forming method thereof is sequentially formed with interior on the sidewalls of the gate
Side wall and external wall, and the thickness of external wall is greater than the thickness of inside wall, and after forming source-drain area, external wall is gone
It removes, and covers stressor layers.In this way, grid two sides are exposed by the part that thicker external wall covers after removing external wall
Come, after covering stressor layers again, stressor layers can formed on the closer region of channel, thus, realize facing for device
Nearly stress effect generates bigger stress to device, so that the speed and performance of device obtain bigger promotion.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, below will to embodiment or
Attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is this hair
Bright some embodiments for those of ordinary skill in the art without creative efforts, can be with
Other attached drawings are obtained according to these attached drawings.
Fig. 1 shows the flow diagram of the manufacturing method of semiconductor devices according to embodiments of the present invention；
Fig. 2-7 shows the device profile during manufacturing method formation semiconductor devices according to an embodiment of the present invention
Structural schematic diagram.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention may be used also
To be different from other way described herein using other and implemented, those skilled in the art can be without prejudice in the present invention
Similar popularization is done in the case where culvert, therefore the present invention is not limited by the specific embodiments disclosed below.
Secondly, combination schematic diagram of the present invention is described in detail, when describing the embodiments of the present invention, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the scope of protection of the invention.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
As the description in background technique, stress engineering plays an important role the raising of device performance, by answering
While power engineering can make MOS device speed be promoted, guarantee that element leakage does not increase, if can be more straight by stress engineering
The channel applied to device connect can then generate bigger stress, so that the speed and performance of device are obtained to device
Bigger promotion.
For this purpose, being sequentially formed on the sidewalls of the gate present applicant proposes a kind of semiconductor devices and its manufacturing method
Inside wall and external wall, and the thickness of external wall is greater than the thickness of inside wall, after forming source-drain area, by external wall
Removal, and cover stressor layers.In this way, the part that grid two sides are covered by thicker external wall exposes after removing external wall
Out, after covering stressor layers again, stressor layers can be being formed on the closer region of channel, thus, realize device
Stress effect is closed on, bigger stress is generated to device, so that the speed and performance of device obtain bigger promotion.
Specific embodiment is described in detail below with reference to flow chart Fig. 1 and attached drawing 2-7.
Refering to what is shown in Fig. 1, providing substrate 100 in step S01, being formed with grid 110 and grid on the substrate 100
Side wall on 110 side walls, the side wall include inside wall 112 and external wall 114, and the thickness of the external wall 114 is greater than inside
The thickness of wall 112, with reference to shown in Fig. 4.
In the embodiment of the present application, substrate 100 can be semiconductor substrate, semiconductor substrate for example can for Si substrate,
Ge substrate, SiGe substrate, SOI (silicon-on-insulator, Silicon On Insulator) or GOI (germanium on insulator,
Germanium On Insulator) etc..In other embodiments, semiconductor substrate can also be include that other elements are partly led
The substrate of body or compound semiconductor, such as GaAs, InP or SiC etc. can also be laminated construction, such as Si/SiGe etc. is gone back
It can be other epitaxial structures, such as SGOI (silicon germanium on insulator) etc..In the present embodiment, which can serve as a contrast for silicon
Bottom.
Isolation structure (not shown go out) can be already formed in substrate 100, isolation structure may include silica
Or the material of other active areas that can separate device, isolation structure for example can be shallow trench isolation (STI, Shallow
Trench Isolation), the substrate area around isolation structure is active area.
On the substrate 100 of active area, it is already formed with grid 110, grid Jie is also formed between grid 110 and substrate
Matter layer 102.Wherein, gate dielectric layer 104 for example can be thermal oxide layer or other suitable dielectric materials, such as silica or
High K medium material, high K medium grid material such as hafnium base oxide, HFO2, in HfSiO, HfSiON, HfTaO, HfTiO etc.
A kind of or in which several combination.Grid 110 can be single or multi-layer structure, such as can be polysilicon, amorphous silicon or gold
Belong to electrode material or their combination, metal electrode material can be one or more groups of TiN, TiAl, Al, TaN, TaC, W
It closes.It can be patterned after growth gate dielectric material and grid material, to form gate dielectric layer 102 and thereon
Grid 110, with reference to shown in Fig. 2.
Side wall is already formed on the side wall of grid 110, side wall includes inside wall 112 and external wall 114, inside wall 112
Closer to the side wall of grid 110, external wall 114 is to sacrifice side wall, has thicker thickness compared with inside wall 112, in this way,
After removing external wall 114, isolation of the relatively thin inside wall 112 as grid 110 can be left, meanwhile, thicker external wall
Region can be used for being formed it is closer apart from channel and with more many areas stressor layers, thus, conducive to promoted device stress
Effect, realization close on stress effect.
In some embodiments, the thickness of external wall 114 can be 3 times or more of 112 thickness of inside wall, inside wall 112
When for lamination, the wherein deposition thickness with a thickness of spacer material of side wall, should with a thickness of from 110 side wall of grid along parallel substrate
The size that 100 directions extend.
In the embodiment of the present application, inside wall 112 may include laminated construction, may include silica, silicon nitride, nitrogen
Silica or their combination, in the present embodiment, inside wall 112 may include the silica stacked gradually from inside to outside
The lamination of 112-1 and silicon nitride 112-2, external wall 114 can be silica.In specific application, the thickness of inside wall 112
Degree can be less than 100 angstroms, and the thickness of external wall may range from 300-1000 angstroms or more.
In the particular embodiment, inside wall 112 and external wall 114 can be formed by following steps.
Specifically, firstly, after forming grid 110, inside wall 112-1,112-2 and external wall 114 are successively carried out
Deposition, refering to what is shown in Fig. 3, the material of inside wall 112-1,112-2 can be silica and silicon nitride thereon, external wall 114
Material can be silica.
Then, anisotropic etching can be used, such as can be RIE (reactive ion etching), is vertically carried out
The etching of 114 material of inside wall 112 and external wall, until exposure substrate 100 surface, in this way, 110 upper surface of grid and
Spacer material except 110 side wall of grid will be all removed, and only the spacer material of 110 side wall of grid remains, thus, shape
At inside wall 112 and external wall 114, with reference to shown in Fig. 4.
In step S02, source-drain area 120 is formed in the substrate 100 of 110 two sides of grid, with reference to shown in Fig. 5.
Ion implantation doping particle can be carried out according to the needs of type of device, and carry out annealing activation doping, carry out shape
At source-drain area 120, specifically, the doping particle of N-type or p-type can be injected, the doping particle of n-type doping for example can for N,
P, As, S etc., the doping particle of p-type doping can be for example B, Al, Ga or In etc..
In step S03, the external wall 114 is removed, with reference to shown in Fig. 5.
In the step, external wall 114 is removed, after external wall 114 removes, grid 110 is only by relatively thin inside wall
112 isolation, the region of the external wall of removal will be used to form stressor layers.
In specific application, which can be removed using dry or wet, in the present embodiment, can used
Wet etching removes the external wall 114 of silicon.
After removing external wall 114, silication technique for metal can be carried out, forms metal silicide on source-drain area 120
Layer 122 when grid 110 includes polysilicon, can also form metal silicide layer 124, with reference to Fig. 6 institute on grid 110 simultaneously
Show.
Metal silicide layer 122/124 can be formed by silication technique for metal, in silication technique for metal, in growth gold
After belonging to layer, by heat treatment process, so that react between metal and the semiconductor material being in contact with it, and other are situated between
Material does not react with metal, thus, form metal silicide layer.In the embodiment of the present application, the material example of metal
Such as can be Ni, Ti or Co, on exposed silicon by the silication technique for metal of Ni, Ti, Co etc. after, form metallic silicon
Compound layer is respectively NiSix、 TiSix、CoSix.Metal layer and metal silicide layer herein is merely illustrative, can also be it
The metal silicide layer that he can arbitrarily be formed by the metal material that metal silication reaction can occur, the application do not make this
It is special to limit.
The metal silicide layer 122 on source-drain area 120 is formed after removing external wall 114, it can be to avoid external wall
Damage when 114 removal to metal silicide layer 122, meanwhile, it can be in silication technique for metal, when repairing external wall removal
Process integration and processing quality are improved in the surface that source-drain area 120 damages.
In step S04, the stress for covering the dielectric material of the source-drain area 120, inside wall 112 and grid 110 is formed
Layer 130, with reference to shown in Fig. 7.
The stressor layers 130 of dielectric material are covered on grid 110 and on the active area of 110 side of grid, this is answered
Power layer 130 will remain always stress layer as device, due to only leaving and leaving after the removal of outer side wall
Isolation of the relatively thin inside wall 112 as grid 110, the region of thicker external wall form closer apart from channel and have
There are the stressor layers 130 of more many areas, stress can be applied to channel through relatively thin inside wall 112 by the stressor layers 130,
To more directly be applied to the channel of device, then can generate bigger stress to device so that the speed of device and
Performance obtains bigger promotion, and realization closes on stress effect.
Can be according to the needs of device, the material of stress types needed for selecting, can be for tensile stress as stressor layers
Or the dielectric material of compression, in the present embodiment, stressor layers 130 include tensile stress material, such as can be for high tensile stress
Silicon nitride can use PECVD (Plasma enhanced chemical vapor in specific application
Deposition, plasma activated chemical vapour deposition) method form the silicon nitride of high tensile stress, can be by depositing
The ratio of nitrogen, silicon, hydrogen etc. in process gas is adjusted in technique, to adjust the size of specific stress, stress intensity needed for realizing
Stressor layers.
Later, other processing technologys that device can be continued, may include: on source-drain area formed interlayer dielectric layer with
And form the contact plug (not shown go out) etc. of perforation interlayer dielectric layer and stressor layers 130 to source-drain area 120.
The manufacturing method of the semiconductor devices of the embodiment of the present application is described in detail above, in addition, the application
The semiconductor devices formed by the above method is additionally provided, refering to what is shown in Fig. 7, including:
Substrate 100；
Grid 110 on the substrate 100；
Source-drain area 120 in the 110 two sides substrate 100 of grid；
Inside wall 112 on 120 side wall of grid, and the inside wall 112 extended to the substrate 100 it is described
Source-drain area 120；
Cover the stressor layers 130 of the dielectric material of the source-drain area 120, inside wall 112 and grid 110.
Further, further includes: the metal silicide layer 122 on the source-drain area 120.
Further, further includes: interlayer dielectric layer and perforation interlayer dielectric layer and stressor layers 130 on source-drain area 120
To the contact plug of source-drain area 120.
Further, the thickness of the inside wall 112 is less than the length that the inside wall 112 extends to the substrate 100
Degree.
Further, the thickness of the inside wall can be less than 100 angstroms, and the inside wall 112 is prolonged to the substrate 100
The length range stretched can be 300-1000 angstroms.
Further, the inside wall 112 can be laminated construction.
All the embodiments in this specification are described in a progressive manner, same and similar between each embodiment
Part may refer to each other, and the highlights of each of the examples are differences from other embodiments.Especially for device
For part embodiment, since it is substantially similar to the method embodiment, so describing fairly simple, related place is referring to method
The part of embodiment illustrates.
The above is only a preferred embodiment of the present invention, although the present invention has been disclosed in the preferred embodiments as above, so
And it is not intended to limit the invention.Anyone skilled in the art is not departing from technical solution of the present invention ambit
Under, many possible changes and modifications all are made to technical solution of the present invention using the methods and technical content of the disclosure above,
Or equivalent example modified to equivalent change.Therefore, anything that does not depart from the technical scheme of the invention, according to the present invention
Technical spirit any simple modification, equivalent variation and modification made to the above embodiment, still fall within the technology of the present invention
In the range of scheme protection.
Claims (10)
1. a kind of manufacturing method of semiconductor devices characterized by comprising
Substrate is provided, the side wall being formed on the substrate on grid and gate lateral wall, the side wall includes inside wall and outer
Side wall, the thickness of the external wall are greater than the thickness of inside wall；
Source-drain area is formed in the substrate of the grid two sides；
Remove the external wall；
Form the stressor layers for covering the dielectric material of the source-drain area, inside wall and grid.
2. the manufacturing method according to claim 1, which is characterized in that in the step for removing the external wall and covering stressor layers
Between rapid, further includes:
Metal silicide layer is formed on the source-drain area.
3. the manufacturing method according to claim 1, which is characterized in that the thickness of the inside wall is described outer less than 100 angstroms
The thickness range of side wall is 300-1000 angstroms.
4. the manufacturing method according to claim 1, which is characterized in that the inside wall is laminated construction.
5. manufacturing method according to claim 4, which is characterized in that silicon nitride of the inside wall for silica and thereon
The lamination of layer, the external wall are silica.
6. manufacturing method according to any one of claims 1-5, which is characterized in that the stressor layers include tensile stress material
Material.
7. manufacturing method according to claim 6, which is characterized in that the tensile stress material is tensile stress silicon nitride.
8. a kind of semiconductor devices characterized by comprising
Substrate；
Grid on the substrate；
Source-drain area in the substrate of the grid two sides；
Inside wall on the gate lateral wall, and the inside wall extends to the source-drain area to the substrate；
Cover the stressor layers of the dielectric material of the source-drain area, inside wall and grid.
9. device according to claim 8, which is characterized in that further include:
Metal silicide layer on the source-drain area.
10. device according to claim 8, which is characterized in that the stressor layers include tensile stress material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201910434970.5A CN110148563A (en) | 2019-05-23 | 2019-05-23 | A kind of semiconductor devices and its manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910434970.5A CN110148563A (en) | 2019-05-23 | 2019-05-23 | A kind of semiconductor devices and its manufacturing method |
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| Publication Number | Publication Date |
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| CN110148563A true CN110148563A (en) | 2019-08-20 |
Family
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| CN201910434970.5A Pending CN110148563A (en) | 2019-05-23 | 2019-05-23 | A kind of semiconductor devices and its manufacturing method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20150143725A (en) * | 2013-04-16 | 2015-12-23 | 머레이 앤 풀 엔터프라이지즈, 리미티드 | Sustained-release formulations of colchicine and methods of using same |
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