CN110148101B - Low-cache improved histogram equalization method and system based on FPGA - Google Patents

Low-cache improved histogram equalization method and system based on FPGA Download PDF

Info

Publication number
CN110148101B
CN110148101B CN201910337758.7A CN201910337758A CN110148101B CN 110148101 B CN110148101 B CN 110148101B CN 201910337758 A CN201910337758 A CN 201910337758A CN 110148101 B CN110148101 B CN 110148101B
Authority
CN
China
Prior art keywords
histogram
result
img
size
gray
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910337758.7A
Other languages
Chinese (zh)
Other versions
CN110148101A (en
Inventor
吴志杰
王群
任小漩
于明轩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Institute of Remote Sensing Equipment
Original Assignee
Beijing Institute of Remote Sensing Equipment
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Institute of Remote Sensing Equipment filed Critical Beijing Institute of Remote Sensing Equipment
Priority to CN201910337758.7A priority Critical patent/CN110148101B/en
Publication of CN110148101A publication Critical patent/CN110148101A/en
Application granted granted Critical
Publication of CN110148101B publication Critical patent/CN110148101B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T5/00—Image enhancement or restoration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T5/00—Image enhancement or restoration
    • G06T5/40—Image enhancement or restoration by the use of histogram techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/10—Image acquisition modality
    • G06T2207/10024—Color image
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/10—Image acquisition modality
    • G06T2207/10048—Infrared image

Abstract

The invention discloses a low-buffer improved histogram equalization method and a system based on FPGA, wherein a time division multiplexing control signal is generated through a time division multiplexing module; the cache control module generates time sequence control signals cached by the three histogram statistical branches; the histogram caching module caches histogram statistical results of the three branches; the histogram merging and accumulating module reads, sums and accumulates the histograms of the three branches; the gray level mapping module is used for completing the mapping from the histogram result to the appointed gray level range; the gray mapping result caching module caches the gray mapping result; the histogram equalization output module completes the output of the histogram equalization result; the method is applied to visible light and infrared image enhancement preprocessing, and has the advantages of high operation processing speed, good real-time performance, less resource consumption and high application value.

Description

Low-cache improved histogram equalization method and system based on FPGA
Technical Field
The invention relates to a low-cache improved histogram equalization method and system based on an FPGA (field programmable gate array).
Background
Histogram equalization is a method for adjusting the contrast of an image by using an image histogram, and is generally used to increase the global contrast of the image, but may also increase the contrast of background noise and decrease the contrast of a useful signal, which causes distortion of the visual effect of the image.
Disclosure of Invention
The invention aims to provide a low-buffer improved histogram equalization method based on an FPGA (field programmable gate array), which solves the problems of noise amplification, image distortion, detail loss and the like in the conventional method.
In view of this, the technical solution provided by the present invention is: an improved low-cache histogram equalization method based on FPGA is characterized by comprising the following specific steps:
generating a time division multiplexing control signal;
generating time sequence control signals cached by three histogram statistical branches according to the input time division multiplexing control signals;
caching the histogram statistical results of the three branches;
reading, summing and accumulating histograms of the three branches;
mapping the histogram result to a specified gray scale range;
caching a gray mapping result;
and finishing the output of the histogram equalization result.
Further, the generating the three-way time division multiplexing control signal comprises: firstly, reading the previous statistical result from the cache RAM, then adding 1 to the read statistical result to obtain a new statistical result, and finally writing the new statistical result into the cache RAM.
Further, the generating a write enable signal wea, an address signal addra and a data signal dina of the histogram statistic result cache RAM according to the input time division multiplexing control signal includes:
when the time division multiplexing control signal is effective, giving the input image data to an address signal to finish data reading in the RAM;
delaying for two clock cycles, and then adding 1 to the DOUTa output from the RAM port A to be used as a data signal;
delaying the time division multiplexing control signal for two clock periods as an enabling signal, simultaneously judging whether douta is greater than TH _ H, closing the write enabling signal when douta is greater than TH _ H, wherein TH _ H is a histogram statistical upper limit value, setting the Width of an image as Img _ Width and the Height as Img _ Height, and the Width of a Pixel bit as Pixel _ Size,
TH _ H is
Figure GDA0002104517900000021
The range of epsilon is 4-128.
Further, ε is chosen to be 8.
Further, the step of caching the histogram statistics of the three branches includes: calling an IP core Block Memory Generator, selecting a True Dual Port RAM, wherein the A Port, the B Port and the read-write Port are configured identically;
the bit Width is configured to ceil (log2(Img _ Width × Img _ Height × ∈)) -Pixel _ Size, and the depth is configured to 2 according to the Pixel bit WidthPixel_SizeThe operation mode selects Read First, and enables selection of Always Enabled.
Further, the step of reading, summing and accumulating the statistical results of the three branch histograms includes:
step one, after the statistics of a frame of histogram is completed, a read timing control signal of a histogram cache module is started to be generated, and the address addrb is accumulated from 0 to 2Pixel_Size1, setting a B port write enable web to be valid, setting a B port write data dinb to be 0, and clearing data in the cache while reading histogram statistics results doutb1, doubt2 and doutb3 of the three branches to prepare for next frame of histogram statistics;
and step two, calculating the sum img _ hist of the statistical results doutb1, doubt2 and doutb3 of the three branch histograms, and performing upper limit protection on the img _ hist according to the following algorithm to obtain the img _ hist _ new.
f(img_hist<TH_L)
img_hist_new＝0；
elseif(img_hist>TH_H)
img_hist_new＝TH_H；
else
img_hist_new＝img_hist；
end
Wherein TH _ L is the lower limit of the histogram and is generally set as 1 or 2, and the interference of noise on the equalization result of the histogram is eliminated;
step three, finishing the gray level from 0 to 2Pixel_SizeThe histogram img _ hist _ new of-1 is accumulated to obtain acc _ img _ hist while preserving 2Pixel_Size-1 gray level accumulation result Nval _ nx, where Nval _ nx is the total number of valid points, and Nval _ nx is protected by the following algorithm to obtain Nval:
Figure GDA0002104517900000031
further, the mapping the histogram to the specified gray scale range includes: setting the requirement of equalizing image bit width as Histeq _ Size, and mapping the histogram result to Histeq _ Size through bit width Pixel _ Size normalization, wherein the mapping algorithm is as follows:
Gray_Map＝(2Histeq-1)×acc_img_hist/Nval
firstly supplementing Histeq _ Size zeros by acc _ img _ hist low bits, then subtracting acc _ img _ hist to obtain a numerator, then calling a divider to obtain a histogram mapping result Gray _ Map, and finally writing the Gray _ Map into a Gray mapping result cache module for histogram equalization output.
Further, the caching the gray mapping result comprises:
and calling an IP core Block Memory Generator, selecting a TDPRAM, and configuring the A port, the B port and the read-write port in the same way. The bit width is configured as Histeq _ Size, and the depth is configured as 2 according to the pixel bit widthPixel_SizeThe operation mode selects Write First, enabling selection of Use Ena Pin.
Further, the performing histogram equalization result output includes: according to the input image data, the image data is buffered as the address of the gray scale mapping result buffer RAM, and the gray scale mapping result buffer RAM outputs.
Another object of the present invention is to provide an FPGA-based low-cache improved histogram equalization system, which includes:
the device comprises a time division multiplexing module, a cache control module, a histogram cache module, a histogram merging and accumulating module, a gray mapping result cache module and a histogram equalization output module;
the time division multiplexing module is used for generating a time division multiplexing control signal;
the buffer control module is used for generating time sequence control signals buffered by the three histogram statistical branches;
the histogram caching module is used for caching the histogram statistical results of the three branches;
the histogram merging and accumulating module is used for reading, summing and accumulating the histograms of the three branches;
the gray mapping module is used for mapping the histogram result to a specified gray range;
the gray mapping result caching module is used for caching a gray mapping result;
and the histogram equalization output module is used for outputting the histogram equalization result.
So far, the low-buffer improved histogram equalization based on the FPGA is completed.
The invention achieves the following significant beneficial effects:
the realization is simple, include: generating a time division multiplexing control signal; generating time sequence control signals cached by three histogram statistical branches according to the input time division multiplexing control signals; caching the histogram statistical results of the three branches; reading, summing and accumulating histograms of the three branches; mapping the histogram result to a specified gray scale range; caching a gray mapping result; and finishing the output of the histogram equalization result. Through the steps, the noise part is suppressed during histogram statistics, and the contrast is increased while details are kept and distortion is avoided. The method is applied to visible light and infrared image enhancement preprocessing, and has the advantages of high operation processing speed, good real-time performance, less resource consumption and high application value.
Drawings
FIG. 1 is a flow chart of the low cache modified histogram equalization method of the present invention based on FPGA;
fig. 2 is a schematic structural diagram of the low-cache improved histogram equalization system based on FPGA of the present invention.
Detailed Description
The advantages and features of the present invention will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings and detailed description of specific embodiments of the invention. It is to be noted that the drawings are in a very simplified form and are not to scale, which is intended merely for convenience and clarity in describing embodiments of the invention.
It should be noted that, for clarity of description of the present invention, various embodiments are specifically described to further illustrate different implementations of the present invention, wherein the embodiments are illustrative and not exhaustive. In addition, for simplicity of description, the contents mentioned in the previous embodiments are often omitted in the following embodiments, and therefore, the contents not mentioned in the following embodiments may be referred to the previous embodiments accordingly.
While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood that the inventors do not intend to limit the invention to the particular embodiments described, but intend to protect all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the claims. The same component numbers may be used throughout the drawings to refer to the same or like parts.
Referring to fig. 1, the present invention provides an FPGA-based low-cache improved histogram equalization method, which includes the following specific steps: step S101, generating a time division multiplexing control signal; step S102, generating time sequence control signals cached by three histogram statistical branches according to the input time division multiplexing control signals; step S103, caching histogram statistical results of the three branches; step S104, reading, summing and accumulating the histograms of the three branches; step S105, mapping the histogram result to a specified gray scale range; step S106, caching a gray mapping result; and finishing the output of the histogram equalization result.
Preferably, the generating the three-way time division multiplexing control signal comprises: firstly, reading the previous statistical result from the cache RAM, then adding 1 to the read statistical result to obtain a new statistical result, and finally writing the new statistical result into the cache RAM.
Preferably, the generating the write enable signal wea, the address signal addra and the data signal dina of the histogram statistic result cache RAM according to the input time division multiplexing control signal includes:
when the time division multiplexing control signal is effective, giving the input image data to an address signal to finish data reading in the RAM;
delaying for two clock cycles, and then adding 1 to the DOUTa output from the RAM port A to be used as a data signal;
delaying the time division multiplexing control signal for two clock periods as an enabling signal, simultaneously judging whether douta is greater than TH _ H, closing the write enabling signal when douta is greater than TH _ H, wherein TH _ H is a histogram statistical upper limit value, setting the Width of an image as Img _ Width and the Height as Img _ Height, and the Width of a Pixel bit as Pixel _ Size,
TH _ H is
Figure GDA0002104517900000051
The range of epsilon is 4-128.
Preferably epsilon is chosen to be 8.
Preferably, the step of caching histogram statistics of three branches includes: calling an IP core Block Memory Generator, selecting a True Dual Port RAM, wherein the A Port, the B Port and the read-write Port are configured identically;
the bit Width is configured to ceil (log2(Img _ Width × Img _ Height × ∈)) -Pixel _ Size, and the depth is configured to 2 according to the Pixel bit WidthPixel_SizeThe operation mode selects Read First, and enables selection of Always Enabled.
Preferably, the step of reading, summing and accumulating the statistical results of the three branch histograms includes:
step one, after the statistics of a frame of histogram is completed, a read timing control signal of a histogram cache module is started to be generated, and the address addrb is accumulated from 0 to 2Pixel_Size1, setting a B port write enable web to be valid, setting a B port write data dinb to be 0, and clearing data in the cache while reading histogram statistics results doutb1, doubt2 and doutb3 of the three branches to prepare for next frame of histogram statistics;
and step two, calculating the sum img _ hist of the statistical results doutb1, doubt2 and doutb3 of the three branch histograms, and performing upper limit protection on the img _ hist according to the following algorithm to obtain the img _ hist _ new.
f(img_hist<TH_L)
img_hist_new＝0；
elseif(img_hist>TH_H)
img_hist_new＝TH_H；
else
img_hist_new＝img_hist；
end
Wherein TH _ L is the lower limit of the histogram and is generally set as 1 or 2, and the interference of noise on the equalization result of the histogram is eliminated;
step three, finishing the gray level from 0 to 2Pixel_SizeThe histogram img _ hist _ new of-1 is accumulated to obtain acc _ img _ histWhile preserving 2Pixel_Size-1 gray level accumulation result Nval _ nx, where Nval _ nx is the total number of valid points, and Nval _ nx is protected by the following algorithm to obtain Nval:
Figure GDA0002104517900000061
preferably, the mapping of the histogram to the specified gray scale range includes: setting the requirement of equalizing image bit width as Histeq _ Size, and mapping the histogram result to Histeq _ Size through bit width Pixel _ Size normalization, wherein the mapping algorithm is as follows:
Gray_Map＝(2Histeq-1)×acc_img_hist/Nval
firstly supplementing Histeq _ Size zeros by acc _ img _ hist low bits, then subtracting acc _ img _ hist to obtain a numerator, then calling a divider to obtain a histogram mapping result Gray _ Map, and finally writing the Gray _ Map into a Gray mapping result cache module for histogram equalization output.
Preferably, the caching the grayscale mapping result includes:
and calling an IP core Block Memory Generator, selecting a TDPRAM, and configuring the A port, the B port and the read-write port in the same way. The bit width is configured as Histeq _ Size, and the depth is configured as 2 according to the pixel bit widthPixel_SizeThe operation mode selects Write First, enabling selection of Use Ena Pin.
Preferably, the performing histogram equalization result output includes: according to the input image data, the image data is buffered as the address of the gray scale mapping result buffer RAM, and the gray scale mapping result buffer RAM outputs.
Referring to fig. 2, another objective of the present invention is to provide an FPGA-based low-cache improved histogram equalization system, including: the device comprises a time division multiplexing module, a cache control module, a histogram cache module, a histogram merging and accumulating module, a gray mapping result cache module and a histogram equalization output module; the time division multiplexing module is used for generating a time division multiplexing control signal; the buffer control module is used for generating time sequence control signals buffered by the three histogram statistical branches; the histogram caching module is used for caching the histogram statistical results of the three branches; the histogram merging and accumulating module is used for reading, summing and accumulating the histograms of the three branches; the gray mapping module is used for mapping the histogram result to a specified gray range; the gray mapping result caching module is used for caching a gray mapping result; and the histogram equalization output module is used for outputting the histogram equalization result.
In one embodiment, the invention performs the following steps:
first step of building a histogram equalization system
A histogram equalization system, comprising: the device comprises a time division multiplexing module, a cache control module, a histogram cache module, a histogram merging and accumulating module, a gray mapping result cache module and a histogram equalization output module;
the time division multiplexing module has the functions of: generating a time division multiplexing control signal;
the cache control module has the functions of: generating time sequence control signals cached by three histogram statistical branches;
the histogram caching module has the functions of: caching the histogram statistical results of the three branches;
the histogram merging and accumulating module has the functions of: reading, summing and accumulating histograms of the three branches;
the gray mapping module has the functions of: completing the mapping of the histogram result to the appointed gray scale range;
the gray mapping result caching module has the functions of: caching a gray mapping result;
the histogram equalization output module has the functions of: finishing the output of the histogram equalization result;
the second step time division multiplexing module generates three paths of time division multiplexing control signals
The time division multiplexing module carries out cycle counting when externally input image data are effective, in order to obtain better time sequence effect, the process of histogram statistics is divided into three steps, firstly, the previous statistical result is read from the cache RAM, then, the read statistical result is added with 1 to obtain a new statistical result, and finally, the new statistical result is written into the cache RAM, so that the cycle counting period is set as 3, three paths of pulse signals latch _1, latch _2 and latch _3 are respectively generated at time points 1, 2 and 3 in the cycle period to serve as time division multiplexing control signals, and the pulse interval is three clock periods;
thirdly, the cache control module generates write time sequence control signals of three histogram statistical branch result cache RAMs
The cache control module generates a write enable signal wea, an address signal addra and a data signal dina of a histogram statistical result cache RAM according to an input time division multiplexing control signal, and the three steps are divided into three steps.
Step one, when a time division multiplexing control signal is effective, giving input image data to an address signal to finish data reading in an RAM;
delaying two clock cycles, and then adding 1 to the DOUTa output of the RAM port A as a data signal;
and step three, delaying the time division multiplexing control signal for two clock periods to serve as an enabling signal, simultaneously judging whether the douta is larger than TH _ H, and closing the write enabling signal when the douta is larger than TH _ H.
Here, TH _ H is a histogram statistical upper limit value and is also a key point of the low buffer processing. Setting the Width of the image as Img _ Width, the Height as Img _ Height, the Pixel bit Width as Pixel _ Size, and TH _ H as
Figure GDA0002104517900000081
(epsilon is selected in the range of 4-128, the smaller the detail loss is, the smaller the distortion is, the greater the detail loss is, but the distortion is also more serious, generally 8), in this case, the buffer write data bit Width is ceil (log2(Img _ Width × Img _ Height × 0 epsilon)) -Pixel _ Size, while the traditional histogram equalization write data bit Width requires ceil (log2(Img _ Width × 1Img _ Height)), and the total savings of Pixel _ Size + ceil (log2(Img _ Width × Img _ Height)) -ceil (log2(Img _ Width × Img _ Height × epsilon)). Assuming that the image is 640 × 512, the pixel bit width is 14, and ε is 8, the three histogram statistic branches are buffered to [14+ ceil (log2(640 × 512)) -ceil (log2(640 × 512 × 8))]×214×3＝528Kbits。
The fourth step histogram buffer module buffers the histogram statistical results of the three branches
And calling an IP core Block Memory Generator, selecting a True Dual Port RAM (TDPRAM) and ensuring that A, B ports and read-write ports are configured identically. The bit Width is configured to ceil (log2(Img _ Width × Img _ Height × ∈)) -Pixel _ Size, and the depth is configured to 2 according to the Pixel bit WidthPixel_SizeSelecting Read First in an operation mode, enabling to select Always Enabled, instantiating three histogram statistical results which are respectively used for storing three branches;
the fifth step of the histogram merging and accumulating module finishes the reading, the summation and the accumulation of the statistical results of the histograms of the three branches
The module is mainly completed by three steps:
step one, after the statistics of a frame of histogram is completed, a read timing control signal of a histogram cache module is started to be generated, and the address addrb is accumulated from 0 to 2Pixel_Size1, setting a B port write enable web to be valid, setting a B port write data dinb to be 0, and clearing data in the cache while reading histogram statistics results doutb1, doubt2 and doutb3 of the three branches to prepare for next frame of histogram statistics;
and step two, calculating the sum img _ hist of the statistical results doutb1, doubt2 and doutb3 of the three branch histograms, and performing upper limit protection on the img _ hist according to the following algorithm to obtain the img _ hist _ new.
f(img_hist<TH_L)
img_hist_new＝0；
elseif(img_hist>TH_H)
img_hist_new＝TH_H；
else
img_hist_new＝img_hist；
end
Wherein TH _ L is the lower limit of the histogram and is generally set as 1 or 2, and the interference of noise on the equalization result of the histogram is eliminated;
step three, finishing the gray level from 0 to 2Pixel_SizeThe histogram img _ hist _ new of-1 is accumulated to obtain acc _ img _ hist while preserving 2Pixel_Size-1 gray level accumulation result Nval _ nx, Nval _ nx being total number of valid points, for Nva as followsl _ nx is protected to get Nval.
if(Nval_nx<TH_H)
Nval＝TH_H；
else
Nval＝Nval_nx；
end
The sixth step of the gray level mapping module is used for completing the mapping from the histogram to the appointed gray level range
According to different application scene requirements, the bit width requirements of the equalized images are different, the bit width requirement of the equalized images is set to Histeq _ Size, therefore, the histogram result needs to be mapped to Histeq _ Size through bit width Pixel _ Size normalization, and the mapping algorithm is as follows:
Gray_Map＝(2Histeq-1)×acc_img_hist/Nval
firstly supplementing Histeq _ Size zeros by acc _ img _ hist low bits, then subtracting acc _ img _ hist to obtain a numerator, then calling a divider to obtain a histogram mapping result Gray _ Map, and finally writing the Gray _ Map into a Gray mapping result cache module for histogram equalization output.
The seventh step is that a gray mapping result caching module caches the gray mapping result
And calling an IP core Block Memory Generator, selecting a TDPRAM, and configuring the A port, the B port and the read-write port in the same way. The bit width is configured as Histeq _ Size, and the depth is configured as 2 according to the pixel bit widthPixel_SizeThe operation mode selects Write First, enabling selection of Use Ena Pin.
The eighth step of finishing the output of the histogram equalization result by the histogram equalization output module
According to the input image data, the image data is used as the address of the gray mapping result cache RAM, and the output of the gray mapping result cache RAM is the histogram equalization image.
So far, the low-buffer improved histogram equalization based on the FPGA is completed.
The invention achieves the following significant beneficial effects:
the realization is simple, include: generating a time division multiplexing control signal; generating time sequence control signals cached by three histogram statistical branches according to the input time division multiplexing control signals; caching the histogram statistical results of the three branches; reading, summing and accumulating histograms of the three branches; mapping the histogram result to a specified gray scale range; caching a gray mapping result; and finishing the output of the histogram equalization result. Through the steps, the noise part is suppressed during histogram statistics, and the contrast is increased while details are kept and distortion is avoided. The method is applied to visible light and infrared image enhancement preprocessing, and has the advantages of high operation processing speed, good real-time performance, less resource consumption and high application value.
Any other suitable modifications can be made according to the technical scheme and the conception of the invention. All such alternatives, modifications and improvements as would be obvious to one skilled in the art are intended to be included within the scope of the invention as defined by the appended claims.

Claims (2)

1. An improved low-cache histogram equalization method based on FPGA is characterized by comprising the following specific steps:
generating a time division multiplexing control signal;
generating time sequence control signals cached by three histogram statistical branches according to the input time division multiplexing control signals;
caching the histogram statistical results of the three branches;
reading, summing and accumulating histograms of the three branches;
mapping the histogram result to a specified gray scale range;
caching a gray mapping result;
finishing the output of the histogram equalization result;
the generating of the time division multiplexing control signal includes: firstly, reading a previous statistical result from a cache RAM, then adding 1 to the read statistical result to obtain a new statistical result, and finally writing the new statistical result into the cache RAM;
the generating of the time sequence control signals buffered by the three histogram statistic branches according to the input time division multiplexing control signals comprises: generating a histogram statistic result according to an input time division multiplexing control signal to buffer an A port write enable signal wea, an address signal addra and a data signal dina of a RAM, comprising:
when the time division multiplexing control signal is effective, giving the input image data to an address signal to finish data reading in the RAM;
delaying for two clock cycles, and then adding 1 to the DOUTa output from the RAM port A to be used as a data signal;
delaying the time division multiplexing control signal for two clock periods as an enabling signal, simultaneously judging whether douta is greater than TH _ H, closing the write enabling signal when douta is greater than TH _ H, wherein TH _ H is a histogram statistical upper limit value, setting the Width of an image as Img _ Width and the Height as Img _ Height, and the Width of a Pixel bit as Pixel _ Size,
TH _ H is
Figure FDA0003112125810000011
The epsilon is selected from the range of 4-128;
the step of caching histogram statistics of the three branches includes: calling an IP core Block Memory Generator, selecting a dual-port RAM, wherein the A port and the B port are the same in configuration as the read-write port;
the bit Width is configured to ceil (log2(Img _ Width × Img _ Height × ∈)) -Pixel _ Size, and the depth is configured to 2 according to the Pixel bit WidthPixel_SizeSelecting Read First in the operation mode, and enabling to select Always Enabled;
the step of reading, summing and accumulating the histograms of the three branches comprises:
step one, after the statistics of a frame of histogram is completed, a read timing control signal of a histogram cache module is started to be generated, and the address addrb is accumulated from 0 to 2Pixel_Size1, setting a B port write enable web to be valid, setting a B port write data dinb to be 0, and clearing data in a cache while reading histogram statistics results doutb1, doutb2 and doutb3 of the three branches to prepare for next frame of histogram statistics;
step two, obtaining the sum img _ hist of the statistical results doutb1, doutb2 and doutb3 of the histograms of the three branches, and performing upper limit protection on the img _ hist according to the following algorithm to obtain img _ hist _ new;
Figure FDA0003112125810000021
wherein TH _ L is the lower limit of the histogram and is set as 1 or 2, and the interference of noise to the equalization result of the histogram is eliminated;
step three, finishing the gray level from 0 to 2Pixel_SizeThe histogram img _ hist _ new of-1 is accumulated to obtain acc _ img _ hist while preserving 2Pixel_Size-1 gray level accumulation result Nval _ nx, where Nval _ nx is the total number of valid points, and Nval _ nx is protected by the following algorithm to obtain Nval:
Figure FDA0003112125810000022
the mapping of the histogram to the specified gray scale range comprises: setting the requirement of equalizing image bit width as Histeq _ Size, and mapping the histogram result to Histeq _ Size through bit width Pixel _ Size normalization, wherein the mapping algorithm is as follows:
Gray_Map＝(2Histeq_Size-1)×acc_img_hist/Nval,
firstly, supplementing Histeq _ Size zeros by acc _ img _ hist low bits, then subtracting acc _ img _ hist to obtain a molecule, then calling a divider to obtain a histogram mapping result Gray _ Map, and finally writing the Gray _ Map into a Gray mapping result cache module for balanced output of the histogram;
the caching the grayscale mapping results includes:
calling an IP core Block Memory Generator, selecting a dual-port RAM, wherein the A port and the B port are the same in configuration as the read-write port; the bit width is configured as Histeq _ Size, and the depth is configured as 2 according to the pixel bit widthPixel_SizeThe operation mode selects Write First, and enables to select Use Ena Pin;
the finishing of the output of the histogram equalization result comprises the following steps: according to the input image data, the image data is used as the address of the gray mapping result cache RAM, and the output of the gray mapping result cache RAM is the histogram equalization image.
2. The FPGA-based low-cache improved histogram equalization method of claim 1, wherein ε is chosen to be 8.
CN201910337758.7A 2019-04-25 2019-04-25 Low-cache improved histogram equalization method and system based on FPGA Active CN110148101B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910337758.7A CN110148101B (en) 2019-04-25 2019-04-25 Low-cache improved histogram equalization method and system based on FPGA

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910337758.7A CN110148101B (en) 2019-04-25 2019-04-25 Low-cache improved histogram equalization method and system based on FPGA

Publications (2)

Publication Number Publication Date
CN110148101A CN110148101A (en) 2019-08-20
CN110148101B true CN110148101B (en) 2021-08-13

Family

ID=67594404

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910337758.7A Active CN110148101B (en) 2019-04-25 2019-04-25 Low-cache improved histogram equalization method and system based on FPGA

Country Status (1)

Country Link
CN (1) CN110148101B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110889814B (en) * 2019-11-21 2024-04-26 上海无线电设备研究所 Visible light image histogram enhancement method and device based on Sysgen

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104217399B (en) * 2013-05-29 2018-03-30 无锡华润矽科微电子有限公司 Realize that infrared image carries out the circuit and method of plateau equalization processing function
CN108242042A (en) * 2016-12-23 2018-07-03 南京理工大学 Objective self-adapting plateau equalization implementation method based on FPGA
CN107248136B (en) * 2017-05-12 2019-11-08 西安交通大学 A kind of image histogram information acquisition method based on FPGA
CN109215001B (en) * 2017-07-01 2022-03-18 南京理工大学 High temperature difference self-adaptive platform histogram equalization implementation method based on FPGA

Also Published As

Publication number Publication date
CN110148101A (en) 2019-08-20

Similar Documents

Publication Publication Date Title
CN109658337B (en) FPGA implementation method for real-time electronic despinning of images
CN102456224A (en) Real-time digital image enhancement method based on field programmable gate array (FPGA)
CN104104888A (en) Parallel multi-core FPGA digital image real-time zooming processing method and device
CN108287336B (en) Area array Geiger APD laser radar range profile intensity image generation system
CN105787898A (en) Platform histogram equalization realization method based on FPGA, and device thereof
CN110148101B (en) Low-cache improved histogram equalization method and system based on FPGA
CN111294520B (en) FPGA-based real-time lucky imaging method and system
Zhang et al. VLSI architecture exploration of guided image filtering for 1080P@ 60Hz video processing
CN114070959A (en) FPGA-based video denoising hardware implementation method
CN100517498C (en) First in first out memory without read delay
CN108024074B (en) Miniaturized infrared imaging method based on SOPC
CN114092338A (en) Image zooming fast calculation method
CN104050635B (en) System and method for nonlinear filter real-time processing of image with adjustable template size
Dong et al. Configurable image rectification and disparity refinement for stereo vision
CN109215001B (en) High temperature difference self-adaptive platform histogram equalization implementation method based on FPGA
CN108460784B (en) FPGA-based gray scale and binary image expansion corrosion processing method
CN209881907U (en) Image acquisition equipment based on FPGA
CN112070651A (en) Texture mapping hardware accelerator based on double Buffer architecture
TWI789158B (en) Image processing method, image processing system, and non-transitory computer readable storage medium
KR100377181B1 (en) Histogram Equalization device using block histogram in image signal processor
CN111191780B (en) Averaging pooling accumulation circuit, device and method
CN104776919B (en) Infrared focal plane array ribbon Nonuniformity Correction system and method based on FPGA
CN114119372A (en) High-precision image scaling method based on FPGA
CN110996005A (en) Real-time digital image enhancement method and system
CN112153355B (en) Digital image pixel conversion system and method based on FPGA

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant