CN104104888A - Parallel multi-core FPGA digital image real-time zooming processing method and device - Google Patents
Parallel multi-core FPGA digital image real-time zooming processing method and device Download PDFInfo
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Abstract
Provided is a parallel multi-core FPGA digital image real-time zooming processing method and device. The method comprises the steps that original video image data to be processed are acquired firstly. The original video image data are inputted to an FPGA chip and the number of zooming cores is confirmed, and the original video image data are divided into image sub-blocks having the same number with that of the zooming cores. Then the divided data are stored in a buffer, the data in the buffer are returned to the FPGA and parallel zooming processing is performed on each image sub-block via one zooming core respectively so that zooming is completed. All the image sub-blocks after zooming are displayed after splicing processing. The method has certain guiding effect on high throughput and high real-time application of digital video images.
Description
Technical field
The present invention relates to a kind of processing method zooming in or out and device of image, specifically the real-time scaling method of a kind of parallel multi-core FPGA digital picture and device.
Background technology
Making rapid progress of electronic product and electronic technology, has driven improving constantly of Display Technique.Development along with video display technology and display terminal manufacturing technology, the size of the desired resolution of all kinds of Video Applications and display terminal is all improving constantly, not only occurred 1920 * 1080 and higher resolution, and the size of display terminal also constantly breaks through the limit of manufacturing process, especially the appearance of screen splicing technology and projection integration technology has further improved display resolution and the size of display terminal especially.The application such as modern media and communications meanwhile,, Window Display and public's demonstration make distributed video Display Technique be able to through engineering approaches.Popularization day by day along with this class application, people start to pursue single video and show that the high definition of node and more high-resolution video show, even some large-scale video consisting of screen splicing system and projection integration system shows that node is also deployed in distributed video display system, and this has improved video data throughput and the operand of single video node greatly.
These Display Techniques and demand, not only comprise and show more high-resolution video information as how larger screen, also comprises and how the video information of low resolution being amplified on the sharpness screen curtain of respective display screen size in real time.Be not difficult to find out thus, the development of video display technology has no longer only been limited by Display Technique itself, but is more limited by some applications quality, real-time and the processing mode of required video information and the operational capability of process chip.
Along with updating of semiconductor technology, integrated millions of transistor in processor unit are.Although the raising of this integrated level makes processor possess more powerful disposal ability, also make the power consumption of processor and heat dissipation problem become increasingly conspicuous.Because dwindling of CMOS transistor feature size causes number of transistors object in unit are, increase, add the lifting of clock frequency, transistor drain current in unit are is constantly increased.Research shows, the every lifting of processor performance l%, and power consumption will increase by 3%.If do not take other to reduce power consumption measure according to this trend development, in 2015, the power dissipation density in every sq will reach kilowatt.The heat accumulation causing therefrom will make chip cannot work at all.Have scholar to point out, under the condition of single-processor, systematic function increase rate is proportional to the square root of system complexity increase rate.As previously mentioned, under the constant prerequisite of system complexity, the treatment effeciency that how to improve system just becomes particularly important.In screen splicing and projection integration technology field, often digital video image to be carried out to real-time convergent-divergent to meet the resolution of different display terminals.Because the data volume of digital video image is large, requirement of real-time is high, require panntographic system will there is larger data throughput capabilities and higher treatment effeciency, so the disposal ability of system is particularly important, the mode of parallel processing, as a kind of efficient processing method, is applied when video image zooming.
At Chinese patent CN103269416A, a kind of device and method that adopts parallel processing mode to realize video image tiled display is disclosed, comprise the following steps: (1) identifies decoded digital video image signal, determine video format, and be divided at least two parts by viewing area; (2) video signal after cutting apart is carried out respectively to image processing simultaneously; (3) convert respectively each video signal after processing to can show for external terminal diaplay unit video signal; (4) video signal all terminal diaplay units being shown is spliced into a complete image.Wherein, in step (2), graphics processing unit carries out image to the video signal of input and also comprises before processing the video image after cutting apart keep in and image is cut apart to the step of mating with the processing speed of image processing.In the method, adopt method that parallel processing mode realizes video image tiled display first to carry out image and cut apart the order of carrying out again image processing by adopting, and in image processing section, adopted the processing method of parallel synchronous, the data transfer rate of not only processing reduces greatly, has also overcome that the response speed existing in prior art is slow, heating is serious, the problem such as slow of dispelling the heat.But, due in device corresponding to the method, the chip that need to adopt multidiameter delay to process, the fpga chip, multichannel cache chip, multiway images process chip, multichannel interface chip and the terminal presentation facility that comprise image cutting unit and video format detecting unit one, multichannel is processed has increased system cost undoubtedly, in addition when screen image being divided into many groups while processing separately, be synchronously a very important problem, directly have influence on image in the demonstration situation of terminal.
Summary of the invention
For this reason, the object of the invention is to in video image method for parallel processing of the prior art, system cost is high, need to keep synchronous problem, proposes a kind ofly to have simplified system configuration, without the synchronously real-time scaling method of attainable parallel multi-core FPGA digital picture and device thereof.
For solving the problems of the technologies described above, one of object of the present invention is to provide the real-time scaling method of a kind of parallel multi-core FPGA digital picture, comprises following process:
(1) obtain pending raw video image data, by described raw video image data input fpga chip;
(2) according to the upper limit working clock frequency of input pixel clock frequency, output pixel clock frequency and single convergent-divergent core, determine convergent-divergent check figure order;
(3), according to the number of described convergent-divergent core, by described raw video image data, by being longitudinally evenly divided into the image subblock consistent with convergent-divergent check figure order, any one edge, the image subblock left and right sides all needs to external expansion one row;
(4) view data after cutting apart is stored in external cache device;
(5) view data in described external cache device is read in fpga chip and processed line by line, each image subblock after cutting apart is independently used a convergent-divergent core to carry out convergent-divergent processing, the parallel running of described convergent-divergent core;
(6) all image subblocks after convergent-divergent are according to pixels put and spliced line by line processing, obtain the digital video image after convergent-divergent.
In the step (2) of the described real-time scaling method of a kind of parallel multi-core FPGA digital picture, the described upper limit working clock frequency according to input pixel clock frequency, output pixel clock frequency and single convergent-divergent core determines that convergent-divergent check figure object process comprises: obtain input pixel clock frequency CLK
inwith output pixel clock frequency CLK
out, after comparing, obtain pixel clock highest frequency CLK=max{CLK
in, CLK
out, the upper limit working clock frequency of single convergent-divergent core is CLK
smax, convergent-divergent check figure order n is positive integer, and n>=CLK/CLK
smax.
Further, in the described real-time scaling method of a kind of parallel multi-core FPGA digital picture, the upper limit working clock frequency CLK of described pixel clock highest frequency CLK and single convergent-divergent core
smax, work as CLK/CLK
smaxduring for integer, n=CLK/CLK
smax; Work as CLK/CLK
smaxduring for non-integer, n=[CLK/CLK
smax]+1.
In the step (4) of the described real-time scaling method of a kind of parallel multi-core FPGA digital picture, described external cache device is Double Data Rate synchronous DRAM.
In the step (5) of the described real-time scaling method of a kind of parallel multi-core FPGA digital picture, it is to adopt bilinear interpolation algorithm that described convergent-divergent is processed.
Another object of the present invention is to provide the real-time convergent-divergent processing unit of a kind of parallel multi-core FPGA digital picture, and this device comprises:
Input module: obtain pending raw video image data, and by described raw video image data input fpga chip;
Convergent-divergent core computing module: determine convergent-divergent check figure order according to the upper limit working clock frequency of input pixel clock frequency, output pixel clock frequency and single convergent-divergent core;
Cut apart module: according to the number of described convergent-divergent core, each image subblock after described raw video image data are cut apart and cut apart;
Memory module: as the bidirectional data transfers interface of buffer and fpga chip, be responsible for the function of access and reading images sub-block data;
Zoom module: by memory module reads image data line by line from buffer, each is cut apart image subblock and uses separately a convergent-divergent core to carry out convergent-divergent processing;
Splicing output module: all image subblocks after convergent-divergent are spliced to processing line by line in pixel mode, obtain the digital video image after convergent-divergent.
Technique scheme of the present invention has the following advantages compared to existing technology,
The real-time scaling method of 1 parallel multi-core FPGA digital picture of the present invention, obtain pending raw video image data, by described raw video image data input fpga chip, then determine convergent-divergent check figure order, and described raw video image Data Segmentation is become to the image subblock consistent with convergent-divergent check figure order, then the data after cutting apart are stored in buffer, again the data in buffer are turned back in FPGA, each image subblock is processed via the convergent-divergent core convergent-divergent that walks abreast respectively, complete convergent-divergent, all image subblocks after convergent-divergent are spliced and processed rear demonstration.In the method, first by FPGA, carry out image and cut apart, then deposit the data after cutting apart in buffer area buffer memory, then the image that the information in buffer area is turned back to after cutting apart in FPGA is processed.And in prior art, by FPGA, will after Video Image Segmentation, put into buffering area, after buffer memory, need to send into graphics processing unit and process again.Compared with prior art, in this programme, saved follow-up graphics processing unit, by FPGA, realize two functions cutting apart and process, greatly reduced system cost, in addition, in prior art, needing that image is divided into many groups carries out separately, because the passage that adopts different equipment to form carries out parallel processing, be therefore synchronously a very important problem, and in the present invention, image is processed and all in same FPGA, is carried out, synchronous without considering.Scheme of the present invention, by multi-core parallel concurrent treatment technology, preferably balance system processing power and the zooming digital video image algorithm contradiction between higher to throughput, requirement of real-time, not only reduced the calculating clock frequency of panntographic system, also reduced system cost, improved system treatment effeciency, the high-throughput of digital video image, high real-time application have been had to certain directive function simultaneously.In addition, in this technical scheme, adopt moderate performance, lower-cost low and middle-end fpga chip to carry out the processing of multi-core parallel concurrent zooming digital video image, reach and be not strict with under the condition of chip performance and external environment condition, take resource few, on hardware attainable object.
The real-time scaling method of 2 parallel multi-core FPGA digital picture of the present invention, the number of convergent-divergent core is more than or equal to the ratio of the upper limit working clock frequency of pixel clock highest frequency and single convergent-divergent core.Like this, designer can realize by the quantity of change convergent-divergent core the video image zooming treatment system of any complexity, according to chip disposal ability dynamic-configuration convergent-divergent nuclear volume, thereby the real-time convergent-divergent that makes digital video image can be on common hardware platform high-efficiency operation, reduce and calculate clock frequency, reduced system cost simultaneously.This technology can be used as the core technology of the real-time convergent-divergent of video image, splicing system, has reduced the complexity that image scaling is processed, and has effectively improved the design efficiency of FPGA firmware.
The real-time scaling method of 3 parallel multi-core FPGA digital picture of the present invention, the number n of convergent-divergent core, works as CLK/CLK
smaxduring for integer, n=CLK/CLK
smax; Work as CLK/CLK
smaxduring for non-integer, n=[CLK/CLK
smax]+1, this mode is meeting on the basis that image subblock processes, and what make that the data of convergent-divergent core arrange is as far as possible few, thus while guaranteeing parallel processing, parallel number remains in optimum quantity, takes into account the treatment effeciency on Liao Mei road in the time of parallel processing.
The real-time scaling method of 4 parallel multi-core FPGA digital picture of the present invention, described convergent-divergent is processed and is adopted bilinear interpolation algorithm, the pixel value for the treatment of solution point is only relevant to 4 original image vegetarian refreshments around it, owing to treating in bilinear interpolation that solution point pixel value is relevant to the pixel value of 4 pixels around it, so can start parallel convergent-divergent computing after DID two row after being cut apart, therefore greatly improve treatment effeciency, saved the time.
The real-time scaling method of 5 parallel multi-core FPGA digital picture of the present invention, adopts the method for longitudinal even partition during to described raw video image Data Segmentation.Because display is generally worked according to raster scan (raster scan) mode, pixel is according to exporting successively from order left to bottom right.Therefore in the solution of the present invention, according to the feature of raster scan mode, video image is carried out longitudinally evenly dividing, longitudinal division of video image can effectively reduce the data volume that needs buffer memory after each image subblock convergent-divergent, and can reduce the delay between inputted video image and output video image, improve the real-time of panntographic system.In this programme, feature for computer export video image, video image is carried out longitudinally cutting apart in preprocessing process, effectively reduced the data volume that needs buffer memory after each image subblock convergent-divergent, reduced the requirement to the throughput of system cache and capacity.Therefore, longitudinal dividing method in video image preconditioning technique of the present invention, can reduce the time of delay between inputted video image and output video image, improves the treatment effeciency of panntographic system, greatly improved real-time, and can realize and laying a good foundation for the hardware of algorithm.
The real-time scaling method of 6 parallel multi-core FPGA digital picture of the present invention, each sub-block after cutting apart on the basis of even partition line, to after external expansion one row as the image subblock after cutting apart.Image partition method is herein relevant to adopted convergent-divergent algorithm.In the bilinear interpolation algorithm adopting, the pixel value for the treatment of solution point is only relevant to 4 original image vegetarian refreshments around it, by each region to external expansion one row, the line of demarcation of each sub-block after cutting apart, guaranteed each image subblock after cutting apart calculating during until solution point required pixel pixel value exist, and need to when processing, again not copy edge, reduce the complexity of processing.
The real-time scaling method of 7 parallel multi-core FPGA digital picture of the present invention, described buffer is Double Data Rate synchronous DRAM, there is the higher speed that reads and store and good net synchronization capability, therefore, improved on the whole the treatment effeciency of the method.The real time processing system of video image need to have certain data throughout, and this not only requires system to have certain computing capability, also requires system will have certain data buffer storage ability.Reasonably data buffer storage mode not only can improve the treatment effeciency of algorithm, also can reduce the requirement to the data throughout of system cache and capacity, and Double Data Rate synchronous DRAM (DDR-SDRAM) has well met requirement herein.
The real-time scaling method of 8 parallel multi-core FPGA digital picture of the present invention, each image subblock carries out convergent-divergent processing via a convergent-divergent core, adopts the mode of parallel running, the parallel processing simultaneously of a plurality of convergent-divergent core.The present invention adopts multi-core parallel concurrent treatment technology, reduces the amount of calculation of single convergent-divergent core, on the basis of balance arithmetic speed and system resources consumption, realizes real-time video image zooming and processes.The amount of calculation of the single convergent-divergent core of the method is little, total algorithm treatment effeciency is high, possesses the condition realizing on hardware.
Accompanying drawing explanation
For content of the present invention is more likely to be clearly understood, below according to a particular embodiment of the invention and by reference to the accompanying drawings, the present invention is further detailed explanation, wherein:
Fig. 1 is the flow chart of the real-time scaling method of parallel multi-core FPGA digital picture in the embodiment of the present invention 1;
Fig. 2 is the system block diagram of the real-time scaling method of parallel multi-core FPGA digital picture in the embodiment of the present invention;
Fig. 3 is the algorithm flow block diagram of the real-time scaling method of parallel multi-core FPGA digital picture in the embodiment of the present invention;
Fig. 4 is raster scan and longitudinal partitioning scheme schematic diagram in the embodiment of the present invention;
Fig. 5 is preliminary treatment dividing method schematic diagram in the embodiment of the present invention;
Fig. 6 (a) and Fig. 6 (b) are respectively the schematic diagrames of the pixel of original image and the pixel of the image after convergent-divergent;
The algorithm schematic diagram that Fig. 7 (a)-Fig. 7 (d) is bilinear interpolation.
Embodiment
embodiment 1:
Development along with technology, demand to video display technology, no longer be solely limited to show more high-resolution video information as how larger screen, also comprise and how the video information of low resolution being amplified on the sharpness screen curtain of respective display screen size in real time.Be not difficult to find out thus, the development of video display technology has no longer only been limited by Display Technique itself, but is more limited by some applications quality, real-time and the processing mode of required video information and the operational capability of process chip.
Based on this, the present embodiment provides a kind of real-time scaling method of parallel digital video image of high treatment efficiency, with balance sysmte disposal ability and zooming digital video image to the contradiction between the high requirement of throughput, real-time, thereby reach the object that reduces system cost, improves system treatment effeciency.Scheme in the present embodiment can be applied to, in screen splicing and projection integration technology field, realize the matched well between image to be displayed resolution and display terminal resolution.
The present embodiment provides a kind of parallel multi-core FPGA digital picture real-time scaling method, and its flow chart as shown in Figure 1, comprises following process:
(1) obtain pending raw video image data, by described raw video image data input fpga chip.
In this step, Computer display adapter (video card) signal is input to video capture device by VGA or DVI interface, if when the signal receiving is analog signal, will first carry out analog-to-digital conversion by AD converter, analog signal is converted to data-signal.When reception signal is digital signal, directly by decoder, decodes, thereby obtain digital video image signal.The digital video image signal herein obtaining is input in fpga chip as raw video image data.
(2) according to the upper limit working clock frequency of input pixel clock frequency, output pixel clock frequency and single convergent-divergent core, determine convergent-divergent check figure order.
Convergent-divergent core herein refers to a kind of soft core with zoom function, by programming, has had zoom function, then it is embedded in FPGA, realizes zoom function.Present FPGA design, huge and function is complicated, therefore each part of design is that to start anew be unpractical.For comparatively general part, can reuse existing functional module, and main time and resource are used in to those brand-new, the unique parts in design.Convergent-divergent core used herein is exactly a kind of soft core, has the processing capacity of convergent-divergent, and the built-in function being similar in MATLAB can be called.
The number that convergent-divergent core is set in a FPGA is to determine according to the clock frequency of input pixel clock frequency, output clock dot frequency and monokaryon.First by inputting and output pixel clock frequency is determined highest frequency CLK, then see the multiple relation of the upper limit working clock frequency of this highest frequency and single convergent-divergent core, according to this relation, determine the number of convergent-divergent core.
When definite convergent-divergent check figure order, the relation of pixel clock frequency, output pixel clock frequency and monokaryon clock frequency of now inputting according to judgement is determined.First, highest frequency (Pixel Clock) CLK of judgement input and output pixel clock, CLK=Max (Clk
in, Clk
out)), then see the multiple relation of the upper limit working clock frequency of this highest frequency and single convergent-divergent core, according to this multiple relation, determine the quantity of convergent-divergent core, the upper limit working clock frequency of single convergent-divergent core and convergent-divergent check figure object product are can not be less than (being more than or equal to) this highest frequency.
That is to say, if input pixel clock frequency CLK
in, output pixel clock frequency CLK
out, after comparing, obtain pixel clock highest frequency CLK=max{CLK
in, CLK
out, the upper limit working clock frequency of single convergent-divergent core is CLK
smax, convergent-divergent check figure order n is positive integer, and n>=CLK/CLK
smax.
(3), according to the number of described convergent-divergent core, described raw video image Data Segmentation is become to the image subblock consistent with convergent-divergent check figure order.By the preliminary treatment segmentation step in this process, the raw video image data of input FPGA are carried out to even partition like this, obtained the image subblock consistent with convergent-divergent nuclear volume.
Above-mentioned steps is all to prepare for processing image subblock parallel processing by convergent-divergent core.
(4) view data after cutting apart is stored in buffer, buffer is herein Double Data Rate synchronous DRAM (Double Data Rate SDRAM, i.e. DDRSDRAM).
The real time processing system of video image need to have certain data throughout, and this not only requires system to have certain computing capability, also requires system will have certain data buffer storage ability.Reasonably data buffer storage mode not only can improve the treatment effeciency of algorithm, also can reduce the requirement to the data throughout of system cache and capacity, and Double Data Rate synchronous DRAM (DDRSDRAM) has well met requirement herein.
The convergent-divergent algorithm of video image is actually according to the process of the pixel value of each point in image after the calculated for pixel values convergent-divergent of each point in original image.Its essence is the mapping relations between a kind of set, as shown in Fig. 6 (a) and Fig. 6 (b), in figure, solid dot represents the pixel in original image, and hollow dots represents pixel to be solved.
(5) data in buffer are turned back in fpga chip and processed, each image subblock after cutting apart carries out convergent-divergent processing via a convergent-divergent core respectively, and described convergent-divergent is processed parallel running in each convergent-divergent core, as shown in Figure 3.By the exchanges data and the storage of having shared mass data information in convergent-divergent process of FPGA and buffering area.According to adopted convergent-divergent algorithm, after obtaining the DID of corresponding line number, carry out the computing of multi-channel parallel convergent-divergent.Wherein, by FPGA and Double Data Rate synchronous DRAM (Double Data Rate SDRAM), be the storage that exchanges data between DDR SDRAM completes mass data information in convergent-divergent process.
(6) all image subblocks after convergent-divergent are spliced to processing, obtain the digital video image after convergent-divergent.By driver module, through VGA or DVI interface, outputed on large-screen display equipment.
The present invention adopts moderate performance, lower-cost low and middle-end fpga chip to carry out the processing of multi-core parallel concurrent zooming digital video image, reach and be not strict with under the condition of chip performance and external environment condition, take resource few, on hardware attainable object, the block diagram of whole system is as shown in Figure 2.This programme can in, in the system of low complex degree, realize the real-time convergent-divergent of digital video image, and can be according to chip disposal ability dynamic-configuration convergent-divergent nuclear volume, thereby the real-time convergent-divergent that makes digital video image can be on common hardware platform high-efficiency operation, reduce and calculate clock frequency, reduced system cost simultaneously.
embodiment 2:
In the present embodiment, convergent-divergent core, when selecting its required quantity, is selected the convergent-divergent core of minimal number, input pixel clock frequency CLK
in, output pixel clock frequency CLK
out, after comparing, obtain pixel clock highest frequency CLK=max{CLK
in, CLK
out, the upper limit working clock frequency of single convergent-divergent core is CLK
smax, convergent-divergent check figure order n is positive integer, works as CLK/CLK
smaxduring for integer, n=CLK/CLK
smax; Work as CLK/CLK
smaxduring for non-integer, n=[CLK/CLK
smax]+1, [] represents rounding operation.
In addition in the present embodiment, adopt, the method for longitudinal even partition during to described raw video image Data Segmentation.Because display is worked according to raster scan (raster scan) mode, pixel is according to exporting successively from order left to bottom right.In the present embodiment, according to the feature of raster scan mode, video image is carried out longitudinally evenly dividing, as shown in Figure 4, longitudinal division of video image can effectively reduce the data volume that needs buffer memory after each image subblock convergent-divergent, and can reduce the delay between inputted video image and output video image, improve the real-time of panntographic system.
Further, the dividing method of image is relevant to adopted convergent-divergent algorithm.Convergent-divergent described in the present embodiment is processed and is adopted bilinear interpolation algorithm, the pixel value for the treatment of solution point is only relevant to 4 original image vegetarian refreshments around it, therefore carrying out when image is cut apart, adopting preliminary treatment dividing method as shown in Figure 5, after being longitudinal even partition, each sub-block after cutting apart on the basis of even partition line, to after external expansion one row as the image subblock after cutting apart.Thereby guarantee each image subblock after cutting apart calculating during until solution point required pixel pixel value exist, and need to when processing, again not copy edge, reduce the complexity of processing.
embodiment 3:
A device that uses the real-time scaling method of parallel multi-core FPGA digital picture described in embodiment 1 or 2, comprises
Input module: adopt the SiI1161 chip of Silicon Image company to obtain pending raw video image data, described raw video image data are inputted to the Spartan-6XC6SLX100 model fpga chip that Xilinx company produces;
Convergent-divergent core computing module: determine convergent-divergent check figure order according to the upper limit working clock frequency of input pixel clock frequency, output pixel clock frequency and single convergent-divergent core;
Cut apart module: according to the number of described convergent-divergent core, each image subblock after described raw video image data are cut apart and cut apart;
Memory module: the view data after cutting apart is stored in outside DDR buffer, and its model is the MT47H32M16-25 of Micron company;
Zoom module: the data in buffer are turned back in fpga chip and processed, each image subblock after cutting apart carries out convergent-divergent processing through a convergent-divergent core, by exchanges data and the storage of having shared mass data information in convergent-divergent process of FPGA and buffering area;
Splicing output module: all image subblocks after convergent-divergent are spliced to processing, obtain the digital video image after convergent-divergent, export display to through the SiI164 of Silicon Image company.
In this device, first by FPGA, carry out image and cut apart, then deposit the data after cutting apart in buffer area buffer memory, then the image that the information in buffer area is turned back to after cutting apart in FPGA is processed.Compared with prior art, save follow-up graphics processing unit, by FPGA, realized two functions cutting apart and process, greatly reduced system cost.In addition, and in this programme, image is processed and all in same FPGA, is carried out, need to parallel running in independent a plurality of chips, therefore, without considering synchronous problem, reduced the complexity of system.Scheme of the present invention, by multi-core parallel concurrent treatment technology, preferably balance system processing power and the zooming digital video image algorithm contradiction between higher to throughput, requirement of real-time, not only reduced the calculating clock frequency of panntographic system, also reduced system cost, improved system treatment effeciency, the high-throughput of digital video image, high real-time application have been had to certain directive function simultaneously.In addition, in this scheme, adopt moderate performance, lower-cost low and middle-end fpga chip to carry out the processing of multi-core parallel concurrent zooming digital video image, reach and be not strict with under the condition of chip performance and external environment condition, take resource few, on hardware attainable object.
embodiment 4:
The real-time scaling method of parallel multi-core FPGA digital picture in above-described embodiment and device are applicable to image being dwindled or amplifying processing.Provide one below and image is amplified to the embodiment processing.
On the fpga chip that to take 1280 * 720 SD digital videos in the present embodiment be XC6SLX100 in model, adopt bilinear interpolation algorithm to be enlarged into 1920 * 1080 high-definition digital videos.
From the picture size of input and output, now input pixel clock frequency Clk
in=74.250MHz, output pixel clock frequency Clk
out=148.500MHz.Be pixel clock highest frequency CLK=148.500MHz.By designing and verifying, learn that on fpga chip, adopting the maximum clock frequency that bilinear interpolation algorithm can reach is 120MHz, 120MHZ herein by experiment emulation obtains, and on Altera Cyclone III3C120 platform, carries out emulation.Main parameters has every pixel ten bits, a Color Channel, logic chip 571, the amplifier that register is 237,39 * 9, the amplifier of 8 18 * 18.On this platform, emulation draws and should use the clock frequency that is greater than 120MHZ.
That is, the upper limit working clock frequency Clk of single in the case convergent-divergent core
smax=120MHz.Due to CLK<Clk
smaxtherefore <2*CLK, at least needs to adopt the convergent-divergent computing that walks abreast of 2 convergent-divergent cores.
Specific implementation step is as follows:
The first step: video acquisition module gathers input video by VGA or DVI interface, obtains pending raw video image data.
Second step: by the original number vedio data input FPGA collecting, when carrying out preliminary treatment and cut apart, determine the complexity of multiplication factor and convergent-divergent algorithm by the input size of raw video image and the size of output video image.Determine that multiplication factor is that convergent-divergent core has zoom function to be needed could work after given parameters in order to provide parameter to convergent-divergent core.The complexity of determining convergent-divergent algorithm can be determined the number of needed convergent-divergent core.Meanwhile, according to the upper limit working clock frequency of single convergent-divergent core, can judge and need to adopt the convergent-divergent computing that walks abreast of 2 convergent-divergent cores.
The method that image preliminary treatment is cut apart is relevant to adopted convergent-divergent algorithm, in this example, only take " bilinear interpolation convergent-divergent algorithm " set forth the process that its image preliminary treatment is cut apart as example.In " bilinear interpolation convergent-divergent algorithm ", after convergent-divergent, in image, treat that 4 pixel pixel values that the pixel value of solution point closes on to it are relevant, each sub-block after Video Image Segmentation will be on the marginal basis of even partition, again to external expansion one row, therefore, above-mentioned video image should longitudinally be divided into 2 sub-blocks according to the pretreatment mode shown in Fig. 4.
The 3rd step: owing to treating in bilinear interpolation that solution point pixel value is relevant to the pixel value of 4 pixels around it, so can start parallel convergent-divergent computing after DID two row after being cut apart.
What parallel convergent-divergent algorithm herein adopted is bilinear interpolation.First according to the pixel distribution of output, determine its position in input picture.For example, the image of one 4 * 3 is enlarged into 5 * 4 image, output image is as shown in Fig. 7 (a), and input picture, as shown in Fig. 7 (b), has provided the pixel correspondence position (all the other positions same shown in) of output image in input picture in Fig. 7 (c).In figure, black color dots is pixel value to be solved.By Fig. 7 (c), it can be calculated by four pixel values around as seen, can find out after input two row and can carry out computing simultaneously.Take first point is example, and as shown in Fig. 7 (d), it is divided into four regions by the pixel region in four known input pictures, is respectively (1) (2) (3) (4), and four pixels use respectively 1,2,3,4 to represent.The value of required pixel is: the area of the pixel value of area+4 of the pixel value of area+3 of the pixel value of area+2 of 1 pixel value * (4) * (3) * (2) * (1).This convergent-divergent algorithm is bilinear interpolation algorithm.
" parallel convergent-divergent computing " is herein that the Image Parallel after two being cut apart in two independent convergent-divergent cores is processed in the present embodiment.
Wherein, by the exchanges data between FPGA and Double Data Rate synchronous DRAM (Double Data Rate SDRAM, i.e. DDR SDAM) and storage and the calculating of having shared mass data information in convergent-divergent process.In the present embodiment, use the storage of DDR module (DDR SDAM) achieve frame.First carry out the collection of image, be entered into FPGA module (this module comprises convergent-divergent core), because the screen-refresh frequency before and after input and output in Zoom module may have difference a little, several hertz of the large zero points of input ratio output, so just can utilize DDR module first to store, if will not catch up with the speed of input without storage output, there is entanglement in the zoomed image of exporting after continuous multiple frames.While carrying out convergent-divergent, from DDR module, obtain the Zoom module that data are input in FPGA and carry out convergent-divergent, during convergent-divergent, utilize foregoing bilinear interpolation algorithm, need a few row data just from DDR module, read several row.Direct output after convergent-divergent completes, does not need again to turn back in DDR module.
The 4th step: processing is spliced to through bilinear interpolation enlarged image in each road, thereby obtain the digital video image after convergent-divergent.Final by display driver, through VGA or DVI interface, output on large-screen display equipment.
As the execution mode that can replace, common convergent-divergent algorithm has bilinear interpolation algorithm used in the present invention and minimum neighborhood interpolation algorithm.As previously described, its advantage is that algorithm complex is lower and be easy to realize in the concrete operations of bilinear interpolation algorithm, and shortcoming is that it is similar to a low pass filter, and high fdrequency component is removed, and causes edge blurry.If adopting minimum neighborhood interpolation method to select the gray value of the nearest input pixel in the position that is mapped to from it is interpolation result.Advantage is that amount of calculation is very little, and algorithm is also simple, so arithmetic speed is very fast.But it only uses the gray value as this sampled point from the gray value of the nearest pixel of sampled point to be measured, and do not consider the impact of other neighbor pixels, thereby gray value has obvious discontinuity after resampling, image quality loss is larger, can produce obvious mosaic and crenellated phenomena.Bilinear interpolation effect is better than arest neighbors interpolation, just amount of calculation is slightly larger, algorithm is complicated, program runtime is also a little longer, but after convergent-divergent, picture quality is high, substantially overcome the discontinuous feature of arest neighbors interpolation gray value, because it has considered sampled point to be measured four direct adjoint points correlation impact on this sampled point around.
embodiment 5:
In the present embodiment, providing one adopts the real-time scaling method of parallel multi-core FPGA digital picture and device in the present invention to carry out the concrete application example that image dwindles.On the fpga chip that is XC6SLX100 by 1920 * 1080 high-definition digital videos in model in the present embodiment, adopt bilinear interpolation algorithm to be reduced into 1280 * 720 SD digital videos.
From the picture size of input and output, now input pixel clock frequency Clk
in=148.500MHz, output pixel clock frequency Clk
out=74.250MHz.Be pixel clock highest frequency CLK=148.500MHz.By designing and verifying, learn that on fpga chip, adopting the maximum clock frequency that bilinear interpolation algorithm can reach is 120MHz, that is, and the upper limit working clock frequency Clk of single in the case convergent-divergent core
smax=120MHz.Due to CLK<Clk
smax<2*CLK, known, at least need to adopt the convergent-divergent computing that walks abreast of 2 convergent-divergent cores.
The real-time scaling method of parallel multi-core FPGA digital picture in the present embodiment, specific implementation step is as follows:
The first step: video acquisition module gathers input video by VGA or DVI interface, obtains pending raw video image data.
Second step: by the original number vedio data input FPGA collecting, preliminary treatment is wherein cut apart module and by the input size of raw video image and the size of output video image, is determined the complexity of multiplication factor and convergent-divergent algorithm, meanwhile, according to the upper limit working clock frequency of single convergent-divergent core, can judge and need to adopt the convergent-divergent computing that walks abreast of 2 convergent-divergent cores.
The method that image preliminary treatment is cut apart is relevant to adopted convergent-divergent algorithm, in this example, can adopt minimum neighborhood interpolation method, and selecting the gray value of the nearest input pixel in the position that is mapped to from it is interpolation result.The advantage of this algorithm is that amount of calculation is very little, and algorithm is also simple, so arithmetic speed is very fast.But it only uses the gray value as this sampled point from the gray value of the nearest pixel of sampled point to be measured, and do not consider the impact of other neighbor pixels, thereby gray value has obvious discontinuity after resampling, image quality loss is larger, can produce obvious mosaic and crenellated phenomena.
As other execution mode, also can adopt the bilinear interpolation in above-described embodiment 4, identical with the account form of above-described embodiment 4.
The 3rd step: by FPGA and Double Data Rate synchronous DRAM (Double Data Rate SDRAM, be DDR SDRAM) between exchanges data with shared storage and the calculating of mass data information in convergent-divergent process, this process is identical with above-described embodiment 4.
The 4th step: the image that each road is dwindled through bilinear interpolation splices processing, thereby obtains the digital video image after convergent-divergent.Final by display driver, through VGA or DVI interface, output on large-screen display equipment.
Obviously, above-described embodiment is only for example is clearly described, and the not restriction to execution mode.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description.Here exhaustive without also giving all execution modes.And the apparent variation of being extended out thus or change are still among the protection range in the invention.
Claims (10)
1. the real-time scaling method of parallel multi-core FPGA digital picture, is characterized in that: the method comprises following process:
(1) obtain pending raw video image data, by described raw video image data input fpga chip;
(2) according to the upper limit working clock frequency of input pixel clock frequency, output pixel clock frequency and single convergent-divergent core, determine convergent-divergent check figure order;
(3), according to the number of described convergent-divergent core, by described raw video image data, by being longitudinally evenly divided into the image subblock consistent with convergent-divergent check figure order, any one edge, the image subblock left and right sides all needs to external expansion one row;
(4) view data after cutting apart is stored in external cache device;
(5) view data in described external cache device is read in fpga chip and processed line by line, each image subblock after cutting apart is independently used a convergent-divergent core to carry out convergent-divergent processing, the parallel running of described convergent-divergent core;
(6) all image subblocks after convergent-divergent are according to pixels put and spliced line by line processing, obtain the digital video image after convergent-divergent.
2. the real-time scaling method of parallel multi-core FPGA digital picture according to claim 1, is characterized in that: the described upper limit working clock frequency according to input pixel clock frequency, output pixel clock frequency and single convergent-divergent core determines that convergent-divergent check figure object process comprises: obtain input pixel clock frequency CLK
inwith output pixel clock frequency CLK
out, after comparing, obtain pixel clock highest frequency CLK=max{CLK
in, CLK
out, the upper limit working clock frequency of single convergent-divergent core is CLK
smax, convergent-divergent check figure order n is positive integer, and n>=CLK/CLK
smax.
3. the real-time scaling method of parallel multi-core FPGA digital picture according to claim 2, is characterized in that: the upper limit working clock frequency CLK of described pixel clock highest frequency CLK and single convergent-divergent core
smax, work as CLK/CLK
smaxduring for integer, n=CLK/CLK
smax; Work as CLK/CLK
smaxduring for non-integer, n=[CLK/CLK
smax]+1.
4. according to the real-time scaling method of parallel multi-core FPGA digital picture described in claim 1 or 2 or 3, it is characterized in that: described convergent-divergent is processed and adopted bilinear interpolation algorithm.
5. the real-time scaling method of parallel multi-core FPGA digital picture according to claim 4, is characterized in that: the method that adopts even partition during to described raw video image Data Segmentation.During to described raw video image Data Segmentation, adopt the method for longitudinal even partition.
6. the real-time scaling method of parallel multi-core FPGA digital picture according to claim 5, is characterized in that: described even partition is longitudinal even partition.
7. the real-time scaling method of parallel multi-core FPGA digital picture according to claim 5, is characterized in that: each sub-block after cutting apart on the basis of even partition line, to after external expansion one row as the image subblock after cutting apart.
8. according to the real-time scaling method of parallel multi-core FPGA digital picture described in claim 1 or 2 or 3 or 5 or 6, it is characterized in that: described external cache device is Double Data Rate synchronous DRAM.
9. according to the real-time scaling method of parallel multi-core FPGA digital picture described in claim 1 or 2 or 3 or 5 or 6, it is characterized in that: the pixel of described raw video image data adopts and exports successively from order left to bottom right.
10. a device for the real-time scaling method of parallel multi-core FPGA digital picture described in right to use requirement 1-9, is characterized in that: comprise
Input module: obtain pending raw video image data, by described raw video image data input fpga chip;
Convergent-divergent core computing module: determine convergent-divergent check figure order according to the upper limit working clock frequency of input pixel clock frequency, output pixel clock frequency and single convergent-divergent core;
Cut apart module: according to the number of described convergent-divergent core, each image subblock after described raw video image data are cut apart and cut apart;
Memory module: the view data after cutting apart is stored in buffer;
Zoom module: the data in buffer are turned back in fpga chip and processed, each image subblock after cutting apart carries out convergent-divergent processing through a convergent-divergent core, by exchanges data and the storage of having shared mass data information in convergent-divergent process of FPGA and buffering area;
Splicing output module: all image subblocks after convergent-divergent are spliced to processing, obtain the digital video image after convergent-divergent.
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