CN104219529B - Image-scaling method, system and device - Google Patents
Image-scaling method, system and device Download PDFInfo
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Abstract
The invention discloses a kind of image-scaling method, system and device, the method includes：Picture signal is written at least N number of input buffer module as unit of frame, wherein, the frame image signal in adjacent N frame image signals is written in one input buffer module, and N is the positive integer obtained by ratio carry rounding of the pixel clock of described image signal with scaling clock frequency；Each frame image signal is read from least N number of input buffer module respectively by least N number of scaling processing module, and every frame image signal of reading is scaled accordingly respectively；Each frame image signal after scaling is respectively written at least N number of output buffer module.The method, system and device for implementing the present invention, can scale the image of the above resolution ratio of ultra high-definition in real time, without improving signal scaling processing device performance, can reduce image scaling cost, be not necessarily to cutting image signal in addition, image play quality can be improved.
Description
Technical field
The present invention relates to signal processing technology fields, more particularly to a kind of image-scaling method, system and device.
Background technology
Resolution ratio is ultra high-definition resolution ratio (the Ultra High- of 4k (3840x2160), 8k (7680x4320) etc.
Definition) image, a picture carries huge information content, while the details inside picture is very clear.Ultra high-definition
Image in different resolution bandwidth is usually twice or more of normal resolution image.
In order to the phenomenon that interim card do not occur after ensureing video signal scaling, can by by input picture transversely or longitudinally
Multiple portions are divided into, are handled using multichannel scaling channel.
But above-mentioned processing method needs to synchronize multiple scaling channels, and the edge of image segmentation is by contracting
It is remerged after putting and will appear incoherent phenomenon, image play quality can be reduced.
Invention content
Based on this, it is necessary to for the problem that above-mentioned image zoom processing method, image play quality can be reduced, provide one
Kind image-scaling method, system and device.
A kind of image-scaling method, includes the following steps：
Picture signal is written at least N number of input buffer module as unit of frame, wherein each input buffer module
The frame image signal in adjacent N frame image signals is written, N is the pixel clock and scaling clock frequency of described image signal
Ratio carry rounding obtained by positive integer；
Each frame image signal is read from least N number of input buffer module respectively by least N number of scaling processing module,
And every frame image signal of reading is scaled accordingly respectively, wherein each scaling processing module reads the phase
The clock frequency of a frame image signal in adjacent N frame image signals, each scaling processing module is the scaling clock
Frequency；
Each frame image signal after scaling is respectively written at least N number of output buffer module, wherein each output is slow
The frame image signal in the adjacent N frame image signals is written in storing module.
A kind of image scaling system, including：
Input module, for picture signal to be written at least N number of input buffer module as unit of frame, wherein Mei Gesuo
The frame image signal that input buffer module is written in adjacent N frame image signals is stated, N is the pixel clock of described image signal
The positive integer obtained by ratio carry rounding with scaling clock frequency；
Zoom module, for being read respectively from least N number of input buffer module by least N number of scaling processing module
Each frame image signal, and every frame image signal of reading is scaled accordingly respectively, wherein each scaling processing mould
Block reads the frame image signal in the adjacent N frame image signals, and the clock frequency of each scaling processing module is
The scaling clock frequency；
Output module, for each frame image signal after scaling to be respectively written at least N number of output buffer module, wherein
The frame image signal in the adjacent N frame image signals is written in each output buffer module.
A kind of image scaling device, including at least N number of input buffer module, at least N number of scaling processing module and at least N number of
Output buffer module, N are the ratio carry of the pixel clock of picture signal and the scaling clock frequency of the scaling processing module
Positive integer obtained by rounding, wherein：
Each input buffer module is used to cache the frame image signal in adjacent N frame image signals；
Each scaling processing module from any one input buffer module for reading in the adjacent N frame image signals
A frame image signal, and every frame image signal of reading is scaled accordingly respectively；
Each output buffer module is used to cache the adjacent N frame images after any one scaling processing module scaling
A frame image signal in signal.
At least N number of input-buffer mould is written in picture signal by above-mentioned image-scaling method, system and device as unit of frame
The frame image signal in adjacent N frame image signals is written in block, an input buffer module, and N is to described image signal
Pixel clock and the ratio of scaling clock frequency carry out the positive integer obtained by carry rounding, pass through at least N number of scaling processing module
Each frame image signal is read from least N number of input buffer module respectively, and every frame image signal of reading is carried out respectively
Corresponding scaling finally will be respectively written at least N by each frame image signal after at least N number of scaling processing module scaling
A output buffer module.The image that the above resolution ratio of ultra high-definition can be scaled in real time can be reduced without improving signal processor performance
Image scaling cost is not necessarily to cutting image signal, image play quality can be improved in addition.
Description of the drawings
Fig. 1 is the flow diagram of image-scaling method first embodiment of the present invention；
Fig. 2 is the schematic diagram of the field duration in image-scaling method of the present invention；
Fig. 3 is the flow diagram of image-scaling method second embodiment of the present invention；
Fig. 4 is the structural schematic diagram of image scaling system first embodiment of the present invention；
Fig. 5 is the structural schematic diagram of image scaling device first embodiment of the present invention.
Specific implementation mode
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Referring to Fig. 1, Fig. 1 is the flow diagram of the image-scaling method first embodiment of the present invention.
The described image Zoom method of present embodiment includes the following steps：
At least N number of input buffer module is written in picture signal by step S101 as unit of frame, wherein each described defeated
Enter the frame image signal that cache module is written in adjacent N frame image signals, N is pixel clock and the contracting of described image signal
Put the positive integer obtained by the ratio carry rounding of clock frequency.
Step S102 reads each frame from least N number of input buffer module respectively by least N number of scaling processing module
Picture signal, and every frame image signal of reading is scaled accordingly respectively, wherein each scaling processing module is read
The frame image signal in the adjacent N frame image signals is taken, the clock frequency of each scaling processing module is described
Scale clock frequency.
Each frame image signal after scaling is respectively written at least N number of output buffer module by step S103, wherein each
The frame image signal in the adjacent N frame image signals is written in the output buffer module.
At least N number of input-buffer is written in picture signal by the image-scaling method described in present embodiment as unit of frame
The frame image signal in adjacent N frame image signals is written in module, an input buffer module, and N is to described image signal
Pixel clock with scaling clock frequency ratio carry out carry rounding obtained by positive integer, pass through at least N number of scaling processing mould
Block reads each frame image signal from at least N number of input buffer module respectively, and respectively to every frame image signal of reading into
The corresponding scaling of row, finally by by each frame image signal after at least N number of scaling processing module scaling be respectively written into
Few N number of output buffer module.The image that the above resolution ratio of ultra high-definition can be scaled in real time can without improving signal processor performance
Image scaling cost is reduced, cutting image signal is not necessarily in addition, image play quality can be improved.
Wherein, for step S101, an input buffer module can be that capacity is depositing for a frame image signal in memory
Storage area domain.Described image signal is preferably video signal.The scaling clock frequency is to be carried out to described image signal
The clock frequency of the scaling processing module of scaling processing.
Preferably, the sequence of predeterminable each input buffer module write-in picture signal, such as：To each caching input-buffer
Module sorts, and according to the field duration of picture signal, each input buffer module is written in each frame image signal by cycle.
As shown in Fig. 2, each field duration inputs a frame image signal, 1 corresponding picture signal of input frame is written N 4
Second input buffer module is written in 2 corresponding picture signal of input frame by first input buffer module, and input frame 3 is right
The picture signal write-in third input buffer module answered, the 4th input-buffer is written by 4 corresponding picture signal of input frame
Then module recirculates, first input buffer module is written in 5 corresponding picture signal of input frame again, and input frame 6 is right
Second input buffer module is written in the picture signal answered again, and cycle carries out until the corresponding picture signals of input frame N are written
Corresponding input buffer module.
In one embodiment, described the step of picture signal is written as unit of frame at least N number of input buffer module
Before, further comprising the steps of：
Described image signal is decoded, frequency reducing and bit wide are widened.
Preferably, described image signal can be decoded by video decoding chip, frequency reducing and bit wide are widened.
In another embodiment, the step of picture signal is written at least N number of input buffer module as unit of frame is wrapped
Include following steps：
Obtain the field duration of described image signal.
According to the field duration, described image signal is written at least N number of input-buffer mould as unit of frame successively
Block.
For step S102, corresponding scaling includes zooming in or out.The scaling processing module is preferably to use
In the processor for carrying out image scaling, clock frequency is the scaling clock frequency.When each scaling processing module has scaled
After a frame image signal in adjacent N frame image signals, a kind of image in next group of adjacent N frame image signal can be read
Signal zooms in and out, and next group of adjacent N frame image will not be made capped.
Preferably, the correspondence between predeterminable each scaling processing module and each input buffer module, such as：To each
Image processing module sorts, and according to the field duration of picture signal, cycle reads each frame image signal and scales.
In one embodiment, as shown in Fig. 2, each field duration inputs a frame image signal, input frame 1 to input frame n
Input of the 1st frame to n-th frame picture signal is corresponded to respectively, and output frame 1 to output frame n corresponds to the 1st frame to n-th frame image respectively to be believed
Number output.N be after the 4, the 1st input frame 4 field duration just have the 1st output frame.First scaling processing module reads first
The 1 corresponding picture signal of input frame of a input buffer module write-in simultaneously scales, and second scaling processing module reads second
The 2 corresponding picture signal of input frame of input buffer module write-in simultaneously scales, and it is defeated that third scaling processing module reads third
Enter the 3 corresponding picture signal of input frame of cache module write-in and scale, the 4th scaling processing module reads the 4th input
The 4 corresponding picture signal of input frame of cache module write-in simultaneously scales, and then recirculates, and first scaling processing module is read
The 5 corresponding picture signal of input frame of first input buffer module write-in simultaneously scales, and second scaling processing module reads the
The 6 corresponding picture signal of input frame of two input buffer modules write-in simultaneously scales, and cycle carries out until the corresponding figures of input frame N
As signal.
For step S103, N number of output buffer module can correspond to N number of scaling processing module and read adjacent N frame figures respectively
As signal.
As shown in Fig. 2, each field duration inputs a frame image signal, N 4, after 1 corresponding scaling processing of input frame
First output buffer module is written in picture signal, and the picture signal after 2 corresponding scaling processing of input frame is written second
Picture signal after 3 corresponding scaling processing of input frame is written third output buffer module, will inputted by output buffer module
The 4th output buffer module is written in picture signal after 4 corresponding scaling processing of frame, then recirculates, and input frame 5 is right
First output buffer module is written in picture signal after the scaling processing answered again, after 6 corresponding scaling processing of input frame
Second output buffer module is written in picture signal again, and cycle carries out until by the image after the corresponding scaling processings of input frame N
Corresponding output buffer module is written in signal.
In one embodiment, each frame image signal after scaling is being respectively written at least N number of output buffer module
It is further comprising the steps of after step：
Each frame image signal is read from least N number of output buffer module.
Each frame image signal is encoded, and each frame image signal after coding is output to display end.
Preferably, output scheduling module can by field duration sequencing successively from N number of output buffer module read scaling after
Picture signal.
Referring to Fig. 3, Fig. 3 is the flow diagram of the image-scaling method second embodiment of the present invention.
The described image Zoom method of present embodiment and first embodiment difference lies in：With 3840x2160@60Hz
Image scaling for, since 3840x2160 60Hz are 4 times of bandwidth of normal resolution image or more, pixel clock reaches
To 594MHz, N 4, scaling processing module is 4, input buffer module is 4, and output buffer module is 4, input/output
Buffer memory capacity is 4 frames.Scaling processing module can be more than the programmable logic of 148.5MHz (594/4=148.5) by working frequency
Device realizes that input/output cache module can be realized by plug-in DDR memory.
Preferably, the clock of ultra high-definition image in different resolution signal is higher, general to support ultra high-definition vision signal input and output
Codec chip can by pixel clock frequency reduce simultaneously data bit width increase, 3840x2160@60Hz, pixel clock
594MHz, the vision signal of 24 bit wides can switch to the pixel clock of 148.5Mhz, data bit width after video decoding chip
Become 96, i.e., a clock exports 4 pixels, and video coding chip can also support the input of 4 pixels of a clock.
Present embodiment may include following steps：
Step S301 is decoded the video signal of input, frequency reducing and bit wide are widened.
Step S302, according to the field duration of the video signal of input by vision signal by frame sequential successively recurrent wrIting
To 4 input buffer modules.
Step S303 reads vedio data from corresponding input buffer module simultaneously by 4 scaling processing modules,
Corresponding output buffer module is written after scaling.
Step S304, after the completion of first frame scale image signals are handled, by the field duration from 4 output buffer modules according to
The secondary vedio data read after scaling.
The vedio data read from output buffer module is input into row Video coding, and is output to by step S305
Display terminal completes the scaling of image.
Present embodiment can scale the video image of the above resolution ratio of ultra high-definition, without improving signal processor in real time
Can, image scaling cost can be reduced, cutting image signal is not necessarily in addition, video playing quality can be improved.
Is worked at the same time by frequency and is only slightly larger than since scaling processing module input and output bit wide is 24 by step S303
148.5MHz, so each scaling processing module scales a frame image data and needs 4 field duration, as shown in Fig. 2, input frame 1
Need can just have output frame 1 after 4 field duration, and by 4 field duration just again to the same input buffer module
Input frame is written, so each Zoom module has the processing that time enough completes signal.
For step S305, Video coding can be read from output buffer module by output scheduling module.
Referring to Fig. 4, Fig. 4 is the structural schematic diagram of the image scaling system first embodiment of the present invention.
The described image panntographic system of present embodiment may include input module 100, Zoom module 200 and output module
300, wherein：
Input module 100, for picture signal to be written at least N number of input buffer module as unit of frame, wherein each
The frame image signal in adjacent N frame image signals is written in the input buffer module, when N is the pixel of described image signal
Positive integer obtained by ratio carry rounding of the clock with scaling clock frequency.
Zoom module 200, for passing through at least N number of scaling processing module respectively from least N number of input buffer module
Each frame image signal is read, and every frame image signal of reading is scaled accordingly respectively, wherein at each scaling
Reason module reads the frame image signal in the adjacent N frame image signals, the clock frequency of each scaling processing module
Rate is the scaling clock frequency.
Output module 300, for each frame image signal after scaling to be respectively written at least N number of output buffer module,
In, the frame image signal in the adjacent N frame image signals is written in each output buffer module.
At least N number of input-buffer is written in picture signal by the image-scaling method described in present embodiment as unit of frame
The frame image signal in adjacent N frame image signals is written in module, an input buffer module, and N is to described image signal
Pixel clock with scaling clock frequency ratio carry out carry rounding obtained by positive integer, pass through at least N number of scaling processing mould
Block reads each frame image signal from at least N number of input buffer module respectively, and respectively to every frame image signal of reading into
The corresponding scaling of row, finally by by each frame image signal after at least N number of scaling processing module scaling be respectively written into
Few N number of output buffer module.The image that the above resolution ratio of ultra high-definition can be scaled in real time can without improving signal processor performance
Image scaling cost is reduced, cutting image signal is not necessarily in addition, image play quality can be improved.
Wherein, for input module 100, described image signal is preferably video signal.The scaling clock frequency
Rate is the clock frequency for the scaling processing module that processing is zoomed in and out to described image signal.
Preferably, the sequence of predeterminable each input buffer module write-in picture signal, such as：To each caching input-buffer
Module sorts, and according to the field duration of picture signal, each input buffer module is written in each frame image signal by cycle.
In one embodiment, as shown in Fig. 2, each field duration inputs a frame image signal, input frame 1 to input frame n
Input of the 1st frame to n-th frame picture signal is corresponded to respectively, and output frame 1 to output frame n corresponds to the 1st frame to n-th frame image respectively to be believed
Number output.N be after the 4, the 1st input frame 4 field duration just have the 1st output frame.Input module 100 can be used for：
First input buffer module is written into 1 corresponding picture signal of input frame, by 2 corresponding picture signal of input frame
Second input buffer module is written, third input buffer module is written into 3 corresponding picture signal of input frame, by input frame
The 4th input buffer module is written in 4 corresponding picture signals, then recirculates, again by 5 corresponding picture signal of input frame
Be written first input buffer module, second input buffer module is written into 6 corresponding picture signal of input frame again, recycle into
Row by the corresponding picture signals of input frame N until be written corresponding input buffer module.
In one embodiment, further include decoder module, for being decoded to described image signal, frequency reducing and bit wide are opened up
It is wide.
Preferably, described image signal can be decoded by video decoding chip, frequency reducing and bit wide are widened.
In another embodiment, input module 100 can be additionally used in the field duration for obtaining described image signal；According to described
At least N number of input buffer module is written in described image signal by the field duration as unit of frame successively.
For Zoom module 200, the scaling processing module is preferably used for carrying out the processor of image scaling, at that time
Clock frequency is the scaling clock frequency.When each scaling processing module has scaled the frame figure in adjacent N frame image signals
As after signal, a kind of picture signal that can be read in next group of adjacent N frame image signal zooms in and out, and will not make next group of phase
Adjacent N frame images are capped.
Preferably, the correspondence between predeterminable each scaling processing module and each input buffer module, according to image
The field duration of signal, cycle read each frame image signal and scale.
As shown in Fig. 2, each field duration inputs a frame image signal, N 4, Zoom module 200 can be used for：
First scaling processing module is set to read the 1 corresponding picture signal of input frame of first input buffer module write-in
And scale, so that second scaling processing module is read the 2 corresponding picture signal of input frame of second input buffer module write-in
And scale, so that third scaling processing module is read the 3 corresponding picture signal of input frame of third input buffer module write-in
And scale, so that the 4th scaling processing module is read the 4 corresponding picture signal of input frame of the 4th input buffer module write-in
And scale, it then recirculates, keeps the input frame 5 that first scaling processing module reads the write-in of first input buffer module right
The picture signal and scaling answered keep the input frame 6 that second scaling processing module reads the write-in of second input buffer module right
The picture signal and scaling answered, cycle carries out until the corresponding picture signals of input frame N.
For output module 300, N number of output buffer module can correspond to N number of scaling processing module and read adjacent N frames respectively
Picture signal.
As shown in Fig. 2, each field duration inputs a frame image signal, N 4, output module 300 can be used for：
First output buffer module is written into picture signal after 1 corresponding scaling processing of input frame, input frame 2 is right
Second output buffer module is written in picture signal after the scaling processing answered, by the figure after 3 corresponding scaling processing of input frame
As signal be written third output buffer module, by the picture signal after 4 corresponding scaling processing of input frame be written the 4th it is defeated
Go out cache module, then recirculate, it is slow that first output is written in the picture signal after 5 corresponding scaling processing of input frame again
Second output buffer module is written in picture signal after 6 corresponding scaling processing of input frame by storing module again, and cycle carries out straight
Corresponding output buffer module is written to by the picture signal after the corresponding scaling processings of input frame N.
In one embodiment, further include display module, for reading each frame figure from least N number of output buffer module
As signal.Each frame image signal is encoded, and each frame image signal after coding is output to display end.
Preferably, output scheduling module can by field duration sequencing successively from N number of output buffer module read scaling after
Picture signal.
Referring to Fig. 5, Fig. 5 is the structural schematic diagram of the image scaling device first embodiment of the present invention.
The described image device for zooming of present embodiment may include at least N number of input buffer module 1010 to 10N0, at least N
To 20N0 and at least, for N number of output buffer module 3010 to 30N0, N is the pixel clock of picture signal to a scaling processing module 2010
The positive integer obtained by ratio carry rounding with the scaling clock frequency of scaling processing module 1010 to 10N0, wherein：
At least N number of input buffer module 1010 is to any one in 10N0 for caching in adjacent N frame image signals
A frame image signal.
At least N number of scaling processing module 2010 to any one in 20N0 is used for from least N number of input buffer module
Any one in 1010 to 10N0 reads the frame image signal in the adjacent N frame image signals, and respectively to reading
Every frame image signal scaled accordingly.
At least N number of output buffer module 3010 is to any one in 30N0 for caching at least N number of scaling processing module
The frame image signal in the adjacent N frame image signals after any one scaling in 2010 to 20N0.
Present embodiment, it is slow by least N number of input buffer module, at least N number of scaling processing module and at least N number of output
Storing module can scale the image of the above resolution ratio of ultra high-definition in real time, without improving signal processor performance, can reduce image scaling
Cost is not necessarily to cutting image signal, image play quality can be improved in addition.
Preferably, the resolution ratio of picture signal is 3840x2160@60Hz, since 3840x2160@60Hz are commonly to differentiate
More than 4 times of bandwidth of rate image, pixel clock reaches 594MHz, N 4, and scaling processing module is 4, input buffer module
It it is 4, output buffer module is 4, and input/output buffer memory capacity is 4 frames.
In one embodiment, further include input scheduling module, the input scheduling module is for dispatching at least N number of input
The write-in order of described image signal is written to 10N0 for cache module 1010.
In another embodiment, further include output scheduling module, for from least N number of output buffer module 3010 to
30N0 reads the sequence that picture signal is read in picture signal and scheduling from least N number of output buffer module 3010 to 30N0.
Further, further include be decoded for the signal to input, the decoder module that frequency reducing and bit wide are widened and use
The coding module of coding output is carried out in the picture signal to output buffer module.
Further, can will at least N number of input buffer module 1010 to 10N0, at least N number of scaling processing module 2010
To 20N0 and at least N number of output buffer module 3010 is to 30N0, corresponds, an input buffer module corresponds at a scaling
Manage module and an output buffer module.
Several embodiments of the invention above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
Cannot the limitation to the scope of the claims of the present invention therefore be interpreted as.It should be pointed out that for those of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the guarantor of the present invention
Protect range.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (8)
1. a kind of image-scaling method, which is characterized in that include the following steps：
Picture signal is written at least N number of input buffer module as unit of frame, wherein by current frame image signal write-in the
When N number of input buffer module, using next frame image signal as the object to be written of the 1st input buffer module；It is each described
Input buffer module is written the frame image signal in adjacent N frame image signals, N be described image signal pixel clock with
Scale the positive integer obtained by the ratio carry rounding of clock frequency；Described image signal is believed for ultra high-definition resolution video image
Number；
Each frame image signal is read from least N number of input buffer module respectively by least N number of scaling processing module, and is divided
Other every frame image signal to reading is scaled accordingly, wherein in n-th scaling processing module to current frame image signal
When being read out scaling, using next frame image signal as the scale objects to be read of the 1st scaling processing module；It is each described
Scaling processing module reads the frame image signal in the adjacent N frame image signals, each scaling processing module
Clock frequency is the scaling clock frequency；
Each frame image signal after scaling is respectively written at least N number of output buffer module, wherein by current frame image signal
When n-th input buffer module is written, using next frame image signal as the object to be written of the 1st input buffer module；Often
The frame image signal in the adjacent N frame image signals is written in a output buffer module.
2. image-scaling method according to claim 1, which is characterized in that described that picture signal is written as unit of frame
At least N number of input buffer module the step of before, it is further comprising the steps of：
Described image signal is decoded, frequency reducing and bit wide are widened.
3. image-scaling method according to claim 1, which is characterized in that each frame image signal difference after it will scale
It is further comprising the steps of after the step of at least N number of output buffer module is written：
Each frame image signal is read from least N number of output buffer module；
Each frame image signal is encoded, and each frame image signal after coding is output to display end.
4. image-scaling method as claimed in any of claims 1 to 3, which is characterized in that by picture signal with frame
The step of at least N number of input buffer module is written for unit includes the following steps：
Obtain the field duration of described image signal；
According to the field duration, described image signal is written at least N number of input buffer module as unit of frame successively.
5. a kind of image scaling system, which is characterized in that including：
Input module, for picture signal to be written at least N number of input buffer module as unit of frame, wherein by present frame
When n-th input buffer module is written in picture signal, using next frame image signal as the to be written of the 1st input buffer module
Object；The frame image signal in adjacent N frame image signals is written in each input buffer module, and N believes for described image
Number pixel clock with scaling clock frequency ratio carry rounding obtained by positive integer；Described image signal is differentiated for ultra high-definition
Rate video signal；
Zoom module, for reading each frame from least N number of input buffer module respectively by least N number of scaling processing module
Picture signal, and every frame image signal of reading is scaled accordingly respectively, wherein in n-th scaling processing module pair
When current frame image signal is read out scaling, using next frame image signal as the contracting to be read of the 1st scaling processing module
Be rivals in a contest as；Each scaling processing module reads the frame image signal in the adjacent N frame image signals, each described
The clock frequency of scaling processing module is the scaling clock frequency；
Output module, for each frame image signal after scaling to be respectively written at least N number of output buffer module, wherein inciting somebody to action
When n-th input buffer module is written in current frame image signal, using next frame image signal as the 1st input buffer module
Object to be written；The frame image signal in the adjacent N frame image signals is written in each output buffer module.
6. image scaling system according to claim 5, which is characterized in that further include decoder module, for the figure
As signal is decoded, frequency reducing and bit wide are widened.
7. image scaling system according to claim 5, which is characterized in that further include display module, for from it is described to
Few N number of output buffer module reads each frame image signal；Each frame image signal is encoded, and by each frame image after coding
Signal is output to display end.
8. the image scaling system according to any one of claim 5 to 7, which is characterized in that the input module is also
Field duration for obtaining described image signal；According to the field duration, described image signal is written as unit of frame successively
At least N number of input buffer module.
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