CN106910162A - Image zoom processing method and device based on FPGA - Google Patents
Image zoom processing method and device based on FPGA Download PDFInfo
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Abstract
The invention discloses a kind of image zoom processing method and device based on FPGA, obtain original digital image data, and be put into speed original digital image data is put into FPGA inner buffers with default, original digital image data is read from inner buffer with the default corresponding reading speed of speed that is put into, and according to interpolation algorithm and the original digital image data of reading, interpolation calculation is carried out, obtain image interpolation data, according to image interpolation data, the view data after being scaled.Original digital image data is put into FPGA inner buffers and is cached, without using external memory storage storage, reduce cost, and can be read out from FPGA inner buffers, without being read from external memory storage again, accelerate data reading speed, improve general image scaling efficiency.In addition, reading original digital image data from inner buffer with the default corresponding reading speed of speed that is put into, i.e., digital independent is carried out with reasonably reading speed, it can be ensured that the speed of reading avoids causing very much loss of data slowly due to reading speed, improves scaling treatment effeciency.
Description
Technical field
The present invention relates to technical field of image processing, more particularly to a kind of image zoom processing method and dress based on FPGA
Put.
Background technology
More and more higher is required, it is necessary to zoom in and out treatment to view data with to image data quality, current picture number
According to scaling field, the algorithm of scaling is varied, but is realized by entering row interpolation to original digital image data, main
The interpolation algorithm wanted has：Arest neighbors interpolation algorithm, bilinear interpolation algorithm and cube sum algorithm.Based on interpolation algorithm reality
Existing complexity and final zooming effect consider, and the most of bilinearitys that use of current image data scaling are inserted
Value-based algorithm.
Passing through bilinearity using FPGA (Field-Programmable Gate Array, field programmable gate array)
When interpolation algorithm carries out image data scaling, need to use external memory storage, such as SDRAM (Synchronous Dynamic at present
Random Access Memory, synchronous DRAM), hardware cost is so on the one hand increased, increase wiring difficult
Degree, on the other hand, it is necessary to read data from external memory storage, increases FPGA control logics, reduces fpga logic speed, so that
Data reading speed is reduced, image data scaling efficiency is influenceed, be i.e. image data scaling efficiency is low.
The content of the invention
Based on this, it is necessary to for increase cost and the low problem of scaling efficiency, there is provided one kind reduces cost and raising
Scale the image zoom processing method and device based on FPGA of efficiency.
A kind of image zoom processing method based on FPGA, comprises the following steps：
Obtain original digital image data, and be put into speed the original digital image data is put into FPGA inner buffers with default；
Original digital image data, and root are read from the inner buffer with the default corresponding reading speed of speed that is put into
According to interpolation algorithm and the original digital image data of reading, interpolation calculation is carried out, obtain image interpolation data；
According to described image interpolated data, the view data after being scaled.
A kind of image scaling processing unit based on FPGA, including：
Storage module, for obtaining original digital image data, and is put into speed the original digital image data is put into FPGA with default
Inner buffer；
Image interpolation data acquisition module, for default being put into the corresponding reading speed of speed from the inside with described
Original digital image data is read in caching, and according to interpolation algorithm and the original digital image data of reading, carries out interpolation calculation, obtain image
Interpolated data；
Image data acquisition module after scaling, for according to described image interpolated data, the picture number after being scaled
According to.
Above-mentioned image zoom processing method and device based on FPGA, obtain original digital image data, and be put into speed with default
Original digital image data is put into FPGA inner buffers, original is read from inner buffer with the default corresponding reading speed of speed that is put into
View data, and according to interpolation algorithm and the original digital image data of reading, interpolation calculation is carried out, obtain image interpolation data, root
According to image interpolation data, the view data after being scaled.Cached due to original digital image data is put into FPGA inner buffers, nothing
Need to be stored using external memory storage, reduce hardware cost, and can be from FPGA inner buffers during subsequent read original digital image data
It is read out, without being read from external memory storage again, accelerates data reading speed, so as to general image scaling effect can be improved
Rate.In addition, read original digital image data from inner buffer with the default corresponding reading speed of speed that is put into, i.e., reasonably reading
Take speed to be read out original digital image data, it can be ensured that the speed of reading avoids causing very much loss of data slowly due to reading speed,
Improve scaling treatment effeciency.
Brief description of the drawings
Fig. 1 is the flow chart of the image zoom processing method based on FPGA of an embodiment；
Fig. 2 is the flow chart of the image zoom processing method based on FPGA of another embodiment；
Fig. 3 is bilinear interpolation schematic diagram；
Fig. 4 is the composition structural representation of FPGA；
Fig. 5 is the module diagram of the image zoom processing method device based on FPGA of an embodiment；
Fig. 6 is the module diagram of the image zoom processing method device based on FPGA of another embodiment.
Specific embodiment
Refer to Fig. 1, there is provided a kind of image zoom processing method based on FPGA of embodiment, comprise the following steps：
S110：Obtain original digital image data, and be put into speed original digital image data is put into FPGA inner buffers with default.
Original image refers to pending image, is that treatment is zoomed in and out to image, that is to say, that original image in the present embodiment
To treat zoomed image, because image is made up of pixel, so that, original digital image data refers to original image pixel point value, is being needed
When zooming in and out treatment to original image, it is necessary first to obtain original digital image data, that is, obtain the pixel point value of original image.In this implementation
In example, realize that image scaling is processed by FPGA, in order to improve FPGA processing speeds, be put into original digital image data in FPGA by FPGA
In portion's caching, stored without using external memory storage, reduced cost, subsequently when being read out, directly from inside FPGA
Read in caching, without being read from external memory storage, improve and read express delivery, so as to improve subsequently be imitated to image scaling treatment
Rate.In addition, collect in cache control logic, in order to realize will not being lost come data cached and data with FPGA inner buffers,
The reading speed of data must be accurately read from FPGA inner buffers, speed can cause very much loss of data slowly, and speed soon can very much
The difficulty that FPGA is realized is increased, causes unnecessary resource to carry out that expense, so as in order to subsequently need with reasonably reading speed
Data are read, speed is put into original digital image data is put into FPGA inner buffers with default.
S120：Original digital image data is read from inner buffer with the default corresponding reading speed of speed that is put into, and according to
Interpolation algorithm and the original digital image data of reading, carry out interpolation calculation, obtain image interpolation data.
Original digital image data is read out with the default corresponding reading speed of speed that is put into, that is to say, that with reasonable ground velocity
Degree is read out to original digital image data, both can ensure that data will not lose and has in turn, ensured that reading speed.Obtaining the artwork of reading
As after data, interpolation calculation being carried out according to interpolation algorithm, image interpolation data are obtained.
S130：According to image interpolation data, the view data after being scaled.
When being zoomed in and out to image, actually to the interpolation processing of image, interpolation algorithm has various, is calculated by interpolation
After method carries out interpolation processing acquisition image interpolation data to original digital image data, after being also achieved with zooming in and out original digital image data
View data.
The above-mentioned image zoom processing method based on FPGA, obtains original digital image data, and be put into speed by artwork with default
As data are put into FPGA inner buffers, original image number is read from inner buffer with the default corresponding reading speed of speed that is put into
According to, and according to interpolation algorithm and the original digital image data of reading, interpolation calculation is carried out, image interpolation data are obtained, according to image
Interpolated data, the view data after being scaled.Cached due to original digital image data is put into FPGA inner buffers, without using
External memory storage is stored, and reduces hardware cost, and can be read from FPGA inner buffers during subsequent read original digital image data
Take, without being read from external memory storage again, accelerate data reading speed, so as to general image scaling efficiency can be improved.In addition,
Original digital image data is read from inner buffer with the default corresponding reading speed of speed that is put into, i.e., with reasonably reading speed pair
Original digital image data is read out, and both can ensure that the speed of reading avoids causing very much loss of data slowly due to reading speed, improves contracting
Treatment effeciency is put, can avoid realizing that difficulty causes the problem of the wasting of resources because reading speed is increased very much soon again.
Fig. 2 is referred to, wherein in one embodiment, FPGA inner buffers include that the first inner buffer, the second inside are slow
Deposit and the 3rd inner buffer, and the first inner buffer, the second inner buffer and the 3rd inner buffer a difference storage cell
Row view data.
In the present embodiment, original digital image data is obtained, and is included the step of original digital image data is put into FPGA inner buffers：
S211：Obtain original digital image data.With unit behavior step-length and default row order direction, by the list of original digital image data
Position row view data is put into the caching of free time in the first inner buffer, the second inner buffer and the 3rd inner buffer.
Wherein, row order direction is preset including the row order direction from minimum row to maximum row or from maximum row to minimum row
Row order direction.Specifically, in the present embodiment, using the order direction of minimum row to maximum row.Due to the size of image
Together decided on by row and example size, the corresponding row of origin of the minimum behavior view data of image, maximum behavior view data
The corresponding row of maximum coordinates point.Such as, original digital image data size is M*N, and the image of M row N row sizes, minimum row is original image
The first row, maximum row is the M rows of original image.Original digital image data includes multi-line images data, for example, the original of M*N sizes
View data, it includes M row view data, with unit behavior step-length and default row order direction, by the list of original digital image data
Position row view data is put into the caching of free time in the first inner buffer, the second inner buffer and the 3rd inner buffer, that is,
According to unit row step-length be put into FPGA inner buffers unit row view data to original digital image data by realization.
In the present embodiment, original image number is read from inner buffer with the default corresponding reading speed of speed that is put into
According to, and interpolation calculation is carried out to the original digital image data for reading according to interpolation algorithm, wrap the step of obtain view data interpolated data
Include：
S221：When the unit row image that the first inner buffer, the second inner buffer and the 3rd inner buffer are stored with
During data, storage time the first two unit row view data more long is read from FPGA inner buffers with reading speed, and will
Storage time unit row view data most long is deleted from FPGA inner buffers.
S222：Storage time according to interpolation algorithm and reading the first two unit row view data more long, is inserted
Value is calculated, and obtains initial pictures interpolated data.
S223：Judge whether original digital image data is put into finish.
Delay if it is not, returning and original digital image data being put into the first inside with unit behavior step-length and default row order direction
Deposit, idle in the second inner buffer and the 3rd inner buffer caching the step of.
If so, then performing following steps：
S224：Remaining two units row view data in FPGA inner buffers is read, according to interpolation algorithm and reading
FPGA inner buffers in remaining two units row view data, carry out interpolation calculation, obtain residual image data interpolating number
According to view data interpolated data is residual image data interpolating data and each initial pictures interpolated data.
Specifically, unit behavior single file, the matrix of pixel point value is represented by due to image, such that it is able to ranks size table
The size of diagram picture, row data represent the row pixel point value in image array.Original digital image data includes multi-line images data, line number
Determine for example, the size of original digital image data is M*N, that is, there is the view data and N row images of M rows by the size of original digital image data
Data.When interpolation calculation is carried out to original digital image data, in order to improve processing speed, by original digital image data with unit behavior step-length
It is stored in FPGA inner buffers, FPGA inner buffers include that the first inner buffer, the second inner buffer and the 3rd inside are slow
Deposit, per unit row view data is put into corresponding single inner buffer.
For example, when initial, the first inner buffer, the second inner buffer and the 3rd inner buffer are the free time, the free time is
Refer to no any data of storage in caching, be deposited into first when the view data of the first row of original image is started into input
Portion caches, and the view data of the second row starts to be stored in the second inner buffer when input, the view data input of the third line
When be deposited into the 3rd inner buffer, because the first inner buffer, the second inner buffer and the 3rd inner buffer are only deposited respectively
Single unit row view data is stored up, now, FPGA no longer receives view data storage, is read from inner buffer with reading speed
Storage time the first two unit row view data (i.e. the view data of the view data of the first row and the second row) more long, and will
Storage time unit row view data most long (i.e. the view data of the first row) is deleted from FPGA inner buffers, and according to
The view data of interpolation algorithm, the view data of the first row and the second row, carries out interpolation calculation, obtains the view data of the first row
Initial pictures interpolated data corresponding with the view data of the second row, now, because the view data of the first row is from inside FPGA
Deleted in caching, i.e., the first inner buffer is idled, if original digital image data is not put into also finishing, return and walked with unit behavior
It is long the step of view data to be put into idle caching in the first inner buffer, the second inner buffer and the 3rd inner buffer after
Renew and put original digital image data, will the view data of fourth line put into the first inner buffer, now, above-mentioned FPGA inside is slow
The time data memory deposited in the second inner buffer and the 3rd inner buffer is more long, will the second row view data and the 3rd
Capable view data is read, and the view data of the second row is deleted from FPGA inner buffers, and according to interpolation algorithm and
The view data and the view data of the third line of the second row for reading, carry out interpolation calculation, obtain the second row view data and
The corresponding initial pictures interpolated data of view data of the third line.Now, because the view data of the second row has been deleted, in second
Portion's caching is idle, the first inner buffer stores the view data of fourth line, the 3rd buffer memory image of the third line
Data, if original digital image data is not put into also finishing, return with unit behavior step-length by view data be put into the first inner buffer,
Continue to deposit original digital image data the step of idle caching in second inner buffer and the 3rd inner buffer, will fifth line
View data is put into the second inner buffer, repeating query, is finished until original digital image data is put into, now, in FPGA inner buffers
The view data of also two later rows of storage time is not deleted, and is not read yet, i.e. two not read in reading FPGA
Unit row view data, according to the two unit row view data not read in interpolation algorithm and the FPGA of reading, is inserted
Value calculate, obtain residual image data interpolating data, view data interpolated data be residual image data interpolating data and it is each just
Beginning image interpolation data.
In order to avoid FPGA reads original digital image data from external memory storage, reading efficiency is improved, original digital image data is deposited
In FPGA inner buffers, so as to follow-up quick reading, because the memory space of FPGA inner buffers is little, each is internal slow for storage
Deposit only can storage cell row view data (in the present embodiment be single file), in order to avoid the influence that insufficient space brings, by upper
The mode for stating wheel circulation carries out interpolation calculation, realizes that image scaling is processed, i.e., the image of single file is stored in each inner buffer
Data, a line storage time view data most long is deleted after often calculating an interpolation calculation, to provide the spatial cache of free time,
So that the view data of next line is deposited, so without entering row interpolation meter again after all original digital image datas are all deposited and finished
Calculate, interpolation calculation efficiency is improved, so as to improve image scaling efficiency.
It is above-mentioned to be read from inner buffer with the default corresponding reading speed of speed that is put into wherein in one embodiment
Before original digital image data, also including step：
The goal-selling size after initial size and the original digital image data scaling of original digital image data is obtained, and according to default
Speed, the initial size of original digital image data and goal-selling size are put into, acquisition reads original image from FPGA inner buffers
The reading speed of data.
In cache control logic, will not be lost to realize that FPGA inner buffers carry out data cached and data, it is necessary to
The reading speed that data are read from FPGA inner buffers is accurately calculated, speed can cause very much the loss of data slowly, and speed is too
The difficulty of FPGA realizations can be increased soon, cause the unnecessary wasting of resources.With 640x1136 resolution ratio (original digital image data it is initial
Size) original image zoom into the image of 720x1280 resolution ratio (goal-selling size) as a example by, it is assumed that original digital image data is put into
For S1, then the formula for obtaining reading speed S2 is the default speed that is put into of FPGA inner buffers：
S2=(720/640) * (1280/1136) * S1.
Wherein in one embodiment, interpolation algorithm includes bilinear interpolation algorithm, and FPGA inner buffers are inside FPGA
SRAM, the first inner buffer is that the first internal SRAM, the second inner buffer are that the second internal SRAM and the 3rd inner buffer are
3rd internal SRAM.
In view of difficulty and zooming effect that interpolation algorithm is realized, image is contracted using bilinear interpolation algorithm
Put treatment.In the algorithm of bilinearity difference, the element of newly-generated picture be by original image position four around new element
Individual adjacent point passes through weighted average calculation out.The correlation of newly-generated element and surrounding element can thus be retained,
So that image has preferable zooming effect at edge.As shown in figure 3, pixel A, B, C, D are original image element (original image pixel
Point), E is new images element (the image slices vegetarian refreshments after scaling), and element value is all 8 data of bit wide.Then new images element E
The computational methods of pixel point value E (x+dx, y+dy) are：
E (x+dx, y+dy)=(1-dx) (1-dy) A (x, y)+dx (1-dy) B (x, y)+(1-dx) dyC (x, y)+dxdyA
(x,y)。
From the equations above as can be seen that new images element is calculated with FPGA needs 8 multipliers, two subtracters, 3
Individual adder.Wherein, A (x, y) is the coordinate of A, and B (x, y) is the coordinate of B, and C (x, y) is the coordinate of C, and D (x, y) is the seat of D
Mark, dx is the abscissa distance of new images element E and pixel A, and dy is the ordinate distance of new images element E and pixel B.
FPGA inner buffers are FPGA internal SRAMs, and SRAM is SRAM, it is not necessary to which refresh circuit can be protected
The data of its storage inside are deposited, overall operating efficiency can be improved.First inner buffer is the first internal SRAM (SRAM1), the
Two inner buffers are the second internal SRAM (SRAM2) and the 3rd inner buffer is the 3rd internal SRAM (SRAM3).Calculate every time
One pixel value of interpolation point, it is necessary to use four pixel values of point around, FPGA inner buffers must can cache three rows
View data, it is necessary to realized using 3 dual-port SRAM that FPGA is carried in itself caching.
FPGA composition structure charts in one embodiment are as shown in figure 4, the FPGA includes fpga logic control module, divides
The FPGA inside not being connected with fpga logic control module is delayed and interpolation calculation module, and SRAM1, SRAM2 and SRAM3 divide equally
It is not connected with fpga logic control module.Include the image scaling processing unit based on FPGA in fpga logic control module,
The image scaling processing unit for being based on FPGA is applied to the image zoom processing method based on FPGA, the i.e. image based on FPGA
Scaling method is performed by fpga logic control module.
Control the data of FPGA inner buffers to deposit and read data by fpga logic control module and send into interpolation meter
Calculating module carries out interpolation calculation.Because every kind of caching can only deposit three row data in FPGA inner buffers, it is therefore desirable in circulation
Storage is processed, and SRAM1 is stored in when the first row view data starts input, when the second row view data starts input
SRAM2 is stored in, the third line view data starts to be stored in SRAM3 when input, to the first row view data and the second row image
Data are read out carries out interpolation calculation, and after deleting the first row view data, SRAM1 is idle, and fourth line view data starts defeated
SRAM1, repeating query are stored in when entering.
Meanwhile, when the third line view data starts to be stored in SRAM3, taking-up view data is carried out from SRAM1 and SRAM2
The new interpolated data of interpolation calculation.When fourth line view data is stored in SRAM1, picture number is taken out from SRAM2 and SRAM3
According to the new interpolated data of calculating.When fifth line view data is stored in SRAM2, view data is taken out from SRAM3 and SRAM1
Calculate new interpolated data.When the 6th row view data starts to be stored in SRAM3, data calculating is taken out from SRAM1 and SRAM2
New interpolated data, repeating query is finished until view data reads.By above-mentioned repeating query process, it is possible to realize with 3 dual-ports
SRAM to cache three row view data, reach realize bilinear interpolation calculate purpose.
It is above-mentioned according to interpolation algorithm and the original digital image data of reading wherein in one embodiment, interpolation calculation is carried out,
Before obtaining image interpolation data, also including step：
The bit wide of each original digital image data for reading is adjusted to default bit wide, the original digital image data for reading is updated.
Wherein, default bit wide is 8.By above-mentioned formula when interpolation arithmetic is carried out, it can be seen that bilinear interpolation
, it is necessary to use multiplier in algorithm, the bit wide of multiplier will be largely fixed the amplification effect for changing algorithm.But multiplication
The bit wide of device can be subject to the arithmetic speed of FPGA and restricting for resource, because having to select a position for suitable multiplier
Width, it is reached amplification effect can meet the speed of service of FPGA again.
Because the distance between pixel is 1, dx, dy, (1-dx) are can be seen that with reference to bilinear interpolation algorithm schematic diagram
And (1-dy) is all the decimal between 0 to 1.Because FPGA does not support fractional arithmetic, must convert it to whole
Number computing.Primitive element value A (x, y), B (x, y), C (x, y), D (x, y) are to be fixed as 8 data of bit wide, so decimal
Being converted into the bit wide of integer will determine the bit wide of multiplier, can also determine the amplification effect of algorithm.In history experiment, test
Decimal is converted into 4,6,8,10 amplification effects of the multiplier of bit wide, practice have shown that the bit wide of multiplier is got over
Greatly, the effect of amplification is better, but amplification effect and the relation that bit wide width is not linear increment, when the width of bit wide is 10
More than position (including 10), amplification effect has not improved significantly, and 10 multipliers of bit wide can cause FPGA integrally to transport
The reduction of efficiency is calculated, therefore, after comprehensive FPGA resource, amplification effect and the big factor of FPGA arithmetic speeds three, using 8 positions
Multiplier amplification effect wide can reach requirement, so that, according to interpolation algorithm and the original digital image data of reading, enter row interpolation
Calculate, before obtaining image interpolation data, the bit wide of each original digital image data for reading is adjusted to 8, update the original for reading
View data.
Refer to Fig. 5, a kind of image scaling processing unit based on FPGA, it is characterised in that including：
Storage module 510, for obtaining original digital image data, and is put into speed original digital image data is put into FPGA with default
Portion caches.
Image interpolation data acquisition module 520, for being put into the corresponding reading speed of speed from inner buffer with default
Middle reading original digital image data, and according to interpolation algorithm and the original digital image data of reading, interpolation calculation is carried out, obtain image interpolation
Data.
Image data acquisition module 530 after scaling, for according to image interpolation data, the picture number after being scaled
According to.
Fig. 6 is referred to, wherein in one embodiment, FPGA inner buffers include that the first inner buffer, the second inside are slow
Deposit and the 3rd inner buffer, and the first inner buffer, the second inner buffer and the 3rd inner buffer a difference storage cell
Row view data.
Storage module includes：
Acquisition module 611, for obtaining original digital image data.
Memory module 612, for unit behavior step-length and default row order direction, by the unit row of original digital image data
View data is put into the caching of free time in the first inner buffer, the second inner buffer and the 3rd inner buffer.
Wherein, row order direction is preset including the row order direction from minimum row to maximum row or from maximum row to minimum row
Row order direction.Specifically, in the present embodiment, using the order direction of minimum row to maximum row.
Image interpolation data acquisition module includes：
Read module 621, for being stored with list when the first inner buffer, the second inner buffer and the 3rd inner buffer
During the row view data of position, storage time the first two unit row picture number more long is read from FPGA inner buffers with reading speed
According to, and storage time unit row view data most long is deleted from FPGA inner buffers.
Initial pictures interpolated data acquisition module 622, for more long according to interpolation algorithm and the storage time of reading
The first two unit row view data, carries out interpolation calculation, obtains initial pictures interpolated data.
Judge module 623, finishes for judging whether original digital image data is put into.
Return module 624, for judge module judged result for it is no when, return memory module with unit behavior step-length with
And default row order direction, by the unit row view data of original digital image data be put into the first inner buffer, the second inner buffer with
And the 3rd idle caching in inner buffer.
Residual image data interpolating acquisition module 625, the judged result for judge module is when being, to be remained in reading FPGA
Two remaining unit row view data, according to remaining two units row view data in interpolation algorithm and the FPGA of reading,
Interpolation calculation is carried out, residual image data interpolating data are obtained, view data interpolated data is residual image data interpolating data
With each initial pictures interpolated data.
Wherein in one embodiment, the above-mentioned image scaling processing unit based on FPGA, also including speed acquiring module.
Speed acquiring module, for image interpolation data acquisition module with it is default be put into the corresponding reading speed of speed from
Obtain pre- after initial size and the original digital image data scaling of original digital image data before reading original digital image data in inner buffer
If target sizes, and speed, the initial size of original digital image data and goal-selling size are put into according to default, obtain from FPGA
The reading speed of original digital image data is read in inner buffer.
Wherein in one embodiment, interpolation algorithm includes bilinear interpolation algorithm, and FPGA inner buffers are inside FPGA
SRAM, the first inner buffer is that the first internal SRAM, the second inner buffer are that the second internal SRAM and the 3rd inner buffer are
3rd internal SRAM.
Wherein in one embodiment, the above-mentioned image scaling processing unit based on FPGA also includes update module.
Update module, for image interpolation data acquisition module according to interpolation algorithm and the original digital image data of reading, enters
Row interpolation is calculated, and the bit wide of each original digital image data for reading is adjusted into default bit wide before obtaining image interpolation data,
Update the original digital image data for reading.
The above-mentioned image zoom processing method device based on FPGA is to realize the above-mentioned image scaling treatment side based on FPGA
The device of method, technical characteristic is corresponded, and be will not be repeated here.
Each technical characteristic of above example can be combined arbitrarily, to make description succinct, not to above-described embodiment
In each technical characteristic it is all possible combination be all described, as long as however, the combination of these technical characteristics do not exist lance
Shield, is all considered to be the scope of this specification record.
Above example only expresses several embodiments of the invention, and its description is more specific and detailed, but can not
Therefore it is interpreted as the limitation to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art,
Without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection model of the invention
Enclose.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
1. a kind of image zoom processing method based on FPGA, it is characterised in that comprise the following steps：
Obtain original digital image data, and be put into speed the original digital image data is put into FPGA inner buffers with default；
Original digital image data is read from the inner buffer with the default corresponding reading speed of speed that is put into, and according to inserting
Value-based algorithm and the original digital image data of reading, carry out interpolation calculation, obtain image interpolation data；
According to described image interpolated data, the view data after being scaled.
2. the image zoom processing method based on FPGA according to claim 1, it is characterised in that the FPGA inside is slow
Bag deposit includes the first inner buffer, the second inner buffer and the 3rd inner buffer, and first inner buffer, in described second
Portion caches and the 3rd inner buffer difference storage cell row view data；
The acquisition original digital image data, and include the step of the original digital image data is put into FPGA inner buffers：Obtain artwork
As data；With unit behavior step-length and default row order direction, the unit row view data of the original digital image data is put into
Idle caching in first inner buffer, second inner buffer and the 3rd inner buffer；
It is described that original digital image data, and root are read from the inner buffer with the default corresponding reading speed of speed that is put into
The step of interpolation calculation, acquisition view data interpolated data are carried out to the original digital image data for reading according to interpolation algorithm includes：
When first inner buffer, second inner buffer and the 3rd inner buffer are stored with unit row image
During data, storage time the first two unit row picture number more long is read from the FPGA inner buffers with the reading speed
According to, and storage time unit row view data most long is deleted from the FPGA inner buffers；
Storage time according to the interpolation algorithm and reading the first two unit row view data more long, enters row interpolation meter
Calculate, obtain initial pictures interpolated data；
Judge whether the original digital image data is put into finish；
If it is not, with unit behavior step-length and default row order direction described in returning, by the unit row figure of the original digital image data
As data are put into the caching of free time in first inner buffer, second inner buffer and the 3rd inner buffer
Step；
If so, remaining two units row view data in reading the FPGA inner buffers, according to the interpolation algorithm and
Remaining two units row view data in the FPGA inner buffers for reading, carries out interpolation calculation, obtains residual image number
According to interpolated data, described image data interpolating data are the residual image data interpolating data and each initial pictures interpolation
Data.
3. the image zoom processing method based on FPGA according to claim 1, it is characterised in that described with pre- with described
If being put into before the corresponding reading speed of speed reads original digital image data from the inner buffer, also including step：
Obtain the original digital image data initial size and the original digital image data scaling after goal-selling size, and according to
Described presetting is put into speed, the initial size of the original digital image data and the goal-selling size, obtains from the FPGA
The reading speed of the original digital image data is read in inner buffer.
4. the image zoom processing method based on FPGA according to claim 1, it is characterised in that the interpolation algorithm bag
Bilinear interpolation algorithm is included, the FPGA inner buffers are FPGA internal SRAMs, and first inner buffer is inside first
SRAM, second inner buffer are the second internal SRAM and the 3rd inner buffer is the 3rd internal SRAM.
5. the image zoom processing method based on FPGA according to claim 1, it is characterised in that described to be calculated according to interpolation
Method and the original digital image data of reading, carry out interpolation calculation, before obtaining image interpolation data, also including step：
The bit wide of the original digital image data of each reading is adjusted to default bit wide, the original image number of the reading is updated
According to.
6. a kind of image scaling processing unit based on FPGA, it is characterised in that including：
Storage module, for obtaining original digital image data, and is put into speed the original digital image data is put into inside FPGA with default
Caching；
Image interpolation data acquisition module, for default being put into the corresponding reading speed of speed from the inner buffer with described
Middle reading original digital image data, and according to interpolation algorithm and the original digital image data of reading, interpolation calculation is carried out, obtain image interpolation
Data；
Image data acquisition module after scaling, for according to described image interpolated data, the view data after being scaled.
7. the image scaling processing unit based on FPGA according to claim 6, it is characterised in that the FPGA inside is slow
Bag deposit includes the first inner buffer, the second inner buffer and the 3rd inner buffer, and first inner buffer, in described second
Portion caches and the 3rd inner buffer difference storage cell row view data；
The storage module includes：
Acquisition module, for obtaining original digital image data；
Memory module, for unit behavior step-length and default row order direction, by the unit row figure of the original digital image data
The caching of free time in first inner buffer, second inner buffer and the 3rd inner buffer is put into as data；
Described image interpolated data acquisition module includes：
Read module, for being deposited when first inner buffer, second inner buffer and the 3rd inner buffer
When containing unit row view data, read from the FPGA inner buffers with the reading speed storage time it is more long before two
Individual unit row view data, and storage time unit row view data most long is deleted from the FPGA inner buffers；
Initial pictures interpolated data acquisition module, for the storage time according to the interpolation algorithm and reading it is more long before two
Individual unit row view data, carries out interpolation calculation, obtains initial pictures interpolated data；
Judge module, finishes for judging whether the original digital image data is put into；
Module is returned, when the judged result for the judge module is no, the memory module is returned to unit behavior step-length
And default row order direction, the unit row view data of the original digital image data is put into first inner buffer, described
Idle caching in second inner buffer and the 3rd inner buffer；
Residual image data interpolating acquisition module, the judged result for the judge module is when being, in the reading FPGA
Remaining two units row view data, according to remaining two unit rows in the interpolation algorithm and the FPGA of reading
View data, carries out interpolation calculation, obtains residual image data interpolating data, and described image data interpolating data are the residue
View data interpolated data and each initial pictures interpolated data.
8. the image scaling processing unit based on FPGA according to claim 6, it is characterised in that also include：
Speed acquiring module, default is put into that speed is corresponding to read speed for described image interpolated data acquisition module with described
Spend before reading original digital image data from the inner buffer and obtain the initial size and the artwork of the original digital image data
As the goal-selling size after data zooming, and according to it is described it is default be put into speed, the initial size of the original digital image data with
And the goal-selling size, obtain the reading speed that the original digital image data is read from the FPGA inner buffers.
9. the image scaling processing unit based on FPGA according to claim 6, it is characterised in that the interpolation algorithm bag
Bilinear interpolation algorithm is included, the FPGA inner buffers are FPGA internal SRAMs, and first inner buffer is inside first
SRAM, second inner buffer are the second internal SRAM and the 3rd inner buffer is the 3rd internal SRAM.
10. the image scaling processing unit based on FPGA according to claim 6, it is characterised in that also include：
Update module, for described image interpolated data acquisition module according to interpolation algorithm and the original digital image data of reading, enters
Row interpolation is calculated, and the bit wide of the original digital image data of each reading is adjusted into default position before obtaining image interpolation data
Width, updates the original digital image data of the reading.
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