CN110138341A - A kind of signal demodulating circuit - Google Patents
A kind of signal demodulating circuit Download PDFInfo
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- CN110138341A CN110138341A CN201810104569.0A CN201810104569A CN110138341A CN 110138341 A CN110138341 A CN 110138341A CN 201810104569 A CN201810104569 A CN 201810104569A CN 110138341 A CN110138341 A CN 110138341A
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- 230000010354 integration Effects 0.000 claims abstract description 30
- 238000006243 chemical reaction Methods 0.000 claims abstract description 8
- 239000003990 capacitor Substances 0.000 claims description 31
- 238000005070 sampling Methods 0.000 claims description 11
- 230000005611 electricity Effects 0.000 claims description 3
- 238000004088 simulation Methods 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 2
- 238000012545 processing Methods 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000010183 spectrum analysis Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 230000000717 retained effect Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/006—Demodulation of angle-, frequency- or phase- modulated oscillations by sampling the oscillations and further processing the samples, e.g. by computing techniques
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Abstract
A kind of signal demodulating circuit includes: integrator module, input terminal input modulating signal, for integrating to input signal；Data acquisition module, input terminal connect the output end of integrator module, carry out data acquisition for the output to integrator module and export useful signal；The integrator module has reset signal, and when integration period starts, reset signal resets integrator module, and at the end of integration period, data acquisition module carries out data acquisition to the output of integrator module.The present invention can pass through simple circuit structure, utilize few hardware resource, effectively useful signal is extracted from the modulated signal containing carrier signal, when need to be converted to digital signal carry out processing analysis when, the requirement to the conversion speed and precision of required digital analog converter is lower.
Description
Technical field
The present invention relates to a kind of signal demodulating circuits, and in particular to one kind for by useful signal from being superimposed with carrier signal
Modulation wave signal in the signal demodulating circuit separated.
Background technique
In the signal processing, filter circuit is generallyd use by the useful signal with certain frequency from containing carrier signal
Or separated in the modulation wave signal of interference signal, the characteristic of filter makes the signal in its passband be retained or amplify,
And the signal outside passband is suppressed.When the distance on frequency domain is closer with the frequency of carrier signal or interference signal for useful signal,
So that the intermediate zone between the passband and stopband of filter is very narrow or the Amplitude Ratio useful signal of carrier signal or interference signal is big
When very much, the design of filter can become extremely complex.Such as DC current and residual current are being carried out using magnetic modulation technique
In the application of detection, carrier signal is usually in 2KHz ~ 10KHz, and the frequency of measured signal reaches as high as 1KHz, and carrier signal
Amplitude be usually 10 times of useful signal amplitude or more, the design of filter becomes complicated in this application environment, required
Hardware resource is more.Well known technology mostly uses greatly analog circuit or digital circuit multi-stage filter, and multi-stage filter is logical
It is often 5 ranks ~ 8 rank Butterworth filters or Chebyshev filter.Technology well known to another kind is the method using spectrum analysis,
The signal that the time-domain signal of sampling is first switched to frequency domain by Fourier transformation, is then filtered and divides in frequency domain
Analysis.These technologies require complicated circuit structure and hardware resource, and such as 5 ranks ~ 8 rank analog filters need at least 3 grades to 4 grades
Operational amplifier, and digital filter or the technology of spectrum analysis will first contain firstly the need of before carrying out Digital Signal Processing
The modulated-analog signal of carrier signal is converted to digital signal by analog-digital converter (ADC), due to the Amplitude Ratio of carrier signal
The big more and carrier signal of the amplitude of useful signal usually contains the signal of radio-frequency component, so that for analog-digital converter
Conversion rate and precision have higher requirement.In addition, the conversion of time-frequency domain needed for spectrum analysis and frequency filtering require
More complex software or hardware resource, so that total solution becomes complicated, cost of implementation is higher.
Summary of the invention
The present invention provides a kind of signal demodulating circuit, and structure is simple, design is convenient, required hardware resource is few.
In order to achieve the above object, the present invention provides a kind of signal demodulating circuit, includes:
Integrator module, input terminal input modulating signal, for being integrated to input signal；
Data acquisition module, input terminal connect the output end of integrator module, count for the output to integrator module
According to acquiring and export useful signal；
The integrator module has reset signal, and when an integration period starts, reset signal is clear by integrator module
Zero, at the end of an integration period, data acquisition module carries out data acquisition to the output of integrator module.
The pulse width of the reset signal is less than integration period.
In one embodiment, the integrator module is analogue integrator, which includes: operation amplifier
Device, resistance, capacitor and switch, the electrode input end ground connection of operational amplifier, negative input connect resistance, the connection of capacitor one end
The output end of operational amplifier, the other end connect the negative input of operational amplifier, switch, one end of switch in parallel with capacitor
The output end of operational amplifier is connected, the other end connects the negative input of operational amplifier, and reset signal control switch is led
Through and off are opened, and when reset signal is low level, switch is in an off state, and is made of operational amplifier, resistance and capacitor
Integrator carries out integration operation to input signal, and when reset signal is high level, switch conduction discharges to capacitor, by operation
The output end of the integrator of amplifier, resistance and capacitor composition is cleared.
The data acquisition module is sampling hold circuit, which includes: switch and capacitor, switch
One end connects the output end of operational amplifier, and the other end connects the output end of data acquisition module, and one end of capacitor connects data
The output end of acquisition module, other end ground connection, the conducting and disconnection of sampled clock signal control switch, when sampled clock signal is
When high level, the signal of switch conduction, operational amplifier output terminal is sampled on capacitor, when sampled clock signal is low level
When, switch disconnects, and signal remains unchanged on capacitor, is updated when sample next time.
The frequency of the sampled clock signal and the frequency of reset signal are identical, and the pulse width of sampled clock signal is small
In integration period.
In another embodiment, the data acquisition module is analog-digital converter.
In another embodiment, the signal demodulating circuit also includes analog-digital converter, and modulated signal connects first
To the input terminal of analog-digital converter, the modulated signal of simulation is converted to the signal of numeric field, analog-digital converter by analog-digital converter
Output end connection integrator module input terminal.
The integrator module is accumulator.
The data acquisition module is register circuit.
In another embodiment, the signal demodulating circuit also includes digital signal processor, at the digital signal
Manage the output end of the input terminal connection data acquisition module of device.
The present invention can be by simple circuit structure, using few hardware resource, effectively by useful signal from containing
Have in the modulated signal of carrier signal and extract, when need to be converted to digital signal carry out processing analysis when, to required digital-to-analogue
The requirement of the conversion speed and precision of converter is lower.
Detailed description of the invention
Fig. 1 is a kind of electrical block diagram of signal demodulating circuit provided by the invention.
Fig. 2 is common carrier signal waveform.
Fig. 3 is that useful signal with carrier signal and the two is superimposed the modulation wave signal to be formed.
Fig. 4 is the electrical block diagram of the first embodiment of the present invention.
Fig. 5 is the waveform of each node in the first embodiment of the present invention.
Fig. 6 is the electrical block diagram of the second embodiment of the present invention.
Fig. 7 is the electrical block diagram of the third embodiment of the present invention.
Specific embodiment
Below according to FIG. 1 to FIG. 7, presently preferred embodiments of the present invention is illustrated.
As shown in Figure 1, the present invention provides a kind of signal demodulating circuit, for by useful signal from being superimposed with carrier signal
It is separated in modulation wave signal, it includes:
Integrator module 1, input terminal input modulating signal, for integrating to input signal, which has
Reset signal, the reset signal are zeroed out operation to the output end of integrator module 1 in each integration period；
Data acquisition module 2, input terminal connect the output end of integrator module 1, and output end exports useful signal, for product
The output of device module 1 is divided to carry out data acquisition.
Modulated signal containing useful signal and carrier signal is inputted by the input terminal of integrator module 1, integrator module 1
Integration operation is carried out to the signal of input, external circuit provides reset signal to integrator module 1, and reset signal is in each integral
Operation is zeroed out to the output end of integrator module 1 in period, the pulse width of reset signal is far smaller than integration period, i.e.,
Integrator module 1 only integrates the modulated signal in an integration period, and the output end of integrator module 1 is connected to data
The input terminal of acquisition module 2, data acquisition module 2 at the end of each integration period to the output result of integrator module 1 into
Row acquisition, signal collected is the form of expression of the useful signal in discrete time-domain.
It, can also be with as shown in Fig. 2, carrier signal waveform can be sinusoidal waveform, triangular waveform or the square wave of waveform rule
It is the irregular waveform of waveform, the carrier waveform such as generated using magnetic modulation technique.Carrier signal has in specific integration period
The characteristics of interior integral is zero.Modulated signal is made of carrier signal superposition useful signal, and Fig. 3 show useful signal, using magnetic
Complicated carrier signal and the two that modulation technique generates are superimposed the waveform for the modulation wave signal to be formed.In the present embodiment, by
It is zero in integral of the carrier signal within the single carrier wave period, therefore, integration period can be equal to carrier cycle, and modulated signal exists
The result for carrying out exporting after the integral of an integration period in integrator module is product of the useful signal in the integration period
Point.Useful signal can be extracted by carrying out integration operation to the modulation wave signal in each integration period.
As shown in figure 4, in the first embodiment of the present invention, integrator module uses well known analogue integrator, the mould
Quasi- integrator includes operational amplifier U, resistance R0, capacitor C0 and switch S0, and the electrode input end of operational amplifier U is grounded, bears
Pole input terminal connects resistance R0, and the one end capacitor C0 connects the output end of operational amplifier, and the other end connects the negative of operational amplifier
Pole input terminal, switch S0 is in parallel with capacitor C0, and one end connects the output end of operational amplifier, and the other end connects operational amplifier
Negative input, the conducting and disconnection of reset signal control switch S0, when reset signal is low level, switch S0, which is in, to be disconnected
State, the integrator being made of operational amplifier U, resistance R0 and capacitor C0 can carry out integration operation to input signal, when clear
When zero-signal is high level, switch S0 conducting discharges to capacitor, the integral being made of operational amplifier U, resistance R0 and capacitor C0
The output end of device is cleared.When each integration period starts, reset signal resets analogue integrator output end signal.Data
Acquisition module uses the sampling hold circuit being made of switched-capacitor circuit to realize, which includes switch S1 and electricity
Hold C1, the output end of one end connection operational amplifier U of switch S1, the other end connects the output end of data acquisition module, capacitor
The output end of one end connection data acquisition module of C1, the conducting of other end ground connection, switch S1 are provided with disconnection by external circuit
Sampling clock control, in the present embodiment, the frequency of sampling clock and the frequency of reset signal are identical, the pulse of sampling clock
Width is far smaller than integration period.When sampled clock signal is high level, switch S1 conducting, operational amplifier U is exported at this time
The signal at end is sampled on capacitor C1, and when sampled clock signal is low level, switch S1 is disconnected, at this time signal on capacitor C1
It remains unchanged.At the end of integration period, the high level pulse signal of sampling clock passes through sampling hold circuit for integrator
Output signal samples on capacitor C1, and is updated at the end of remaining to next integration period.Fig. 5 is in first embodiment
The waveform diagram of each node signal.It should be pointed out that at the end of an integration period, the advanced line number of data acquisition module
According to acquisition, when back to back next integration period starts, reset signal resets integrator module.
As shown in fig. 6, integrator module still uses well known analogue integrator in the second embodiment of the present invention, and
Data acquisition module realizes that the analog-digital converter can be direct by the output signal of integrator using analog-digital converter (ADC)
The signal of numeric field is converted to be handled in order to which digital signal processor (DSP) is further to the signal after demodulation, such as
Virtual value, the maximum value for seeking signal analyze the frequency spectrum etc. of signal, realize the function of various signal processings.It should be pointed out that through
Integrator and data acquisition module are crossed treated that signal no longer contains carrier signal, so that analog signal is converted into digital letter
Number when required analog-digital converter conversion rate and precision all greatly reduce.
Signal demodulating circuit of the invention can also use digital circuit.As shown in fig. 7, real in third of the invention
It applies in example, modulated signal is firstly connected to the input terminal of analog-digital converter (ADC), and analog-digital converter first believes the modulation of simulation
Number be converted to the signal of numeric field.The output end of analog-digital converter is connected to the digital integrator realized using accumulator, described
Accumulator is cleared when each integration period starts, and the output end of accumulator is connected to data acquisition module, data acquisition
Module is realized using digital sample logic, is the register circuit being made of d type flip flop, in the digital sample logic, number
According to being latched, in order to do further Digital Signal Processing (DSP), the function of various signal processings is realized.In the present embodiment
In the modulating wave containing carrier signal is directly converted due to analog-digital converter, the conversion rate of required analog-digital converter and
Precision is higher, but subsequent accumulator and digital sample logic are all very simple structures, are using few hardware resource
It can be achieved.
The present invention can be by simple circuit structure, using few hardware resource, effectively by useful signal from containing
Have in the modulated signal of carrier signal and extract, when need to be converted to digital signal carry out processing analysis when, to required digital-to-analogue
The requirement of the conversion speed and precision of converter is lower.
It is discussed in detail although the contents of the present invention have passed through above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read above content, for of the invention
A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (10)
1. a kind of signal demodulating circuit, characterized by comprising:
Integrator module, input terminal input modulating signal, for being integrated to input signal；
Data acquisition module, input terminal connect the output end of integrator module, count for the output to integrator module
According to acquiring and export useful signal；
The integrator module has reset signal, and when an integration period starts, reset signal is clear by integrator module
Zero, at the end of an integration period, data acquisition module carries out data acquisition to the output of integrator module.
2. signal demodulating circuit as described in claim 1, which is characterized in that the pulse width of the reset signal is less than product
Divide the period.
3. signal demodulating circuit as described in claim 1, which is characterized in that the integrator module is analogue integrator,
The analogue integrator includes: operational amplifier, resistance, capacitor and switch, the electrode input end ground connection of operational amplifier, and cathode is defeated
Entering end connection resistance, capacitor one end connects the output end of operational amplifier, and the other end connects the negative input of operational amplifier,
, the output end of one end connection operational amplifier of switch in parallel with capacitor is switched, the cathode that the other end connects operational amplifier is defeated
Enter end, the conducting and disconnection of reset signal control switch, when reset signal is low level, switch is in an off state, by transporting
The integrator for calculating amplifier, resistance and capacitor composition carries out integration operation to input signal, when reset signal is high level, opens
Conducting is closed, is discharged capacitor, the output end for the integrator being made of operational amplifier, resistance and capacitor is cleared.
4. signal demodulating circuit as claimed in claim 3, which is characterized in that the data acquisition module is that sampling keeps electricity
Road, which includes: switch and capacitor, the output end of one end connection operational amplifier of switch, other end connection
The output end of data acquisition module, the output end of one end connection data acquisition module of capacitor, other end ground connection, sampling clock letter
The conducting and disconnection of number control switch, when sampled clock signal is high level, switch conduction, the letter of operational amplifier output terminal
It number is sampled on capacitor, when sampled clock signal is low level, switch is disconnected, and signal remains unchanged on capacitor, under
It is updated when primary sampling.
5. signal demodulating circuit as claimed in claim 4, which is characterized in that the frequency and clearing of the sampled clock signal
The frequency of signal is identical, and the pulse width of sampled clock signal is less than integration period.
6. signal demodulating circuit as claimed in claim 3, which is characterized in that the data acquisition module is analog-to-digital conversion
Device.
7. signal demodulating circuit as described in claim 1, which is characterized in that the signal demodulating circuit also turns comprising modulus
Parallel operation, modulated signal are firstly connected to the input terminal of analog-digital converter, and the modulated signal of simulation is converted to number by analog-digital converter
The signal in word domain, the input terminal of the output end connection integrator module of analog-digital converter.
8. signal demodulating circuit as claimed in claim 7, which is characterized in that the integrator module is accumulator.
9. signal demodulating circuit as claimed in claim 8, which is characterized in that the data acquisition module is register electricity
Road.
10. such as claim 6 or signal demodulating circuit as claimed in claim 9, which is characterized in that the signal demodulating circuit
It also include digital signal processor, the output end of the input terminal connection data acquisition module of the digital signal processor.
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| CN201810104569.0A CN110138341B (en) | 2018-02-02 | 2018-02-02 | Signal demodulation circuit |
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| CN201810104569.0A CN110138341B (en) | 2018-02-02 | 2018-02-02 | Signal demodulation circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110865383A (en) * | 2019-11-26 | 2020-03-06 | 宁波飞芯电子科技有限公司 | Signal extraction circuit, signal extraction method, and distance measurement method and device |
| CN113009854A (en) * | 2019-12-19 | 2021-06-22 | 江森自控空调冷冻设备(无锡)有限公司 | Device for obtaining effective value of analog input signal |
| CN115146747A (en) * | 2021-03-30 | 2022-10-04 | 上海复旦微电子集团股份有限公司 | Digital temperature sensor and passive radio frequency tag comprising same |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110865383A (en) * | 2019-11-26 | 2020-03-06 | 宁波飞芯电子科技有限公司 | Signal extraction circuit, signal extraction method, and distance measurement method and device |
| CN113009854A (en) * | 2019-12-19 | 2021-06-22 | 江森自控空调冷冻设备(无锡)有限公司 | Device for obtaining effective value of analog input signal |
| CN115146747A (en) * | 2021-03-30 | 2022-10-04 | 上海复旦微电子集团股份有限公司 | Digital temperature sensor and passive radio frequency tag comprising same |
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| CN110138341B (en) | 2023-11-14 |
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