CN110134176B - LDO circuit and wireless charging system - Google Patents

LDO circuit and wireless charging system Download PDF

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Publication number
CN110134176B
CN110134176B CN201910474349.1A CN201910474349A CN110134176B CN 110134176 B CN110134176 B CN 110134176B CN 201910474349 A CN201910474349 A CN 201910474349A CN 110134176 B CN110134176 B CN 110134176B
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pmos
current
comparator
lim
voltage
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CN110134176A (en
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宋垠锡
廖京
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Jiangxi Celfras Integrated Circuit Co ltd
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Jiangxi Celfras Integrated Circuit Co ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Secondary Cells (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The present disclosure provides an LDO circuit and a wireless charging system, the LDO circuit comprising: LDO module and current detection and current limiting module; the LDO module includes: the inverting input end of the first comparator is used for accessing the band gap reference voltage V BGR; the grid electrode of the first PMOS is connected with the output end of the first comparator; the first end of the resistor R1 is connected with the drain electrode of the first PMOS; a varistor R2, the first end of which is connected to the second end of the resistor R1; the first input end of the second input multiplexer is connected with the second end of the resistor R1, and the output end of the second input multiplexer is connected with the non-inverting input end of the first comparator; the current detection and limiting module includes: the first end of the current sensor is connected with the grid electrode of the first PMOS, and the second end of the current sensor is connected with the second input end of the selector; and the non-inverting input end of the second comparator is connected with the second input end of the two-input multiplexer, the inverting input end of the second comparator is used for being connected with the reference voltage V BGR, and the output end of the second comparator is connected with the control end of the two-input multiplexer. The LDO circuit and the wireless charging system reduce the cost and complexity of the circuit.

Description

LDO circuit and wireless charging system
Technical Field
The present disclosure relates to an LDO circuit with current detection and current limiting protection and a wireless charging system.
Background
In modern society, there are more and more places where various electronic devices are used, and the range and the number thereof are also increasing. Basically, these electronic devices all require charging. Most of the current power supplies supply power to the subsequent core circuits after passing through the LDO. Therefore, the stability of the power supply can be ensured, and the normal operation of the circuit can be ensured.
As shown in fig. 1, in the wireless charging system, the receiver converts an ac power source into a dc power source, but the load circuit is generally powered through the LDO because of the influence of ripple in the dc power source, which affects the normal operation of the load. How to detect the output current of the LDO and how to protect the safety of the load circuit by the current limiting protection circuit are very important, especially for the wireless charging system, the control of the output current and the protection of the load are key to realize a stable and high-efficiency wireless charging system.
FIG. 2 is a schematic diagram of a conventional LDO circuit. When VOUT is higher than the design value, VFB is higher than VBGR, resulting in an amplifier output higher than the design value, thereby reducing the voltage VGS between the gate and source of the power transistor PMOS, resulting in a reduction of the main current path current, and thus a reduction of VOUT. Similarly, when VOUT is below the design value, the loop causes VOUT to increase. Thereby stabilizing VOUT at the design voltage. One significant drawback of the LDO circuit shown in fig. 2 is that the magnitude of the output current cannot be controlled. Under the condition that the driving capability of the power tube is enough, the lower the load resistance, the larger the current flowing through the load, and the current limiting protection cannot be provided for the load in time. In practical applications, irreversible damage to the load is possible.
FIG. 3 is a schematic diagram of a conventional LDO detection and current limiting circuit, wherein the LDO comprises a current module loop and a voltage module loop, which are closed by two comparators, and the two loops work independently and act together at the G point to control the output current and voltage. The disadvantage of this circuit is that two high performance comparators are required, which in wireless charging systems operate at high voltage and therefore high voltage devices must be used, thus greatly increasing the circuit area cost. Meanwhile, the circuit adopts the charge pump module, so that the G point is in a high-voltage working state of about V RECT+VTH, the chip area is increased, and the system stability and the power transmission efficiency are influenced.
Disclosure of Invention
First, the technical problem to be solved
In view of the foregoing, a primary object of the present disclosure is to provide an LDO circuit and a wireless charging system, so as to solve at least one of the foregoing problems.
(II) technical scheme
To achieve the above object, as one aspect of the present disclosure, there is provided an LDO circuit comprising: the LDO module and the current detection and limiting module; wherein the method comprises the steps of
The LDO module comprises:
The inverting input end of the first comparator is used for accessing a bandgap reference voltage V BGR;
the grid electrode of the first PMOS is connected with the output end of the first comparator;
A resistor R1, the first end of which is connected with the drain electrode of the first PMOS;
A varistor R2, the first end of which is connected with the second end of the resistor R1, and the second end is grounded; and
The first input end of the two-input multiplexer is connected with the second end of the resistor R1, and the output end of the two-input multiplexer is connected with the non-inverting input end of the first comparator; and
The current detection and limiting module comprises:
The first end of the current sensor is connected with the grid electrode of the first PMOS, and the second end of the current sensor is connected with the second input end of the two-input multiplexer; and
And the non-inverting input end of the second comparator is connected with the second input end of the two-input multiplexer, the inverting input end of the second comparator is used for being connected with the reference voltage V BGR, and the output end of the second comparator is connected with the control end of the two-input multiplexer.
In some embodiments, the voltage connected to the non-inverting input terminal of the second comparator is V LIM, which is used for comparing the detected voltage V LIM with the reference voltage V BGR, and outputting the control signal ocl_en according to the comparison result;
The control end of the two-input multiplexer is used for receiving the control signal OCL_EN output by the second comparator and switching a current mode loop or a voltage mode loop according to the control signal OCL_EN.
In some embodiments, if V LIM is higher than V BGR, then the current loop mode is closed and the voltage loop is open; if V LIM is below V BGR, then the voltage mode loop is closed and the current loop mode is open.
In some embodiments, the current sensor comprises: and the grid electrode of the second PMOS is connected with the grid electrode of the first PMOS, the source electrode of the second PMOS is connected with the source electrode of the first PMOS, the drain electrode of the second PMOS is respectively connected with the first end of a resistor R LIM, the second input end of the two-input multiplexer and the non-inverting input end of the second comparator, and the second end of the resistor R LIM is grounded.
In some embodiments, the first PMOS and the second PMOS form a cascode current mirror; the current at the junction of the second PMOS and the resistor R LIM is the detection current I LIM, and the voltage at the junction is the detection voltage V LIM, which satisfy the following relation: v LIM＝ILIM×RLIM.
In some embodiments, the LDO circuit further comprises a reference module connected to the inverting input of the first comparator for providing the reference voltage V BGR.
In some embodiments, the LDO circuit further comprises a source follower buffer connected between the output of the first comparator and the gate of the first PMOS.
In some embodiments of the present invention, in some embodiments,Where Ratio represents a Ratio of the first PMOS to the second PMOS, I OUT represents an output current value of the LDO, and R LIM represents a detection resistance value.
According to another aspect of the disclosure, there is also provided a wireless charging system including the LDO circuit.
(III) beneficial effects
From the above technical solution, it can be seen that the LDO circuit and the wireless charging system of the present disclosure have at least one of the following advantages:
(1) The LDO circuit and the wireless charging system comprise a current detection and current limiting module, and can realize instant current detection and current limiting.
(2) The current limiting can be realized by switching the voltage mode loop and the current mode loop, and the two mode loops share one comparator, so that a charge pump module is avoided, and the cost and the complexity of a circuit are reduced.
Drawings
Fig. 1 is a schematic diagram of a conventional wireless power transmission system.
FIG. 2 is a schematic diagram of a conventional LDO circuit.
FIG. 3 is a schematic diagram of a conventional LDO detection and current limiting circuit.
FIG. 4 is a schematic diagram of an LDO circuit according to an embodiment of the present disclosure.
Fig. 5 is a timing diagram of an LDO with current limited on and current limited off according to an embodiment of the present disclosure.
Fig. 6 is a schematic diagram of an LDO circuit according to another embodiment of the present disclosure.
< Description of symbols >
P1-on-chip, P2-off-chip; 1-alternating current power supply, 2-rectifier, 3-LDO, 4-load, 5, 6-comparator, 7-charge pump; the system comprises a 10-LDO module, a 20-current detection and current limiting module; 101. 201-first comparator, 102, 202-second comparator, 103, 203-two-input multiplexer, 104, 204-current sensor, 205-source follower buffer, 206-limiter, 207-reference block, ER-external resistor, FRC-feedback resistor control (Feedback resistor control).
Detailed Description
For the purposes of promoting an understanding of the principles and advantages of the disclosure, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same.
The LDO provided by the disclosure is an LDO circuit with current detection and current limiting protection. Compared with the existing LDO, the LDO has the advantages that the functions of current detection and current limiting can be realized by only one comparator, and the charge pump module is avoided.
In one embodiment, as shown in fig. 4, the LDO circuit includes:
the first comparator 101 has an inverting input terminal, an in-phase input terminal, a power supply terminal and an output terminal, wherein the inverting input terminal is used for accessing a bandgap reference voltage V BGR, and the power supply terminal is used for accessing a power supply voltage VDD_5V; of course, the power supply voltage VDD is not limited to 5V;
A first PMOS MPl, the gate of which is connected to the output terminal of the first comparator 101, and the source and the drain of which are connected to a parasitic diode, the source of which is connected to the voltage V RECT;
a current sensor 104, a first end of which is connected with the gate of the first PMOS MP1, and a third end of which is connected with a voltage V RECT;
a resistor R1, a first end of which is connected with the drain electrode of the first PMOS MP 1;
A varistor R2, the first end of which is connected with the second end of the resistor R1, and the second end is grounded;
the inverting input end of the second comparator 102 is used for accessing the band gap reference voltage V BGR, and the non-inverting input end of the second comparator is connected with the second end of the current sensor and used for accessing the detection voltage V LIM;
The control end of the two-input multiplexer 103 is connected to the output end of the second comparator 102, the first input end is connected to the second end of the resistor R1, the second input end is connected to the second end of the current sensor 104 and the non-inverting input end of the second comparator 102, and the output end is connected to the non-inverting input end of the first comparator 101.
In addition, a load capacitor C LOAD, a first end of which is connected to the drain of the first PMOS, and a second end of which is grounded;
A load resistor R LOAD, the first end of which is connected with the drain electrode of the first PMOS, and the second end of which is grounded; wherein, the voltage at the connection part of the load capacitor C LOAD and the load resistor R LOAD is V OUT;
And the first end of the resistor R LIM is connected with the second end of the current sensor, the second end of the resistor R LIM is grounded, and the voltage at the connection part of the resistor R LIM and the current sensor is V LIM.
The LDO circuit of the embodiment comprises a voltage mode loop and a current mode loop. The voltage mode loop and the current mode loop are switched by opening and closing the voltage mode loop and the current mode loop by a multiplexer.
Specifically, when the load is larger and the load current I oUT is smaller, the second comparator outputs ocl_en as a low level, the control end of the two-input multiplexer receives the low level output by the second comparator, so that the voltage mode loop is closed, the current mode loop is opened (the path between the second end of the resistor R1 and the first input end of the two-input multiplexer, and the second end of the current sensor is disconnected from the second input end of the two-input multiplexer), and the current detector can continuously detect the output current at this time.
When the load is smaller and the load current I oUT becomes larger, V LIM increases, and when I oUT is higher than the current limit value I LIM, V LIM is caused to increase to be higher than the set value V BGR, the second comparator outputs ocl_en as a high level, and the control end of the two-input multiplexer receives the high level output by the second comparator, so that the voltage mode loop is opened, the current mode loop is closed, the output current is stabilized on the design maximum value at this time, and I oUT always limits the current value I LIM, thereby achieving the effects of current detection and current limit protection.
FIG. 5 is a timing diagram of an LDO circuit with current detection and current limiting protection according to the present embodiment. Wherein, the dark solid line represents the change condition of each key signal when the current limit is opened; the dashed lines represent the various key signal changes when the restriction is closed.
As shown in fig. 5, at time Φ0, the system is turned off and all signals are in an initial state. At the time phi 1, V DD is in the power-on stage, at the moment, all signals are gradually established, the system works normally, and at the moment, the system is in a voltage mode loop working state.
At time Φ2, for the ON current limiting function, i.e., OCL ON, since I OUT is higher than the current limiting value, V LIM is higher than V BGR, resulting in ocl_en being high, so that the system enters the current mode from the voltage mode, and as long as V LIM is higher than V BGR, its output current I OUT is always the current limiting value. For an unopened current limit function, i.e., OCL OFF, the system is always in a voltage mode state as shown by the dotted line, and the system is active with infinite current, I OUT may be above the current limit value, since OCL_EN is always low.
At time Φ3, for the ON-current limiting function, i.e., OCL ON, V DD starts to drop at this time, since I OUT is still higher than the current limiting value, the system is always in current mode, and its output current I OUT is always at the current limiting value. For the unopened current limit, OCL OFF, the system is always in voltage mode, and as V DD begins to drop, I OUT and V OUT also begin to drop slowly, as indicated by the dashed line.
At time Φ4, for the ON current limit function, OCL ON, i.e., I OUT starts to be lower than the current limit value due to V DD gradually decreasing, V LIM is lower than V BGR, and ocl_en is low, so that the system enters the voltage mode from the current mode, I OUT starts to decrease. For the unopened current limit function, OCL OFF, the system is always in voltage mode, and since V DD begins to fall, I OUT and V OUT also begin to fall slowly, at which point the dashed line coincides with the solid line and eventually returns to time Φ0.
In yet another embodiment, as shown in fig. 6, the LDO circuit includes: the LDO module and the current detection and limiting module; wherein the LDO module (LDO core) 10 comprises:
A limiter (Limiter) 206, the input end of which is connected to the rectified voltage V RECT and outputs a voltage V LIM;
A reference module (BGR) 207, an input end of which is connected to an output end of the limiter, for accessing the voltage V LIM and outputting a reference voltage V BGR;
a first comparator 201, the inverting input end of which is connected to the bandgap reference voltage V BGR, and the non-inverting input end of which is connected to the feedback voltage V FB;
A source follower buffer (source follower buffer) 205, one end of which is connected to the output end of the first comparator;
A first PMOS, the grid electrode of which is connected with the second end of the source electrode follower buffer, the source electrode of which is connected with the rectification voltage V RECT, and a parasitic diode is arranged between the source electrode and the drain electrode of which;
A capacitor C1, the first end of which is connected with the drain electrode of the PMOS;
a resistor R1, the first end of which is connected with the drain electrode of the PMOS;
A varistor R2, the first end of which is connected with the second end of the resistor R1, and the second end is grounded;
The control end of the two-input multiplexer 203 is used for accessing the control signal ocl_en, the first input end is connected with the second end of the resistor R1, the second input end is accessed with the voltage V LIM, and the output end is connected with the inverting input end of the first comparator.
The current detection and limiting module (over current limit)) 20 includes:
A second PMOS 204, the gate of which is connected to the gate of the first PMOS, and the source of which is connected to the source of the first PMOS;
a resistor R LIM, the first end of which is connected with the drain electrode of the second PMOS, and the second end of which is grounded;
The second comparator 202 has an inverting input terminal connected to the bandgap reference voltage V BGR, a non-inverting input terminal connected to the detection voltage V LIM, and outputs the control signal ocl_en.
In addition, an external capacitor C2 (external capatitor) having a first end connected to the drain of the first PMOS and a second end grounded;
And a load resistor R LOAD, the first end of which is connected with the drain electrode of the first PMOS, and the second end of which is grounded.
The current detection and limiting module is specifically described in this embodiment. The current detection and limiting module detects the current level of the second PMOS of the LDO through a current mirror, and causes a detection current to flow through an External Resistor (ER) R LIM to obtain a detection voltage V LIM, and the detection voltage V LIM switches the current mode loop or the voltage mode loop by comparing with V BGR. When V LIM is higher than V BGR, the system enters a current mode loop; when V LIM is below V BGR, the system enters the voltage mode loop. The current limiting value can be flexibly set through the size of the external resistor.
Where Ratio represents the Ratio of the main PMOS to the detection PMOS (Width Ratio of PMOS), alternatively, ratio is 1000:1, but is not limited thereto.
The switching current mode loop and the voltage mode loop achieve the effect similar to that of fig. 3, and compared with the structure of fig. 3, the switching current mode loop and the voltage mode loop reduce the use of a high-performance high-voltage comparator, avoid the use of a charge pump module and greatly reduce the circuit cost.
The present disclosure has been successfully applied to wireless charging system chips with overall efficiencies higher than 90% consistent with the expected results. Furthermore, the above definitions of the elements and methods are not limited to the specific structures, shapes or modes mentioned in the embodiments, and may be simply modified or replaced by those of ordinary skill in the art.
It should be noted that, the directional terms, such as "upper", "lower", "front", "rear", "left", "right", etc., in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Like elements are denoted by like or similar reference numerals throughout the drawings. Conventional structures or constructions will be omitted when they may cause confusion in understanding the present disclosure. And the shapes and dimensions of the various elements in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. In addition, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.
Furthermore, the word "comprising" or "comprises" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
The use of ordinal numbers such as "first," "second," "third," etc., in the description and the claims to modify a corresponding element does not by itself connote any ordinal number of elements or the order of manufacturing or use of the ordinal numbers in a particular claim, merely for enabling an element having a particular name to be clearly distinguished from another element having the same name.
Similarly, it should be appreciated that in the above description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.
While the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be understood that the foregoing embodiments are merely illustrative of the invention and are not intended to limit the invention, and that any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.

Claims (8)

1. An LDO circuit, comprising: the LDO module and the current detection and limiting module; wherein the method comprises the steps of
The LDO module comprises:
The inverting input end of the first comparator is used for accessing a bandgap reference voltage V BGR;
the grid electrode of the first PMOS is connected with the output end of the first comparator;
A resistor R1, the first end of which is connected with the drain electrode of the first PMOS;
a varistor R2, the first end of which is connected with the second end of the resistor R1, and the second end is grounded; and
The first input end of the two-input multiplexer is connected with the second end of the resistor R1, and the output end of the two-input multiplexer is connected with the non-inverting input end of the first comparator;
The current detection and limiting module comprises:
The first end of the current sensor is connected with the grid electrode of the first PMOS, and the second end of the current sensor is connected with the second input end of the two-input multiplexer;
The non-inverting input end of the second comparator is connected with the second input end of the two-input multiplexer, the inverting input end of the second comparator is used for being connected with the reference voltage V BGR, and the output end of the second comparator is connected with the control end of the two-input multiplexer;
wherein the current sensor comprises:
And the grid electrode of the second PMOS is connected with the grid electrode of the first PMOS, the source electrode of the second PMOS is connected with the source electrode of the first PMOS, the drain electrode of the second PMOS is respectively connected with the first end of a resistor R LIM, the second input end of the two-input multiplexer and the non-inverting input end of the second comparator, and the second end of the resistor R LIM is grounded.
2. The LDO circuit of claim 1, wherein,
The voltage connected to the non-inverting input end of the second comparator is V LIM, and is used for comparing the detection voltage V LIM with the reference voltage V BGR and outputting a control signal OCL_EN according to the comparison result;
The control end of the two-input multiplexer is used for receiving the control signal OCL_EN output by the second comparator and switching a current mode loop or a voltage mode loop according to the control signal OCL_EN.
3. The LDO circuit of claim 2, wherein if V LIM is higher than V BGR, then the current loop mode is closed and the voltage loop is open; if V LIM is below V BGR, then the voltage mode loop is closed and the current loop mode is open.
4. The LDO circuit of claim 1, wherein the first PMOS and second PMOS form a cascode current mirror; the current at the junction of the second PMOS and the resistor R LIM is the detection current I LIM, and the voltage at the junction is the detection voltage V LIM, which satisfy the following relation: v LIM＝ILIM×RLIM.
5. The LDO circuit of claim 1, further comprising a reference block coupled to an inverting input of the first comparator for providing the reference voltage V BGR.
6. The LDO circuit of claim 1, further comprising a source follower buffer connected between an output of the first comparator and a gate of the first PMOS.
7. The LDO circuit of claim 4, wherein,
Where Ratio represents a Ratio of the first PMOS to the second PMOS, I OUT represents an output current value of the LDO, and R LIM represents a detection resistance value.
8. A wireless charging system comprising the LDO circuit of any of claims 1-7.
CN201910474349.1A 2018-09-05 2019-05-31 LDO circuit and wireless charging system Active CN110134176B (en)

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CN209946732U (en) * 2018-09-05 2020-01-14 江西联智集成电路有限公司 LDO circuit and wireless charging system

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