CN109470908B

CN109470908B - Peak current detection method of CS-free sampling resistor

Info

Publication number: CN109470908B
Application number: CN201811245237.0A
Authority: CN
Inventors: 宗强; 刘准; 方芳; 吴寿化; 管磊
Original assignee: Shenzhen Chip Hope Micro-Electronics Ltd
Current assignee: Shenzhen Chip Hope Micro-Electronics Ltd
Priority date: 2018-10-24
Filing date: 2018-10-24
Publication date: 2021-08-24
Anticipated expiration: 2038-10-24
Also published as: CN109470908A

Abstract

The invention provides a peak current detection method of a CS-free sampling resistor, which is characterized by comprising a switching power tube current detection module and a switching capacitor charge-discharge peak detection module; the switch power tube current detection module comprises a first power tube, a second power tube, a current source structure and a resistor, and the switch capacitor charge-discharge peak value detection module comprises a first comparator, a second comparator, a first logic circuit, a second logic circuit, a first current source, a second current source, a first switch tube, a second switch tube, a third switch tube and a capacitor. The framework and the circuit provided by the invention do not need a current detection pin and a current sampling resistor, and reduce the system cost while ensuring the system performance.

Description

Peak current detection method of CS-free sampling resistor

[ technical field ]

The invention relates to the technical field of electronic circuits, in particular to a peak current detection method without a CS (Circuit switching) sampling resistor.

[ background art ]

FIG. 1 is a schematic diagram of a conventional BUCK power supply application control circuit, in which 101 is a rectifier chip and a power switch tube is integrated inside the chip; GND is zero potential, GND is reference zero potential (not necessarily zero potential); VIN passes through a resistor R104 and a capacitor C108 to provide starting current; the resistors R102 and R103 are voltage division resistors, are connected between Vout and gnd, and divide the voltage of Vout to be used as the input of the FB pin of the chip; l109 is an inductor and is connected between Vout and the CS pin; d106 is a freewheeling diode, the anode is connected with GND, and the cathode is connected with GND; r105 is a load resistor, C107 is a load capacitor and is connected between Vout and GND; r110 is a sampling resistor connected between the CS pin and gnd, and samples the current flowing through the inductor L109 and converts the current signal into a voltage signal, and hereinafter, the resistor R110 is referred to as a CS sampling resistor.

Figure 2 is a schematic diagram of a self-powered internal circuit. P201 is the first power transistor, which is turned on when the pfm _ H signal is high; p202 is the second power transistor, which is turned on when the P _ H signal is high. The non-self powered system is high at pfm _ H, the first and second power transistors are always conducting, and the current through the inductor is approximately equal to the current through the first and second power transistors.

When pfm _ H is high, the self-powered system firstly turns on the first and second power tubes, and the current flowing through the inductor is approximately equal to the current flowing through the first and second power tubes; then the first power tube is turned on, the second power tube is turned off, the diode D203 is turned on, and the capacitor C205 is charged, and at this time, the current flowing through the inductor is approximately equal to the current flowing through the first power tube. The self-powered system will have a portion of time to power the internal power source during pfm _ H is high, thereby keeping the internal power source VCC stable and achieving self-power.

The peak current mode is a control method for peak current turn-off, and in the existing peak current control mode, the magnitude of the output side inductive current needs to be detected through a CS sampling resistor, then the detected magnitude is compared with a preset peak current value to obtain the pulse turn-off time, and the pulse width is indirectly controlled by directly controlling the magnitude of the output side inductive current. The peak current detection method has high transient response speed, but the existing peak current detection method needs an additional pin for receiving a CS sampling signal and needs a CS sampling resistor, so that the hardware cost is increased.

[ summary of the invention ]

The invention solves the defects of the prior art and provides a peak current detection method without a CS sampling resistor.

In order to achieve the above purpose, the technical scheme of the invention is as follows:

a peak current detection method without a CS sampling resistor is characterized by comprising a switching power tube current detection module and a switching capacitor charge-discharge peak detection module; the switch power tube current detection module comprises a first power tube, a second power tube, a current source structure and a resistor, and the switch capacitor charge-discharge peak value detection module comprises a first comparator, a second comparator, a first logic circuit, a second logic circuit, a first current source, a second current source, a first switch tube, a second switch tube, a third switch tube and a capacitor; the positive electrode of the first comparator is connected with the positive electrode of the second comparator; the output end of the first comparator is connected with one end of the first logic circuit, the other end of the first logic circuit is connected with the first switch tube, the first switch tube is connected with a current source, one end of the second switch tube is connected with the first switch tube, the other end of the second switch tube is connected with the second current source, and the second current source is grounded; the third switching tube is connected with the anode of the second comparator; the output end of the second comparator is connected with the second logic circuit; one end of the capacitor is connected with the anode of the second comparator, and the other end of the capacitor is grounded. Furthermore, one end of the first power tube is connected with an input voltage, the other end of the first power tube is connected with the second power tube, one end of the second power tube is connected with the first power tube, the other end of the second power tube is grounded, the current source structure mirrors the current of the second power tube in any Miller ratio, one end of the resistor is connected with the output end of the current mirror, the other end of the resistor is grounded, and the current of the second power tube is converted into a voltage signal.

Furthermore, one end of the third switch tube is connected with a fixed potential, the other end of the third switch tube is connected with the positive plate of the capacitor, the control signal is pfm _ H, and when pfm _ H is low, the control signal is triggered to reset the voltage of the capacitor to an initial value V0; one end of the first current source is connected with the input voltage, the other end of the first current source is connected with the first switch tube, one end of the first switch tube is connected with the first current source, the other end of the first switch tube is connected with the capacitor, the control signal is ch, when the potential of the point A reaches a set value VCS _ REF, the signal of the ch is turned over, the first switch tube is disconnected, and the first current source, the first switch tube and the capacitor form a charging loop.

Furthermore, one end of a second current source is grounded, one end of the second current source is connected with a second switch tube, one end of the second switch tube is connected with the second current source, one end of the second switch tube is connected with a capacitor, a control signal is dch, the second current source, the second switch tube and the capacitor form a discharge loop, and when the discharge voltage of the capacitor is reduced to an initial value V0, the second comparator is turned over, and the second switch tube is disconnected.

Furthermore, the inverting input end of the first comparator is connected with the peak value comparison voltage VCS _ REF of the capacitor, the non-inverting input end of the first comparator is connected with the resistor, the comparison value of the first comparator is processed by the first logic circuit and is used as a control signal ch of the first switch, the non-inverting input end of the second comparator is connected with the capacitor, the inverting input end of the second comparator is connected with the initial voltage V0 of the capacitor, and the comparison value of the second comparator is processed by the second logic circuit and is used as a control signal dch of the second switch.

The invention has the beneficial effects that: the framework and the circuit provided by the invention do not need a current detection pin and a current sampling resistor, and reduce the system cost while ensuring the system performance.

[ description of the drawings ]

FIG. 1 is a schematic diagram of a conventional BUCK power application control circuit;

FIG. 2 is a schematic diagram of a self-powered internal control circuit;

FIG. 3 is a schematic diagram of a non-sampling resistor peak current detection circuit according to the present invention;

fig. 4 is a waveform diagram illustrating the operation of the present invention.

[ detailed description of the invention ]

The technical scheme of the invention is clearly and completely described in the following by combining specific examples and comparative examples. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 3, a circuit diagram of a peak current detection method without a CS sampling resistor includes a switching power tube current detection module 300 and a switching capacitor charge-discharge peak detection module 301; the switching power tube current detection module 300 comprises a first power tube P302, a second power tube P303, a current mirror 304 and an MOS tube 305, which form a current source structure, and a resistor R306, wherein the switching capacitor charging and discharging peak value detection module 301 comprises a first comparator 307, a second comparator 315, a first logic circuit 308, a second logic circuit 309, a first current source 310, a second current source 311, a first switching tube 312, a second switching tube 313, a third switching tube 317 and a capacitor C314; the positive pole of the first comparator 307 is connected to the positive pole of the second comparator 316; the output end of the first comparator 307 is connected with one end of the first logic circuit 308, the other end of the first logic circuit 308 is connected with the first switch tube 312, the first switch tube 312 is connected with a current source 310, one end of the second switch tube 313 is connected with the first switch tube 312, the other end of the second switch tube 313 is connected with the second current source 311, and the second current source 311 is grounded; the third switching tube 317 is connected to the anode of the second comparator 316; the output of the second comparator 316 is connected to the second logic 309; one end of the capacitor C314 is connected to the positive electrode of the second comparator 316, and the other end of the capacitor C314 is grounded.

One end of the first power tube P302 is connected to the input voltage, the other end is connected to the second power tube P303, one end of the second power tube P303 is connected to the first power tube P302, and the other end is grounded, the

current source structures

304 and 305 mirror the current of the second power tube P303 with any miller ratio, one end of the resistor R306 is connected to the output end of the current mirror, and the other end is grounded, so that the current of the second power tube P303 is converted into a voltage signal.

Wherein, one end of the third switch tube 316 is connected to the fixed potential, one end is connected to the positive plate of the capacitor C314, the control signal is pfm _ H, and when pfm _ H is triggered to be low, the voltage of the capacitor C314 is reset to the initial value V0; one end of the first current source 310 is connected to the input voltage, the other end of the first current source 310 is connected to the first switch tube 312, one end of the first switch tube 312 is connected to the first current source 310, the other end of the first current source is connected to the capacitor C314, the control signal is ch, when the potential of the point a reaches the set value VCS _ REF, the signal of the ch is inverted, the first switch tube 312 is turned off, the working waveform of the ch is as shown in fig. 4, and the first current source 310, the first switch tube 312 and the capacitor C314 form a charging loop.

One end of the second current source 311 is grounded, the other end of the second current source 311 is connected to the second switch tube 313, one end of the second switch tube 313 is connected to the second current source 311, the other end of the second current source is connected to the capacitor C314, the control signal is dch, the dch working waveform is shown in fig. 4, the second current source 311, the second switch tube 313 and the capacitor C314 form a discharge loop, and when the discharge voltage of the capacitor C314 is reduced to an initial value V0, the second comparator 315 is inverted, and the second switch tube 313 is turned off.

The inverting input of the first comparator 307 is connected to the peak comparison voltage VCS _ REF of the capacitor C314, the non-inverting input is connected to the resistor R306, the comparison value of the first comparator 307 is processed by the first logic circuit 308 and used as the control signal ch of the first switch 312, the non-inverting input of the second comparator 315 is connected to the capacitor C314, the inverting input is connected to the initial voltage V0 of the capacitor C314, and the comparison value of the second comparator 315 is processed by the second logic circuit 309 and used as the control signal dch of the second switch 313.

The switching power tube current detection module 300 mirrors the current of the second power tube P303 with any miller ratio, the current of the second power tube P303 maps an inductive current, the resistor R306 acts like a CS sampling resistor, and a voltage signal of the resistor R306 is detected to obtain a peak off signal. The switched capacitor charging and discharging peak value detection module 301 realizes peak value detection by charging and discharging the switched capacitor, determines charging time, determines charging and discharging time proportion, and also determines discharging end time, namely, time of system pulse turn-off, thereby completing peak value detection.

The peak current mode is a control method for peak current turn-off, a system with a CS sampling resistor detects peak current Ipk by detecting voltage on the CS resistor, and when the peak current reaches a preset value, a peak turn-off signal shunt _ H is output, so that a pulse signal is turned off, namely the pfm _ H signal is changed to be low, and a system power tube is turned off. Without the CS sampling resistor, the peak current needs to be detected by other methods. As can be seen from fig. 2, the current of the first power transistor is approximately equal to the current flowing through the inductor, and the first power transistor is generally a power transistor provided by a manufacturer, and it is difficult to directly mirror the current by using a current mirror structure. The second power tube is a built-in power tube and can be mirrored through a current mirror, and the current mirrored through the current mirror structure is mapped to the inductive current.

The current flowing through the first and second power tubes in a normal system (non-self-powered) is equal, the voltage across the resistor R306 is mapped to the inductor current, and the peak off signal shunt _ H can be obtained by comparing the voltage with the set peak voltage through the comparator 316.

For the self-powered system, when the first power tube and the second power tube are conducted simultaneously, the current of the second power tube is equal to the current of the first power tube. However, during self-power supply, the second power tube is turned off, the current is zero, and the peak current of the inductor cannot be mapped.

The implementation method of the invention is shown in figure 3 and mainly comprises two parts: the power tube current detection module 300 and the switched capacitor charge-discharge peak value detection module 301. The current mirror 304 and the MOS transistor 305 form a current source structure, the current of the second power transistor P303 is mirrored in any miller ratio, one end of the resistor R306 is connected to the output end of the current mirror, i.e., a point a in the figure, and the other end is grounded, so that the current of the second power transistor is converted into a voltage signal, at this time, the resistor R306 functions like a CS sampling resistor, a peak value turn-off signal can be obtained by detecting the voltage signal of the resistor R306, and the voltage of the point a is mapped to an inductive current.

The self-powered system without the CS sampling resistor cannot directly detect a peak value, the peak value detection is realized by charging and discharging a capacitor, 310 and 311 are current sources, 312 and 313 are switching tubes, a control signal of a first switching tube 312 is ch, when ch is high, the first switching tube 312 is closed, the first current source 310 charges a capacitor C314, the initial value of the capacitor C314 is V0, and the charging time is t 1; when the control signal of the second switch tube 313 is dch and dch is high, the second switch tube 313 is closed, the capacitor C314 is discharged to ground by the second current source 311, the discharge time is t2, and the waveform is as shown in fig. 4. The charge-discharge time ratio is equal to the ratio of the second current source discharge current 311 to the first current source charge current 310, i.e.: k-t 1-t 2-I311-I310. If the peak current Ipk is known, a VCS _ REF value can be obtained:

m is the Miller ratio of the current mirror.

When the voltage at the point a reaches a set value VCS _ REF, the first comparator 307 is turned over, the first switch tube 312 is turned off, the second switch tube 313 is turned on, the capacitor C314 starts to discharge, and when the voltage on the capacitor drops to an initial voltage V0, the second comparator 315 is turned over to output a peak turn-off signal shutd _ H, thereby completing peak current detection. The charging time is determined, the charging and discharging time proportion is determined, and the discharging end time, namely the time of system pulse turn-off is also determined.

The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiment, and all technical solutions belonging to the principle of the present invention belong to the protection scope of the present invention. Modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention.

Claims

1. A peak current detection device without a CS sampling resistor is characterized by comprising a switching power tube current detection module and a switching capacitor charge-discharge peak detection module which are connected together;

the switch power tube current detection module comprises a first power tube, a second power tube, a current source structure and a resistor;

the switch capacitor charging and discharging peak value detection module comprises a first comparator, a second comparator, a first logic circuit, a second logic circuit, a first current source, a second current source, a first switch tube, a second switch tube, a third comparator and a capacitor; the positive electrode of the first comparator is connected with the positive electrode of the third comparator; the output end of the first comparator is connected with one end of the first logic circuit, the other end of the first logic circuit is connected with the first switch tube, the first switch tube is connected with the first current source, one end of the second switch tube is connected with the first switch tube, the other end of the second switch tube is connected with the second current source, and the second current source is grounded; the third switching tube is connected between the first switching tube and the second switching tube; the output end of the second comparator is connected with the second logic circuit; one end of the capacitor is connected to the anode of the second comparator, and the other end of the capacitor is grounded;

the current source structure comprises a current mirror and an MOS (metal oxide semiconductor) tube; one end of the first power tube is connected with input voltage, the other end of the first power tube is connected with the second power tube, one end of the second power tube is connected with the first power tube, the other end of the second power tube is grounded, the current source structure mirrors the current of the second power tube in any Miller ratio, one end of the resistor is connected with the MOS tube, the other end of the resistor is grounded, and the current of the second power tube is converted into a voltage signal.

2. The device as claimed in claim 1, wherein the third switch tube is connected to a fixed potential at one end and to the positive plate of the capacitor at the other end, the control signal is pfm _ H, and when pfm _ H is low, the control signal triggers to reset the capacitor voltage to an initial value V0; one end of the first current source is connected with an input voltage, the other end of the first current source is connected with a first switch tube, one end of the first switch tube is connected with the first current source, the other end of the first switch tube is connected with a capacitor, a control signal is ch, when the potential of one end of the resistor reaches a set value VCS _ REF, a ch signal is inverted, the first switch tube is disconnected, and the first current source, the first switch tube and the capacitor form a charging loop.

3. The device as claimed in claim 1, wherein the second current source is connected to ground at one end and to a second switch tube at the other end, the second switch tube is connected to the second current source at one end and to a capacitor at the other end, the control signal is dch, the second current source, the second switch tube and the capacitor form a discharge loop, and when a discharge voltage of the capacitor decreases to an initial value V0, the second comparator is inverted and the second switch tube is turned off.

4. The peak current detector without the CS sampling resistor of claim 1, wherein the inverting input of the first comparator is connected to the peak comparison voltage VCS _ REF of the capacitor, the non-inverting input of the first comparator is connected to the resistor, the comparison value of the first comparator is processed by the first logic circuit and used as the control signal ch of the first switch tube, the non-inverting input of the second comparator is connected to the capacitor, the inverting input of the second comparator is connected to the initial voltage V0 of the capacitor, and the comparison value of the second comparator is processed by the second logic circuit and used as the control signal dch of the second switch tube.