CN209946732U - LDO circuit and wireless charging system - Google Patents

Abstract

The utility model provides a LDO circuit and wireless charging system, the LDO circuit includes: the LDO module and the current detection and limiting module; the LDO module includes: a first comparator with an inverting input terminal for accessing a bandgap reference voltage V_BGR(ii) a The grid of the first PMOS is connected with the output end of the first comparator; a resistor R1, a first end of which is connected with the drain electrode of the first PMOS; a rheostat R2, wherein the first end of the rheostat R2 is connected with the second end of the resistor R1; the first input end of the two-input multiplexer is connected with the second end of the resistor R1, and the output end of the two-input multiplexer is connected with the non-inverting input end of the first comparator; and the current sensing and limiting module includes: a first end of the current sensor is connected with the grid electrode of the first PMOS, and a second end of the current sensor is connected with a second input end of the selector; and second comparisonA non-inverting input terminal connected with the second input terminal of the two-input multiplexer, and an inverting input terminal for receiving a reference voltage V_BGRAnd the output end is connected with the control end of the two-input multiplexer. The LDO circuit and the wireless charging system reduce circuit cost and complexity.

Description

LDO circuit and wireless charging system

Technical Field

The disclosure relates to an LDO circuit with current detection and current limiting protection and a wireless charging system.

Background

In modern society, various electronic devices are used more and more, and the range and number thereof are increasing. These electronic devices basically require charging. Most of the current power supplies supply power to subsequent core circuits after passing through the LDO. Therefore, the stability of the power supply can be ensured, and the normal work of the circuit can be ensured.

As shown in fig. 1, in the wireless charging system, the receiver converts an ac power into a dc power, but the ripple in the dc power affects the normal operation of the load, so the load circuit is generally powered by the LDO. How to detect the output current of the LDO and how to protect the safety of the load circuit by the current limiting protection circuit are very important, especially for a wireless charging system, the control of the output current and the protection of the load are the key points for realizing a stable and high-efficiency wireless charging system.

FIG. 2 is a schematic diagram of a conventional LDO circuit. When VOUT is higher than the design value, VFB is higher than VBGR, causing the amplifier output to be higher than the design value, thereby reducing the voltage VGS between the gate and source of the power transistor PMOS, causing the main current path current to decrease, causing VOUT to decrease. Similarly, when VOUT is below the design value, the loop causes VOUT to increase. Thereby stabilizing VOUT at the design voltage. One significant drawback of the LDO circuit shown in fig. 2 is that the magnitude of the output current cannot be controlled. When the driving capability of the power tube is sufficient, the lower the load resistance of the power tube is, the larger the current flowing through the load is, and the current-limiting protection cannot be provided for the load in time. In practice, irreversible damage to the load is possible.

FIG. 3 is a schematic diagram of a conventional LDO detection and current limiting circuit, wherein the LDO comprisesThe current module loop and the voltage module loop realize the closing of the two loops through two comparators, and the two loops work independently and act on a G point together to realize the control of the output current and the output voltage. The disadvantage of this circuit is that two high performance comparators are required, which operate at high voltage in a wireless charging system, and therefore high voltage devices must be used, thereby greatly increasing the circuit area cost. Meanwhile, the circuit adopts a charge pump module, so that the G point is about V_RECT+V_THThe high-voltage working state not only increases the chip area, but also influences the system stability and the power transmission efficiency.

SUMMERY OF THE UTILITY MODEL

Technical problem to be solved

In view of the above problems, it is a primary object of the present disclosure to provide an LDO circuit and a wireless charging system, so as to solve at least one of the above problems.

(II) technical scheme

To achieve the above object, as one aspect of the present disclosure, there is provided an LDO circuit including: the LDO module and the current detection and limiting module; wherein

The LDO module comprises:

a first comparator having an inverting input for receiving a bandgap reference voltage V_BGR；

A first PMOS, a grid of which is connected with an output end of the first comparator;

a resistor R1, a first end of which is connected to the drain of the first PMOS;

a rheostat R2, wherein the first end of the rheostat R2 is connected with the second end of the resistor R1, and the second end of the rheostat R2 is grounded; and

a two-input multiplexer having a first input terminal connected to the second terminal of the resistor R1 and an output terminal connected to the non-inverting input terminal of the first comparator; and

the current sensing and limiting module includes:

a first end of the current sensor is connected with the grid electrode of the first PMOS, and a second end of the current sensor is connected with a second input end of the two-input multiplexer; and

a second comparator having a non-inverting input connected to the second input of the two-input multiplexer and an inverting input for receiving the reference voltage V_BGRAnd the output end is connected with the control end of the two-input multiplexer.

In some embodiments, the voltage applied to the non-inverting input of the second comparator is V_LIMFor comparing said detection voltage V_LIMAnd a reference voltage V_BGRAnd outputs a control signal OCL _ EN according to the comparison result;

and the control end of the two-input multiplexer is used for receiving the control signal OCL _ EN output by the second comparator and switching the current mode loop or the voltage mode loop according to the control signal OCL _ EN.

In some embodiments, if V_LIMHigher than V_BGRIf the current loop mode is closed, the voltage loop mode is opened; if V_LIMBelow V_BGRThe voltage mode loop is closed and the current loop mode is open.

In some embodiments, the current sensor comprises: a second PMOS with gate connected to the gate of the first PMOS, source connected to the source of the first PMOS, and drain connected to a resistor R_LIMThe first terminal of the two-input multiplexer, the second input terminal of the two-input multiplexer and the non-inverting input terminal of the second comparator are connected, and the resistor R_LIMThe second terminal of (a) is grounded.

In some embodiments, the first PMOS and the second PMOS form a cascode current mirror; the second PMOS and the resistor R_LIMThe current at the junction is the detection current I_LIMThe voltage at the junction is the detection voltage V_LIMAnd both satisfy the following relation: v_LIM＝I_LIM×R_LIM。

In some embodiments, the LDO circuit further comprises a reference module connected to the inverting input of the first comparator for providing the reference voltage V_BGR。

In some embodiments, the LDO circuit further comprises a source follower buffer connected between the output of the first comparator and the gate of the first PMOS.

In some embodiments of the present invention, the,

wherein Ratio represents the Ratio of the first PMOS to the second PMOS, I_OUTIndicating the output current value, R, of the LDO_LIMIndicating the detection resistance value.

According to another aspect of the disclosure, a wireless charging system is also provided, which includes the LDO circuit.

(III) advantageous effects

From above-mentioned technical scheme can see, this disclosure LDO circuit and wireless charging system have one of them of following beneficial effect at least:

(1) the LDO circuit and the wireless charging system comprise a current detection and current limiting module, and can realize instant current detection and current limiting.

(2) Current limiting can be achieved by switching a voltage mode loop and a current mode loop, the two mode loops share one comparator, a charge pump module is avoided, and circuit cost and complexity are reduced.

Drawings

Fig. 1 is a schematic diagram of a conventional wireless power transmission system.

FIG. 2 is a schematic diagram of a conventional LDO circuit.

FIG. 3 is a schematic diagram of a conventional LDO detection and current limiting circuit.

FIG. 4 is a schematic diagram of an LDO circuit according to an embodiment of the present disclosure.

FIG. 5 is a timing diagram of an LDO with current limit on and current limit off according to an embodiment of the present disclosure.

FIG. 6 is a schematic diagram of an LDO circuit according to another embodiment of the present disclosure.

< description of symbols >

P1-above slice, P2-below slice; 1-alternating current power supply, 2-rectifier, 3-LDO, 4-load, 5, 6-comparator and 7-charge pump; 10-LDO module, 20-current detection and current limiting module; 101. 201-first comparator, 102, 202-second comparator, 103, 203-two input multiplexer, 104, 204-current sensor, 205-source follower buffer, 206-limiter, 207-reference module, ER-external resistance, FRC-Feedback resistance control (Feedback resistor control).

Detailed Description

For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

The LDO provided by the disclosure is an LDO circuit with current detection and current limiting protection. Compared with the existing LDO, the current detection and current limiting function can be realized by only using one comparator, and the use of a charge pump module is avoided.

In an embodiment, as shown in fig. 4, the LDO circuit includes:

a first comparator 101 having an inverting input terminal for receiving a bandgap reference voltage V, an inverting input terminal, a power supply terminal and an output terminal_BGRThe power supply end is used for connecting power supply voltage VDD _ 5V; of course, the power supply voltage VDD is not limited to 5V;

a first PMOS MP1 having a gate connected to the output terminal of the first comparator 101, a parasitic diode connected between the source and the drain, and a source connected to a voltage V_RECT；

A current sensor 104 having a first terminal connected to the gate of the first PMOS MP1 and a third terminal voltage V_RECT；

A resistor R1, a first end of which is connected with the drain of the first PMOS MP 1;

a rheostat R2, wherein the first end of the rheostat R2 is connected with the second end of the resistor R1, and the second end of the rheostat R2 is grounded;

a second comparator 102 having an inverting input terminal for receiving the bandgap reference voltage V_BGRThe non-inverting input end is connected with the second end of the current sensor and is used for being connected with the detection voltage V_LIM；

A control terminal of the two-input multiplexer 103 is connected to the output terminal of the second comparator 102, a first input terminal thereof is connected to the second terminal of the resistor R1, a second input terminal thereof is connected to the second terminal of the current sensor 104 and the non-inverting input terminal of the second comparator 102, and an output terminal thereof is connected to the non-inverting input terminal of the first comparator 101.

In addition, a load capacitor C_LOADThe first end of the first PMOS is connected with the drain electrode of the first PMOS, and the second end of the first PMOS is grounded;

a load resistor R_LOADThe first end of the first PMOS is connected with the drain electrode of the first PMOS, and the second end of the first PMOS is grounded; wherein the load capacitance C_LOADAnd the load resistor R_LOADAt a voltage of V_OUT；

A resistor R_LIMA first end of the resistor is connected with the second end of the current sensor, a second end of the resistor is grounded, and the resistor R_LIMThe voltage at the junction with the current sensor is V_LIM。

The LDO circuit of this embodiment includes a voltage mode loop and a current mode loop. The voltage mode loop and the current mode loop are switched by opening and closing the voltage mode loop and the current mode loop through a multiplexer.

Specifically, when the load is large, a load current I flows_OUTIn the smaller case, the second comparator output OCL _ EN is low, the control terminal of the two-input multiplexer receives the low level of the second comparator output, so that the voltage mode loop is closed, the current mode loop is open (the path between the second terminal of the resistor R1 and the first input terminal of the two-input multiplexer is closed, and the path between the second terminal of the current sensor and the second input terminal of the two-input multiplexer is open), and the current detector can continuously detect the output current.

When the load is small, a load current I flows_OUTBecome large, V_LIMIncrease at I_OUTAbove the restriction value I_LIMIn the case of (2), result in V_LIMIncrease above the set value V_BGRWhen the output OCL _ EN of the second comparator is high level, the control end of the two-input multiplexer receives the output of the second comparatorSo that the voltage mode loop is open and the current mode loop is closed, at which time the output current will settle at the design maximum, I_OUTAlways has a current limiting value I_LIMTherefore, the current detection and current limiting protection effects are achieved, and therefore the LDO circuit of the embodiment achieves current detection and current limiting.

FIG. 5 is a timing diagram of the LDO circuit with current detection and current limiting protection according to the present embodiment. Wherein, the solid line with dark color represents the change condition of each key signal when the current limit is opened; the dashed lines indicate the variation of the respective critical signals when the current limit is closed.

As shown in fig. 5, at time Φ 0, the system is off and all signals are in the initial state. At time Φ 1, V_DDAnd in a power-on stage, all signals are gradually established at the moment, the system works normally, and the system is in a voltage mode loop working state at the moment.

At time Φ 2, for the current limit function to be turned ON, i.e. OCL ON, due to I_OUTAbove the limiting value, such that V_LIMHigher than V_BGROCL _ EN is caused to be high, thereby causing the system to enter current mode from voltage mode as long as V_LIMHigher than V_BGRIts output current I_OUTAlways at the current limit value. For the unopened current limiting function, i.e. OCL OFF, since OCL _ EN is always low, the system is always in voltage mode, as shown by the dotted line, the system has no current action, I_OUTMay be higher than the restriction value.

At time Φ 3, for the current limiting function to be turned ON, i.e. OCL ON, V_DDBegins to fall due to I_OUTStill above the current limit value, so that the system is always in current mode, outputting a current I_OUTAlways at the current limit value. For the unopened current limit function, i.e., OCL OFF, the system is always in voltage mode since V_DDBegin to fall, I_OUTAnd V_OUTIt also begins to slowly fall as shown by the dashed line.

At time Φ 4, for the current limit function to be turned ON, i.e., OCL ON, due to V_DDGradually decrease so that I_OUTInitially below the restriction value, V_LIMBelow V_BGRCausing OCL _ EN to be low, thereby causing the system to go from current mode to voltage mode, I_OUTAnd begins to fall. For the unopened current limit function, i.e., OCL OFF, the system is always in voltage mode since V_DDBegin to fall, I_OUTAnd V_OUTIt also begins to slowly fall, where the dashed line coincides with the solid line and eventually returns to time Φ 0.

In yet another embodiment, as shown in fig. 6, the LDO circuit includes: the LDO module and the current detection and limiting module; wherein the LDO module (LDO core)10 includes:

a Limiter (Limiter)206, the input of which is connected to the rectified voltage V_RECTAnd output a voltage V_LIM；

A reference Block (BGR)207, the input of which is connected to the output of the limiter, for receiving a voltage V_LIMAnd outputs a reference voltage V_BGR；

A first comparator 201, the inverting input terminal of which is connected to the bandgap reference voltage V_BGRA feedback voltage V is connected to the non-inverting input terminal_FB；

A source follower buffer (source follower buffer)205, one end of which is connected to the output end of the first comparator;

a first PMOS with gate connected to the second end of the source follower buffer and source connected to the rectified voltage V_RECTA parasitic diode is arranged between the source electrode and the drain electrode;

a capacitor C1, a first end of which is connected with the drain electrode of the PMOS;

a resistor R1, a first end of which is connected with the drain of the PMOS;

a rheostat R2, wherein the first end of the rheostat R2 is connected with the second end of the resistor R1, and the second end of the rheostat R2 is grounded;

a two-input multiplexer 203 having a control terminal for receiving a control signal OCL _ EN, a first input terminal connected to the second terminal of the resistor R1, and a second input terminal for receiving a voltage V_LIMAnd the output end of the comparator is connected with the inverting input end of the first comparator.

The current detection and current limiting module (over current limit) 20 includes:

a second PMOS 204 having a gate connected to the gate of the first PMOS and a source connected to the source of the first PMOS;

resistance R_LIMThe first end of the second PMOS is connected with the drain electrode of the second PMOS, and the second end of the second PMOS is grounded;

a second comparator 202 having an inverting input terminal connected to the bandgap reference voltage V_BGRThe in-phase input end is connected with a detection voltage V_LIMAnd outputs the control signal OCL _ EN.

In addition, an external capacitor C2(external capacitor) having a first terminal connected to the drain of the first PMOS and a second terminal connected to ground;

a load resistor R_LOADAnd the first end of the second PMOS is connected with the drain electrode of the first PMOS, and the second end of the second PMOS is grounded.

The current detection and limiting module is specifically described in this embodiment. The current detection and current limiting module detects the current of the second PMOS of the LDO in the form of a current mirror and makes the detection current flow through an External resistor (ER, External Res) R_LIMObtaining a detection voltage V_LIMDetecting the voltage V_LIMThrough and V_BGRThe comparison switches either the current mode loop or the voltage mode loop. When V is_LIMHigher than V_BGRThe system enters a current mode loop; when V is_LIMBelow V_BGRThe system enters a voltage mode loop. The current limiting value can be flexibly set through the size of the external resistor.

Wherein Ratio represents the Ratio (Width Ratio) of the main PMOS to the detection PMOS, and optionally, Ratio is 1000: 1, but not limited thereto.

The current mode loop and the voltage mode loop are switched to achieve the effect similar to that of the structure in the figure 3, compared with the structure in the figure 3, the high-performance high-voltage comparator is reduced, a charge pump module is avoided, and the circuit cost is greatly reduced.

The present disclosure has been successfully applied in wireless charging system chips with overall efficiencies above 90%, consistent with expected results. Further, the above definitions of the various elements and methods are not limited to the various specific structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by those of ordinary skill in the art.

It should be noted that directional terms, such as "upper", "lower", "front", "rear", "left", "right", and the like, mentioned in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure. And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.

Furthermore, the word "comprising" or "comprises" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify a corresponding element does not by itself connote any ordinal number of the element or any ordering of one element from another or the order of manufacture, and the use of the ordinal numbers is only used to distinguish one element having a certain name from another element having a same name.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that is, the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, disclosed aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.

The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.

Claims (9)

1. An LDO circuit, comprising: the LDO module and the current detection and limiting module; wherein

The LDO module comprises:

a first comparator having an inverting input for receiving a bandgap reference voltage V_BGR；

A first PMOS, a grid of which is connected with an output end of the first comparator;

a resistor R1, a first end of which is connected to the drain of the first PMOS;

a rheostat R2, wherein the first end of the rheostat R2 is connected with the second end of the resistor R1, and the second end of the rheostat R2 is grounded; and

a two-input multiplexer having a first input terminal connected to the second terminal of the resistor R1 and an output terminal connected to the non-inverting input terminal of the first comparator; and

the current sensing and limiting module includes:

a first end of the current sensor is connected with the grid electrode of the first PMOS, and a second end of the current sensor is connected with a second input end of the two-input multiplexer; and

a second comparator having a non-inverting input connected to the second input of the two-input multiplexer and an inverting input for receiving the reference voltage V_BGRAnd the output end is connected with the control end of the two-input multiplexer.

2. The LDO circuit of claim 1,

the voltage accessed to the non-inverting input end of the second comparator is a detection voltage V_LIMThe second comparator is used for comparing the detection voltage V_LIMAnd a reference voltage V_BGRAnd outputs a control signal OCL _ EN according to the comparison result;

and the control end of the two-input multiplexer is used for receiving the control signal OCL _ EN output by the second comparator and switching the current mode loop or the voltage mode loop according to the control signal OCL _ EN.

3. The LDO circuit of claim 2, wherein if the detected voltage V is V_LIMAbove the reference voltage V_BGRIf the current loop mode is closed, the voltage loop mode is opened; if the voltage V is detected_LIMBelow the reference voltage V_BGRThe voltage mode loop is closed and the current loop mode is open.

4. The LDO circuit of claim 1, wherein the current sensor comprises: a second PMOS with gate connected to the gate of the first PMOS, source connected to the source of the first PMOS, and drain connected to a resistor R_LIMThe first terminal of the two-input multiplexer, the second input terminal of the two-input multiplexer and the non-inverting input terminal of the second comparator are connected, and the resistor R_LIMThe second terminal of (a) is grounded.

5. The LDO circuit of claim 4, wherein the first PMOS and the second PMOS form a cascode current mirror; the second PMOS and the resistor R_LIMThe current at the junction is the detection current I_LIMThe voltage at the junction is the detection voltage V_LIMAnd both satisfy the following relation: v_LIM＝I_LIM×R_LIM。

6. The LDO circuit of claim 1, further comprising a reference module coupled to an inverting input of the first comparator for providing the reference voltage V_BGR。

7. The LDO circuit of claim 1, further comprising a source follower buffer connected between the output of the first comparator and the gate of the first PMOS.

8. The LDO circuit of claim 4,

wherein Ratio represents the Ratio of the first PMOS to the second PMOS, I_OUTIndicating the output current value, R, of the LDO_LIMIndicating the detection resistance value.

9. A wireless charging system comprising the LDO circuit according to any of claims 1 to 8.

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