CN110120366B - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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Publication number
CN110120366B
CN110120366B CN201810117810.3A CN201810117810A CN110120366B CN 110120366 B CN110120366 B CN 110120366B CN 201810117810 A CN201810117810 A CN 201810117810A CN 110120366 B CN110120366 B CN 110120366B
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groove
area
region
hole
layer
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CN110120366A (en
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杨青
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions

Abstract

A semiconductor device and a method of forming the same, the method comprising: obtaining a plurality of discrete contact hole regions in the second trench region; acquiring a second groove correction area positioned in the second groove area according to the position of the contact hole area, wherein the width of the second groove correction area is smaller than that of the second groove area; respectively forming sacrificial layers on the dielectric layer second groove correction area and the first groove area; forming a first side wall and a second side wall on the dielectric layer; forming a barrier layer on the second groove region exposed by the second side wall, wherein the distance from the edge of the barrier layer to the edge of the sacrificial layer on the adjacent first groove region is equal to the minimum distance between the first side wall and the second side wall; then removing the sacrificial layer; and etching the dielectric layer by taking the barrier layer, the first side wall and the second side wall as masks, forming a first groove in the dielectric layer at two sides of the first side wall, and forming a second groove in the dielectric layer second groove correction area. The performance of the semiconductor device is improved.

Description

Semiconductor device and method of forming the same
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
With the continuous progress of semiconductor integrated circuit technology, as semiconductor devices are scaled down to the deep submicron range, high-performance and high-density connections between semiconductor devices need to be realized through an interconnection structure. Parasitic resistance and parasitic capacitance are easily formed in an interconnection structure, so that parasitic effect occurs, and time delay of metal connection line transmission is caused, and people face the problem how to overcome the problem that RC (R refers to resistance and C refers to capacitance) delay is obviously increased due to rapid increase of connection length.
In order to overcome the parasitic effect in interconnection, in the integration process of large scale integrated circuit back end of line interconnection, on one hand, the parasitic capacitance is proportional to the relative dielectric constant K of the insulating medium of the interconnection layer, so that low K material, especially ultra-low dielectric constant (Ult)ra-low dielectric constant, ULK) material instead of conventional SiO2Dielectric materials have become a demand for satisfying the development of high-speed chips, and on the other hand, since copper has a low resistivity, an excellent electromigration resistance and a high reliability, the interconnection resistance of metal can be lowered, thereby reducing the total interconnection delay effect, the conventional aluminum interconnection has been changed to a low-resistance copper interconnection.
However, the performance of the semiconductor device formed by the prior art is poor.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which are used for improving the performance of the semiconductor device.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, including: providing a medium layer, wherein the medium layer comprises a first groove area and a plurality of second groove areas, the first groove areas and the second groove areas are mutually separated, the first groove areas are positioned between the adjacent second groove areas, and the width of each second groove area is greater than that of each first groove area; obtaining a plurality of discrete contact hole regions in the second trench region; acquiring a second groove correction area positioned in the second groove area according to the position of the contact hole area, wherein the second groove correction area covers the contact hole area, and the width of the second groove correction area is smaller than that of the second groove area; respectively forming sacrificial layers on the dielectric layer second groove correction area and the first groove area; forming a first side wall and a second side wall on the dielectric layer, wherein the first side wall is positioned on the side walls of the sacrificial layer on the first groove area along the two sides of the width direction of the first groove area, and the second side wall is positioned on the side walls of the sacrificial layer on the second groove correction area along the two sides of the width direction of the second groove correction area; forming a barrier layer on the second groove region exposed by the second side wall, wherein the distance from the edge of the barrier layer to the edge of the sacrificial layer on the adjacent first groove region is equal to the minimum distance between the first side wall and the second side wall; after the barrier layer is formed, removing the sacrificial layer; and after removing the sacrificial layer, etching the dielectric layer by taking the barrier layer, the first side wall and the second side wall as masks, forming a first groove in the dielectric layer at two sides of the first side wall, and forming a second groove in the dielectric layer second groove correction area.
Optionally, the width of the second groove correction area is equal to the width of the first groove area; alternatively, the width of the second groove modification region is smaller or larger than the width of the first groove region.
Optionally, the width of the second groove modification region is 95% to 105% of the width of the first groove region.
Optionally, the second groove correction area includes a connection area and a plurality of discrete hole correction areas, an extending direction of the hole correction areas is parallel to a length direction of the second groove area, projections of the plurality of hole correction areas on an edge of the second groove area along a width direction of the second groove area are discrete from each other, and projections of the plurality of hole correction areas on an edge of the second groove area along a length direction of the second groove area are discrete from each other; and two ends of the connecting area are respectively connected with the hole correcting area, and the hole correcting areas are respectively positioned at two sides of the connecting area in the length direction of the second groove area.
Optionally, the number of the hole modification regions is two; the two hole correction areas are respectively a first hole correction area and a second hole correction area; the extending direction of the first hole correcting area and the second hole correcting area is parallel to the length direction of the second groove area; the two ends of the connecting area are respectively connected with the first hole correcting area and the second hole correcting area, and the first hole correcting area and the second hole correcting area are respectively located on the two sides of the connecting area in the length direction of the second groove area.
Optionally, the first hole correction area and the second hole correction area are respectively located at two side edges of the second groove area in the width direction of the second groove area.
Optionally, the two ends of the connection region are a first end and a second end, the first end is connected with the first hole correction region, the second end is connected with the second hole correction region, and the direction from the first end to the second end is parallel to the width direction of the second groove region.
Optionally, the sacrificial layer is made of amorphous silicon or amorphous carbon; the first side wall and the second side wall are made of silicon nitride; the dielectric layer is made of silicon oxide or a low-K dielectric material.
Optionally, the method for forming the sacrificial layer includes: forming a sacrificial film on the surface of the dielectric layer; forming a photoresist film on the sacrificial film; carrying out an exposure process on the photoresist film by adopting a mask plate, and forming an exposure area and a non-exposure area in the photoresist film; developing the photoresist film to remove the non-exposure area of the photoresist film and form a photoresist layer in the exposure area of the photoresist film; etching the sacrificial film by taking the photoresist layer as a mask until the surface of the dielectric layer is exposed to form the sacrificial layer; and removing the photoresist layer after etching the sacrificial film.
Optionally, the manufacturing method of the mask includes: acquiring photoetching mask layer patterns corresponding to the patterns of the second groove correction area and the first groove area; carrying out OPC correction on the photoetching mask layer pattern to obtain a corrected pattern; and manufacturing a mask according to the corrected graph.
Optionally, the method for forming the first side wall and the second side wall includes: forming side wall films on the side wall and the top of the sacrificial layer and the surface of the dielectric layer exposed by the sacrificial layer; and etching the side wall film back until the surface of the dielectric layer is exposed to form the first side wall and the second side wall.
Optionally, the material of the barrier layer includes a photoresist material; the method for forming the barrier layer comprises the following steps: forming barrier films on the exposed dielectric layers of the sacrificial layer, the first side wall and the second side wall and on the sacrificial layer, the first side wall and the second side wall; and exposing and developing the barrier film to form the barrier film into the barrier layer.
Optionally, the method further includes: after the first groove and the second groove are formed, removing the barrier layer, the first side wall and the second side wall; after the barrier layer, the first side wall and the second side wall are removed, a first conductive layer is formed in the first groove, and a second conductive layer is formed in the second groove; forming a first plug on the first conductive layer, the first plug and the first conductive layer being electrically connected; forming a plurality of second plugs on the second conductive layer, wherein the second plugs are respectively positioned on the contact hole regions; the second plug is electrically connected to the second conductive layer.
The present invention also provides a semiconductor device comprising: the dielectric layer comprises a first groove area and a plurality of second groove areas, the first groove areas and the second groove areas are mutually separated, the first groove areas are positioned between the adjacent second groove areas, and the width of each second groove area is greater than that of each first groove area; a plurality of discrete contact hole regions located in the second trench region; a second trench trim region in the second trench region, the second trench trim region including a contact hole region, the second trench trim region having a width less than a width of the second trench region; the first grooves are respectively positioned in the first groove area of the dielectric layer and in partial dielectric layers on two sides of the first groove area; and a second recess in the dielectric layer second recess trim region.
Optionally, the width of the second groove correction area is equal to the width of the first groove area; alternatively, the width of the second groove modification region is smaller or larger than the width of the first groove region.
Optionally, the width of the second groove modification region is 95% to 105% of the width of the first groove region.
Optionally, the second groove correction area includes a connection area and a plurality of discrete hole correction areas, an extending direction of the hole correction areas is parallel to a length direction of the second groove area, projections of the plurality of hole correction areas on an edge of the second groove area along a width direction of the second groove area are discrete from each other, and projections of the plurality of hole correction areas on an edge of the second groove area along a length direction of the second groove area are discrete from each other; and two ends of the connecting area are respectively connected with the hole correcting area, and the hole correcting areas are respectively positioned at two sides of the connecting area in the length direction of the second groove area.
Optionally, the number of the hole modification regions is two; the two hole correction areas are respectively a first hole correction area and a second hole correction area; the extending direction of the first hole correcting area and the second hole correcting area is parallel to the length direction of the second groove area; the two ends of the connecting area are respectively connected with the first hole correcting area and the second hole correcting area, and the first hole correcting area and the second hole correcting area are respectively located on the two sides of the connecting area in the length direction of the second groove area.
Optionally, the two ends of the connection region are a first end and a second end, the first end is connected with the first hole correction region, the second end is connected with the second hole correction region, and the direction from the first end to the second end is parallel to the width direction of the second groove region.
Optionally, the method further includes: the first conducting layer is positioned in the first groove; the second conducting layer is positioned in the second groove; a first plug on the first conductive layer, the first plug and the first conductive layer being electrically connected; and the second plugs are respectively positioned on the contact hole regions, and the second plugs are electrically connected with the second conductive layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming the semiconductor device provided by the technical scheme of the invention, a plurality of discrete contact hole areas are obtained in the second groove area, and the contact hole areas are areas projected to the second groove area by the subsequent second plug. A second groove correction region located in the second groove region is obtained according to the position of the contact hole region. The sacrificial layer is formed on the second groove correction region and the first groove region, and the pattern of the sacrificial layer is required to be according to the patterns of the second groove correction region and the first groove region. Because the width of the second groove correction area is smaller than that of the second groove area, the difference between the widths of the second groove correction area and the first groove area is reduced, so that in the pattern of the sacrificial layer determined according to the patterns of the second groove correction area and the first groove area, the problem that the resolution ratio of the sacrificial layer on the first groove area corresponding to the pattern on the mask is too low is avoided, the size of the sacrificial layer formed on the first groove area is consistent with the size of the pattern of the first groove, the requirement of process design is met, and the performance of a semiconductor device is improved.
Further, the manufacturing method of the mask used in the process of forming the sacrificial layer comprises the following steps: acquiring photoetching mask layer patterns corresponding to the patterns of the second groove correction area and the first groove area; carrying out OPC correction on the photoetching mask layer pattern to obtain a corrected pattern; and manufacturing a mask according to the corrected graph. The size of the corrected graph corresponding to the first groove area is prevented from exceeding the lower limit size of the test graph used when the OPC correction model is established, and therefore the resolution of the corrected graph in the mask is improved.
Drawings
Fig. 1 to 3 are schematic structural views of a semiconductor device formation process;
fig. 4 to 11 are schematic structural diagrams illustrating a semiconductor device forming process according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of semiconductor devices formed by the prior art is poor.
Fig. 1 to 3 are schematic structural views of a semiconductor device formation process.
Referring to fig. 1, a dielectric layer 100 is provided, the dielectric layer 100 including a plurality of first trench regions 101 and a plurality of second trench regions 102, the plurality of first trench regions 101 being located between adjacent second trench regions 102.
Referring to fig. 2, a sacrificial layer 120 is formed on the dielectric layer 100 in the first and second trench regions 101 and 102, respectively; and forming side walls 130 on the sidewalls of the sacrificial layer 120.
Referring to fig. 3, after forming the sidewall spacers 130, the sacrificial layer 120 (refer to fig. 2) is removed; after removing the sacrificial layer 120, the dielectric layer 100 is etched by using the spacers 130 as masks, a first groove 140 is formed in the first groove region 101 of the dielectric layer 100 and in a part of the dielectric layer 100 on both sides of the first groove region 101, and a second groove 150 is formed in the second groove region 102 of the dielectric layer 100.
The following steps are also included: after the first groove 140 and the second groove 150 are formed, the side wall 130 is removed; thereafter, a first conductive layer is formed in the first groove 140; forming a second conductive layer in the second groove 150; forming a first plug on the first conductive layer; and forming a second plug and a third plug on the second conductive layer, wherein the second plug and the third plug are respectively electrically connected with different top material layers. A certain distance is required between the second plug and the third plug in the width direction of the second groove region 102. It is therefore common to design the width of the second conductive layer to be greater than the width of the first conductive layer, and correspondingly, the width of the second slot region 102 is greater than the width of the first slot region 101.
The pattern of the mask required for forming the sacrificial layer is made according to the pattern obtained by correcting the pattern of the photoetching mask layer corresponding to the second groove region 102 and the first groove region 101.
Since the width of the second groove area 102 is larger than the width of the first groove area 101, the width of the first corrected pattern is smaller in the corrected patterns obtained after the OPC correction, and the size of the first corrected pattern easily exceeds the lower limit size of the test pattern used when the OPC correction model is established, resulting in poor lithographic resolution of the first corrected pattern. In this way, when the exposure condition is slightly changed by using the mask, the number of the weak points in the first exposure pattern obtained by the first correction pattern is increased, so that the shape of the first exposure pattern is greatly different from that of the first groove area 101. So that the size of the first conductive layer subsequently formed in the first trench region 101 cannot meet the requirements of process design.
On the basis, the invention provides a method for forming a semiconductor device, which obtains a plurality of discrete contact hole regions in the second groove region; acquiring a second groove correction area positioned in the second groove area according to the position of the contact hole area; respectively forming sacrificial layers on the dielectric layer second groove correction area and the first groove area; forming a first side wall and a second side wall on the dielectric layer; forming a barrier layer on the second groove region exposed by the second side wall; then removing the sacrificial layer; and etching the dielectric layer by taking the barrier layer, the first side wall and the second side wall as masks, forming a first groove in the dielectric layer at two sides of the first side wall, and forming a second groove in the dielectric layer second groove correction area. The method improves the performance of the semiconductor device.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 11 are schematic structural diagrams illustrating a semiconductor device forming process according to an embodiment of the present invention.
Referring to fig. 4, a dielectric layer 200 is provided, the dielectric layer 200 including a first groove region 201 and a plurality of second groove regions 202, the first groove region 201 and the second groove regions 202 being separated from each other, the first groove region 201 being located between adjacent second groove regions 202, a width H2 of the second groove regions 202 being greater than a width H1 of the first groove region 201.
The dielectric layer 200 is made of a low-K dielectric material (the low-K dielectric material refers to a dielectric material with a relative dielectric constant of 2.6 or more and less than 3.9) or an ultra-low-K dielectric material (the ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant of less than 2.6). When the dielectric layer 200 is made of a low-K dielectric material or an ultra-low-K dielectric material, the dielectric layer 200 is made of SiOH,SiCOH, FSG (fluorine doped silica), BSG (boron doped silica), PSG (phosphorus doped silica), BPSG (boron phosphorus doped silica), hydrogen silsesquioxane (HSQ, (HSiO)1.5)n) Or methylsilsesquioxane (MSQ, (CH)3SiO1.5)n). In this embodiment, the dielectric layer 200 is made of an ultra-low K dielectric material, and the ultra-low K dielectric material is SiCOH.
The extending direction of the first trench region 201 is perpendicular to the width direction of the first trench region 201 and parallel to the surface of the dielectric layer 200.
The second trench region 202 extends in a direction perpendicular to the width of the second trench region 202 and parallel to the surface of the dielectric layer 200.
The surface of the second groove area 202 of the dielectric layer 200 is in a strip shape, specifically, the second groove area 202 has a first side and a second side opposite to each other in the width direction of the second groove area 202, the surface of the second groove area 202 of the dielectric layer 200 has a first side and a second side opposite to each other, and a seventh side and an eighth side opposite to each other, two ends of the seventh side are respectively connected with the first side and the second side, and two ends of the eighth side are respectively connected with the first side and the second side. The first side is parallel to the second side, the seventh side is parallel to the eighth side, the length of the first side is equal to the length of the second side, the length of the seventh side is equal to the length of the eighth side, and the length of the first side is greater than the length of the seventh side.
The surface of the first groove area 201 of the dielectric layer 200 is in a strip shape, specifically, the first groove area 201 has a ninth side and a tenth side opposite to each other in the width direction of the first groove area 201, the surface of the second groove area 202 of the dielectric layer 200 has a ninth side and a tenth side opposite to each other, two ends of the tenth side are respectively connected with the ninth side and the tenth side, and two ends of the twelfth side are respectively connected with the ninth side and the tenth side. The ninth side is parallel to the tenth side, the eleventh side is parallel to the twelfth side, the ninth side has a length equal to the tenth side, the tenth side has a length equal to the twelfth side, and the ninth side has a length greater than the tenth side.
The width direction of the first groove region 201 of the dielectric layer 200 is parallel to the seventh side and the eighth side. The width direction of the second groove region 202 of the dielectric layer 200 is parallel to the tenth side and the twelfth side.
The number of the first groove regions 201 located between the adjacent second groove regions 202 is one or more. In this embodiment, the number of the first groove regions 201 between the adjacent second groove regions 202 is 3 as an example.
Referring to fig. 5, a number of discrete contact hole regions 203 are obtained in the second trench region 202.
For convenience of description, the contact hole regions 203 are divided into contact hole region types, the contact hole region types of each contact hole region type are arranged along the length direction of the second groove region, the projections of the contact hole region types of different contact hole regions on the edge of the second groove region along the width direction of the second groove region are mutually separated, and the projections of the contact hole region types of different contact hole regions on the edge of the second groove region along the length direction of the second groove region are mutually separated. This reduces the risk of short circuits between subsequent second plugs located over different types of contact hole regions.
In this embodiment, the contact hole regions 203 are divided into a first contact hole region and a second contact hole region, the first contact hole region is arranged along the length direction of the second trench region 202, the second contact hole region is arranged along the length direction of the second trench region 202, projections of the first contact hole region and the second contact hole region on the edge of the second trench region 202 along the width direction of the second trench region 202 are separated from each other, and projections of the first contact hole region and the second contact hole region on the edge of the second trench region 202 along the length direction of the second trench region 202 are separated from each other.
The contact hole region 203 is a region where a subsequent second plug is projected to the second trench region 202.
Referring to fig. 6, a second groove modification region 210 located in the second groove region 202 is obtained according to the position of the contact hole region 203, the second groove modification region 210 covering the contact hole region 203, the width of the second groove modification region 210 being smaller than the width of the second groove region 202.
The second groove correction region 210 includes a connection region and a plurality of discrete hole correction regions, the extending direction of the hole correction regions is parallel to the length direction of the second groove region 202, the projections of the plurality of hole correction regions on the edge of the second groove region 202 along the width direction of the second groove region 202 are discrete from each other, and the projections of the plurality of hole correction regions on the edge of the second groove region along the length direction of the second groove region 202 are discrete from each other; both ends of the connection region are connected to hole correction regions, which are located on both sides of the connection region in the length direction of the second groove region 202, respectively.
Both ends of the connecting region are connected to the adjacent hole correction regions, respectively.
Each hole modification region comprises a contact hole region of a type. And for the contact hole region covered by the hole correction region and the same hole correction region, along the length direction of the second groove region 202, the projection of the hole correction region on the edge of the second groove region 202 is coincident with the projection of the contact hole region on the edge of the second groove region 202.
In the present embodiment, the number of the hole correction regions is two as an example. The two hole correction regions are a first hole correction region 211 and a second hole correction region 212, respectively. The extending direction of the first hole correction region 211 and the second hole correction region 212 is parallel to the length direction of the second groove region 202, two ends of the connection region 213 are respectively connected with the first hole correction region 211 and the second hole correction region 212, and the first hole correction region 211 and the second hole correction region 212 are respectively located at two sides of the connection region 213 in the length direction of the second groove region 202.
The width of the second groove modification region 210 is equal to the width of the first groove region 201; alternatively, the width of the second groove correction region 210 is smaller than the width of the first groove region 201; alternatively, the width of the second groove correction region 210 is greater than the width of the first groove region 201 and less than the width of the second groove region 202.
In this embodiment, the width of the second groove modification region 210 is 95% to 105% of the width of the first groove region 201.
In this embodiment, the first hole modification region 211 and the second hole modification region 212 are respectively located at two side edges of the second groove region 202 in the width direction of the second groove region 202.
In this embodiment, the first hole modified region 211 has a third edge and a fourth edge opposite to each other in the width direction of the first hole modified region 211, the third edge is overlapped with a part of the first edge, and the fourth edge is located between the third edge and the second edge; the second hole correction region 212 has a fifth side and a sixth side opposite to each other in the width direction of the second hole correction region 212, the sixth side and a part of the second side are overlapped, and the fifth side is located between the sixth side and the first side.
In other embodiments, the third and fourth edges are between the first and second edges, the fourth edge is between the first and second edges, the fifth edge is between the first and second edges, and the sixth edge is between the first and second edges.
The two ends of the connection region 213 are a first end and a second end, the first end is connected to the first hole modification region 211, the second end is connected to the second hole modification region 212, and the direction from the first end to the second end is parallel to the width direction of the second groove region 202.
Referring to fig. 7, a sacrificial layer 220 is formed on the dielectric layer 200 on the second groove modification region 210 and the first groove region 201, respectively.
The material of the sacrificial layer 220 is amorphous silicon or amorphous carbon.
The method of forming the sacrificial layer 220 includes: forming a sacrificial film (not shown) on the surface of the dielectric layer 200; forming a photoresist film on the sacrificial film; carrying out an exposure process on the photoresist film by adopting a mask plate, and forming an exposure area and a non-exposure area in the photoresist film; developing the photoresist film to remove the non-exposure area of the photoresist film and form a photoresist layer in the exposure area of the photoresist film; etching the sacrificial film by using the photoresist layer as a mask until the surface of the dielectric layer 200 is exposed to form the sacrificial layer 220; the photoresist layer is then removed.
The pattern of the mask is obtained according to the shapes of the second groove correction region 210 and the first groove region 201. Specifically, the manufacturing method of the mask comprises the following steps: acquiring photoetching mask layer patterns corresponding to the patterns of the second groove correction area 210 and the first groove area 201; performing OPC correction on the photoetching mask layer pattern to obtain a corrected pattern, wherein the corrected pattern comprises a first corrected pattern corresponding to the shape of the first groove area 201 and a second corrected pattern corresponding to the shape of the second groove corrected area 210; and manufacturing a mask according to the corrected graph.
Since the width of the second groove correction area 210 is smaller than the width of the second groove area 202, in the corrected pattern obtained after OPC correction, it is avoided that the width of the first corrected pattern located at the center of the adjacent second corrected pattern is too small, and the width of the first corrected pattern exceeds the lower limit size of the test pattern used when the OPC correction model is established, so that the lithography resolution of the first corrected pattern located at the center of the adjacent second corrected pattern is improved. In this way, when the exposure condition is slightly changed, the mask is used for exposure, and when the exposure condition is slightly changed, more weak points do not exist in the first exposure pattern obtained by the first correction pattern, so that the size of the first conductive layer formed in the first groove region 201 in the following process can meet the requirement of process design.
With reference to fig. 7, a first sidewall 231 and a second sidewall 232 are formed on the dielectric layer 200, wherein the first sidewall 231 is located on the sidewalls of the first trench area 201 on the two sides of the sacrificial layer 220 along the width direction of the first trench area 201, and the second sidewall 232 is located on the sidewalls of the second trench area 210 on the two sides of the sacrificial layer 220 along the width direction of the second trench area 210.
The material of the first sidewall 231 and the second sidewall 232 includes silicon nitride.
The method for forming the first side wall 231 and the second side wall 232 includes: forming a side wall film on the side wall and the top of the sacrificial layer 220 and the surface of the dielectric layer 200 exposed by the sacrificial layer 220; and etching the side wall film back until the surface of the dielectric layer 200 is exposed to form the first side wall 231 and the second side wall 232.
Referring to fig. 8, a barrier layer 233 is formed on the second trench region 202 exposed by the second sidewall spacers 232, and a distance from an edge of the barrier layer 233 to an edge of the sacrificial layer 220 on the adjacent first trench region 201 is equal to a minimum distance between the first sidewall 231 and the second sidewall spacers 232.
The minimum distance between the first side wall 231 and the second side wall 232 means: the minimum distance from the edge of the first sidewall 231 to the edge of the second sidewall 232.
The material of the barrier layer 233 includes a photoresist material. The method of forming the barrier layer 233 includes: forming a barrier film (not shown) on the dielectric layer 200 exposed by the sacrificial layer 220, the first sidewall 231 and the second sidewall 232, and on the sacrificial layer 220, the first sidewall 231 and the second sidewall 232; the barrier film is exposed and developed, so that the barrier film forms the barrier layer 233.
Referring to fig. 9, after forming the barrier layer 233, the sacrificial layer 220 is removed.
The process of removing the sacrificial layer 220 is a wet etching process or a dry etching process.
With reference to fig. 9, after removing the sacrificial layer 220, the dielectric layer 200 is etched by using the barrier layer 233, the first sidewall 231, and the second sidewall 232 as masks, a first groove 250 is formed in the dielectric layer 200 at two sides of the first sidewall 231, and a second groove 240 is formed in the second groove modification region 210 of the dielectric layer 200.
The process of etching the dielectric layer 200 using the barrier layer 233, the first sidewall 231, and the second sidewall 232 as masks includes an anisotropic dry etching process.
The first grooves 250 are located between adjacent second grooves 240.
Referring to fig. 10, after forming the first and second recesses 250 and 240, the barrier layer 233, the first and second sidewalls 231 and 232 are removed.
Referring to fig. 11, after removing the barrier layer 233, the first sidewall 231, and the second sidewall 232, a first conductive layer 260 is formed in the first groove 250, and a second conductive layer 270 is formed in the second groove 240; forming a first plug on the first conductive layer 260, the first plug being electrically connected to the first conductive layer 260; a plurality of second plugs are formed on the second conductive layer 270, and the second plugs are respectively located on the contact hole regions, and the second plugs are electrically connected with the second conductive layer 270.
The material of the first conductive layer 260 and the second conductive layer 270 is metal.
The material of the first plug and the second plug is metal.
The number of the first plugs is one or a plurality of plugs.
And the second plug positioned on the contact hole areas of different types is used for connecting different top layer conductive materials.
Accordingly, the present embodiment also provides a semiconductor device formed by the above method, and referring to fig. 10, the method includes: a dielectric layer 200 (refer to fig. 4), where the dielectric layer 200 includes a first groove area 201 and a plurality of second groove areas 202, the first groove area 201 and the second groove areas 202 are separated from each other, the first groove area 201 is located between adjacent second groove areas 202, and the width of each second groove area 202 is greater than the width of the first groove area 201; a number of discrete contact hole regions 203 (see fig. 5) located in the second trench region 202; a second trench modification region 210 (see fig. 6) located in the second trench region 202, the second trench modification region 210 covering the contact hole region, the second trench modification region 210 having a width less than a width of the second trench region 202; the first grooves 250 are respectively positioned in the first groove area 201 of the dielectric layer 200 and in the dielectric layer 200 at two sides of the first groove area 201; a second recess 240 in the second trench modification region 210 of the dielectric layer 200.
The width of the second groove modification region 210 is equal to the width of the first groove region 201; alternatively, the width of the second groove modification region 210 is smaller or larger than the width of the first groove region 201.
The width of the second groove modification region 210 is 95% to 105% of the width of the first groove region 201.
The second groove correction region 210 includes a connection region and a plurality of discrete hole correction regions, the extending direction of the hole correction regions is parallel to the length direction of the second groove region 202, the projections of the plurality of hole correction regions on the edge of the second groove region 202 along the width direction of the second groove region 202 are discrete from each other, and the projections of the plurality of hole correction regions on the edge of the second groove region 202 along the length direction of the second groove region 202 are discrete from each other; both ends of the connection region are connected to hole correction regions, which are located on both sides of the connection region in the length direction of the second groove region 202, respectively.
The number of the hole correction areas is two; the two hole correction areas are respectively a first hole correction area and a second hole correction area; the extending direction of the first hole correction region and the second hole correction region is parallel to the length direction of the second groove region 202; both ends of the connection region are connected with the first hole correction region and the second hole correction region, respectively, and the first hole correction region and the second hole correction region are located on both sides of the connection region in the length direction of the second groove region 202, respectively.
The two ends of the connection region 213 are a first end and a second end, the first end is connected to the first hole modification region, the second end is connected to the second hole modification region, and the direction from the first end to the second end is parallel to the width direction of the second groove region 202.
The number of the first groove regions 201 between the adjacent second groove regions 202 is one or several.
The semiconductor device further includes: a first conductive layer 260 positioned in the first groove 250; a second conductive layer 270 in the second groove 240; a first plug on the first conductive layer 260, the first plug being electrically connected to the first conductive layer 260; and a plurality of second plugs located on the second conductive layer 270, and the second plugs are respectively located on the contact hole regions, and the second plugs are electrically connected with the second conductive layer 270.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

1. A method of forming a semiconductor device, comprising:
providing a medium layer, wherein the medium layer comprises a first groove area and a plurality of second groove areas, the first groove areas and the second groove areas are mutually separated, the first groove areas are positioned between the adjacent second groove areas, and the width of each second groove area is greater than that of each first groove area;
obtaining a plurality of discrete contact hole regions in the second trench region;
acquiring a second groove correction area positioned in the second groove area according to the position of the contact hole area, wherein the second groove correction area covers the contact hole area, and the width of the second groove correction area is smaller than that of the second groove area;
respectively forming sacrificial layers on the dielectric layer second groove correction area and the first groove area;
forming a first side wall and a second side wall on the dielectric layer, wherein the first side wall is positioned on the side walls of the sacrificial layer on the first groove area along the two sides of the width direction of the first groove area, and the second side wall is positioned on the side walls of the sacrificial layer on the second groove correction area along the two sides of the width direction of the second groove correction area;
forming a barrier layer on the second groove region exposed by the second side wall, wherein the distance from the edge of the barrier layer to the edge of the sacrificial layer on the adjacent first groove region is equal to the minimum distance between the first side wall and the second side wall;
after the barrier layer is formed, removing the sacrificial layer;
after the sacrificial layer is removed, etching the dielectric layer by taking the barrier layer, the first side wall and the second side wall as masks, forming a first groove in the dielectric layer on two sides of the first side wall, and forming a second groove in the second groove correction area of the dielectric layer;
the width of the second groove correction area is equal to the width of the first groove area; alternatively, the width of the second groove modification region is smaller or larger than the width of the first groove region.
2. The method of claim 1, wherein the width of the second trench modification region is 95% to 105% of the width of the first trench region.
3. The method for forming a semiconductor device according to claim 1, wherein the second trench modification region includes a connection region and a plurality of discrete hole modification regions, an extending direction of the hole modification region is parallel to a length direction of the second trench region, projections of the plurality of hole modification regions on an edge of the second trench region along a width direction of the second trench region are discrete from each other, and projections of the plurality of hole modification regions on an edge of the second trench region along a length direction of the second trench region are discrete from each other; and two ends of the connecting area are respectively connected with the hole correcting area, and the hole correcting areas are respectively positioned at two sides of the connecting area in the length direction of the second groove area.
4. The method according to claim 3, wherein the number of the hole modification regions is two; the two hole correction areas are respectively a first hole correction area and a second hole correction area; the extending direction of the first hole correcting area and the second hole correcting area is parallel to the length direction of the second groove area; the two ends of the connecting area are respectively connected with the first hole correcting area and the second hole correcting area, and the first hole correcting area and the second hole correcting area are respectively located on the two sides of the connecting area in the length direction of the second groove area.
5. The method for forming a semiconductor device according to claim 4, wherein the first hole correction region and the second hole correction region are located at both side edges in the second trench region in a width direction of the second trench region, respectively.
6. The method for forming a semiconductor device according to claim 4, wherein the two ends of the connection region are a first end and a second end, the first end is connected to the first hole modification region, the second end is connected to the second hole modification region, and a direction from the first end to the second end is parallel to a width direction of the second groove region.
7. The method according to claim 1, wherein a material of the sacrificial layer is amorphous silicon or amorphous carbon; the first side wall and the second side wall are made of silicon nitride; the dielectric layer is made of silicon oxide or a low-K dielectric material.
8. The method according to claim 1, wherein the method for forming the sacrificial layer comprises: forming a sacrificial film on the surface of the dielectric layer; forming a photoresist film on the sacrificial film; carrying out an exposure process on the photoresist film by adopting a mask plate, and forming an exposure area and a non-exposure area in the photoresist film; developing the photoresist film to remove the non-exposure area of the photoresist film and form a photoresist layer in the exposure area of the photoresist film; etching the sacrificial film by taking the photoresist layer as a mask until the surface of the dielectric layer is exposed to form the sacrificial layer; and removing the photoresist layer after etching the sacrificial film.
9. The method for forming a semiconductor device according to claim 8, wherein the method for manufacturing the mask comprises: acquiring photoetching mask layer patterns corresponding to the patterns of the second groove correction area and the first groove area; carrying out OPC correction on the photoetching mask layer pattern to obtain a corrected pattern; and manufacturing a mask according to the corrected graph.
10. The method for forming the semiconductor device according to claim 1, wherein the method for forming the first and second side walls comprises: forming side wall films on the side wall and the top of the sacrificial layer and the surface of the dielectric layer exposed by the sacrificial layer; and etching the side wall film back until the surface of the dielectric layer is exposed to form the first side wall and the second side wall.
11. The method according to claim 1, wherein a material of the barrier layer comprises a photoresist material;
the method for forming the barrier layer comprises the following steps: forming barrier films on the exposed dielectric layers of the sacrificial layer, the first side wall and the second side wall and on the sacrificial layer, the first side wall and the second side wall; and exposing and developing the barrier film to form the barrier film into the barrier layer.
12. The method for forming a semiconductor device according to claim 1, further comprising: after the first groove and the second groove are formed, removing the barrier layer, the first side wall and the second side wall; after the barrier layer, the first side wall and the second side wall are removed, a first conductive layer is formed in the first groove, and a second conductive layer is formed in the second groove; forming a first plug on the first conductive layer, the first plug and the first conductive layer being electrically connected; forming a plurality of second plugs on the second conductive layer, wherein the second plugs are respectively positioned on the contact hole regions; the second plug is electrically connected to the second conductive layer.
13. A semiconductor device, comprising:
the dielectric layer comprises a first groove area and a plurality of second groove areas, the first groove areas and the second groove areas are mutually separated, the first groove areas are positioned between the adjacent second groove areas, and the width of each second groove area is greater than that of each first groove area;
a plurality of discrete contact hole regions located in the second trench region;
a second trench trim region in the second trench region, the second trench trim region including a contact hole region, the second trench trim region having a width less than a width of the second trench region;
the first grooves are respectively positioned in the first groove area of the dielectric layer and in partial dielectric layers on two sides of the first groove area;
a second groove in the dielectric layer second groove correction area;
the width of the second groove correction area is equal to the width of the first groove area; alternatively, the width of the second groove modification region is smaller or larger than the width of the first groove region.
14. The semiconductor device according to claim 13, wherein a width of the second groove modification region is 95% to 105% of a width of the first groove region.
15. The semiconductor device according to claim 13, wherein the second groove correction region comprises a connection region and a plurality of discrete hole correction regions, an extending direction of the hole correction regions is parallel to a length direction of the second groove region, projections of the plurality of hole correction regions on edges of the second groove region along a width direction of the second groove region are discrete from each other, and projections of the plurality of hole correction regions on edges of the second groove region along a length direction of the second groove region are discrete from each other; and two ends of the connecting area are respectively connected with the hole correcting area, and the hole correcting areas are respectively positioned at two sides of the connecting area in the length direction of the second groove area.
16. The semiconductor device according to claim 15, wherein the number of the hole modification regions is two; the two hole correction areas are respectively a first hole correction area and a second hole correction area; the extending direction of the first hole correcting area and the second hole correcting area is parallel to the length direction of the second groove area; the two ends of the connecting area are respectively connected with the first hole correcting area and the second hole correcting area, and the first hole correcting area and the second hole correcting area are respectively located on the two sides of the connecting area in the length direction of the second groove area.
17. The semiconductor device according to claim 16, wherein the two ends of the connection region are a first end and a second end, the first end is connected to the first hole modification region, the second end is connected to the second hole modification region, and a direction from the first end to the second end is parallel to a width direction of the second groove region.
18. The semiconductor device according to claim 13, further comprising: the first conducting layer is positioned in the first groove; the second conducting layer is positioned in the second groove; a first plug on the first conductive layer, the first plug and the first conductive layer being electrically connected; and the second plugs are respectively positioned on the contact hole regions, and the second plugs are electrically connected with the second conductive layer.
CN201810117810.3A 2018-02-06 2018-02-06 Semiconductor device and method of forming the same Active CN110120366B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090069458A (en) * 2007-12-26 2009-07-01 주식회사 동부하이텍 Method for opc modeling of semiconductor device
CN103777457A (en) * 2012-10-18 2014-05-07 中芯国际集成电路制造(上海)有限公司 Optical proximity correction method for contact hole graphic design
CN105719999A (en) * 2014-12-02 2016-06-29 中芯国际集成电路制造(上海)有限公司 Interconnection structure and forming method thereof
CN106338883A (en) * 2015-07-16 2017-01-18 中芯国际集成电路制造(上海)有限公司 Optical proximity correction method
CN106981484A (en) * 2017-03-28 2017-07-25 上海理工大学 The layout design method of standard cell lib area is reduced using local interlinkage

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420077B1 (en) * 2001-01-23 2002-07-16 United Microelectronic Corp. Contact hole model-based optical proximity correction method
JP4398824B2 (en) * 2004-09-08 2010-01-13 株式会社東芝 Pattern data correction method, photomask manufacturing method, semiconductor device manufacturing method, and program

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090069458A (en) * 2007-12-26 2009-07-01 주식회사 동부하이텍 Method for opc modeling of semiconductor device
CN103777457A (en) * 2012-10-18 2014-05-07 中芯国际集成电路制造(上海)有限公司 Optical proximity correction method for contact hole graphic design
CN105719999A (en) * 2014-12-02 2016-06-29 中芯国际集成电路制造(上海)有限公司 Interconnection structure and forming method thereof
CN106338883A (en) * 2015-07-16 2017-01-18 中芯国际集成电路制造(上海)有限公司 Optical proximity correction method
CN106981484A (en) * 2017-03-28 2017-07-25 上海理工大学 The layout design method of standard cell lib area is reduced using local interlinkage

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