CN110112210B - Side wall gate structure of radio frequency LDMOS (laterally diffused metal oxide semiconductor) and preparation method thereof - Google Patents
Side wall gate structure of radio frequency LDMOS (laterally diffused metal oxide semiconductor) and preparation method thereof Download PDFInfo
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- CN110112210B CN110112210B CN201910217614.8A CN201910217614A CN110112210B CN 110112210 B CN110112210 B CN 110112210B CN 201910217614 A CN201910217614 A CN 201910217614A CN 110112210 B CN110112210 B CN 110112210B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 229910044991 metal oxide Inorganic materials 0.000 title description 3
- 150000004706 metal oxides Chemical class 0.000 title description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000003647 oxidation Effects 0.000 claims abstract description 15
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 10
- 238000001259 photo etching Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- 229910052681 coesite Inorganic materials 0.000 claims 1
- 229910052906 cristobalite Inorganic materials 0.000 claims 1
- 239000000377 silicon dioxide Substances 0.000 claims 1
- 235000012239 silicon dioxide Nutrition 0.000 claims 1
- 229910052682 stishovite Inorganic materials 0.000 claims 1
- 229910052905 tridymite Inorganic materials 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 230000005684 electric field Effects 0.000 abstract description 6
- 150000002500 ions Chemical class 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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Abstract
The invention relates to a side wall gate structure of a radio frequency LDMOS and a preparation method thereof, comprising a semiconductor substrate and a thermal oxidation SiO 2 Polysilicon, deposited SiO 2 And metal, etching the surface of the semiconductor substrate to form a step, forming a side wall grid at the corner of the step, and manufacturing a metal field plate on the surface of the step by selective etching so that the grid is not overlapped with the field plate. The invention has the beneficial effects that: 1) The side wall grid is not overlapped with the field plate, so that the parasitic capacitance is reduced, and the frequency characteristic of the LDMOS is improved. 2) The side surface of the grid is used as a part of field plate, the electric field intensity of the boundary of the channel and the drift region is reduced, and effective support is provided for reducing the length of the channel. 3) When the ions are injected into the drift region, the influence of the side scattering of the ions on the channel region is weakened, and the control difficulty of process production is reduced. 4) The side wall gate structure pulls open the space distance between the channel region and the drift region in the longitudinal direction, and under the condition that the electric field at the boundary of the channel region and the drift region is reduced, the concentration of the drift region close to the side wall of the gate can be increased, and the on-resistance is effectively reduced.
Description
Technical Field
The invention discloses a side wall gate structure of a radio frequency LDMOS (laterally diffused metal oxide semiconductor) and a preparation method thereof, belonging to the technical field of semiconductor microelectronic design and manufacture.
Background
With the development of mobile communication, the radio frequency LDMOS device is more and more widely applied to communication base stations, broadcast televisions and modern radar systems. Under the condition of not considering parasitic parameters, the frequency performance of the LDMOS is in inverse proportion to the characteristic size Lg of the gate (402T ℃. + Vs/Lg), in order to continuously improve the frequency performance of the LDMOS, a manufacturer usually reduces the characteristic gate length Lg of the LDMOS gate to continuously improve the frequency performance of a device, wherein in the last ten years, the characteristic size of the gate of the radio frequency LDMOS is reduced from about 1 mu m to about 0.25 mu m at present, and the working frequency is also improved from about 1GHz to about 4GHz at present. The overlap parasitic capacitance between the gate and the field plate usually accounts for more than 20% of the total input capacitance, so in order to improve the LDMOS frequency performance, the parasitic capacitance between the gate and the field plate needs to be reduced in addition to the gate characteristic dimension Lg.
The semiconductor under the control of the gate comprises three parts, namely a partial source region (n +), a channel region (P) and a partial drift region (n-), two interfaces exist, and the interfaces are formed by lateral diffusion, wherein the n +/P and the P/n-are formed by lateral diffusion. When the size of the gate is further reduced, the following technical difficulties are faced, firstly, the process control difficulty is very high due to the concentration requirement of each region under the gate, and secondly, after the P/n-interface under the gate is closer to the edge of the gate at the drain end, the electric field concentration at the position influences the reliability, and the short channel effect is easy to occur.
The gate and the field plate are overlapped inevitably due to the planar process, and the parasitic capacitance is mainly determined by the geometrical parameters of a medium (SiO 2) between the side face of the polysilicon gate and the field plate. The distance between the two in the lateral direction cannot be increased in consideration of controlling the electric field in the drift region, and the height of the gate in the longitudinal direction cannot be further reduced under the limitation of other implantation conditions. The parasitic capacitance between the gate and the field plate of the conventional LDMOS is difficult to reduce.
Disclosure of Invention
The invention provides a side wall gate structure of a radio frequency LDMOS and a preparation method thereof, and aims to further reduce the parasitic capacitance between an LDMOS gate and a field plate and improve the frequency performance of the LDMOS.
The technical scheme of the invention is as follows: a side wall gate structure of radio frequency LDMOS comprises a semiconductor substrate and a thermal oxidation SiO 2 Polysilicon, deposited SiO 2 And metal, wherein the surface of the semiconductor substrate is etched to form a step, and the surface of the step is provided with thermal oxide SiO 2 Thermal oxidation of SiO 2 The surface is deposited with polysilicon which forms a side wall gate at the corner of the step, and the upper surface of the step is provided with deposited SiO 2 And metal, the metal field plate formed by selective etching, the field plate and the sidewall gate have no overlap.
The surface of the semiconductor substrate forms a channel region through ion implantation and transverse diffusion, and a drift region is formed through self doping of raw materials or through ion implantation and longitudinal diffusion.
The semiconductor substrate material is one of silicon, germanium, silicon carbide, carbon, gallium arsenide and gallium nitride.
The side wall gate side is isolated from the step side by a medium, and the medium can be formed independently or formed together with the gate oxide layer.
And the polysilicon gate at the corner of the step is formed by a self-alignment process or photoetching.
The metal material is one of doped polysilicon, tungsten and tungsten silicon.
The preparation method comprises the following steps:
1) Forming a step with a height difference of 3000-6000 angstroms on a semiconductor substrate through photoetching;
2) Growing 150-300 angstrom gate oxide by thermal oxidation, and depositing 3000-4000 angstrom polysilicon;
3) By means of polysilicon back etching, the process is terminated at SiO 2 Forming a side wall grid;
4) Doping a channel region, a drift region and a source drain region by adopting an ion implantation mode;
5) Depositing 600-1500 angstroms of SiO 2 And photoetching the medium and 1000-2000 angstroms of metal to form a metal field plate on the surface of the step.
The invention has the beneficial effects that:
(1) The side wall grid is not overlapped with the field plate, so that the parasitic capacitance is reduced, and the frequency characteristic of the LDMOS is improved.
(2) The side surface of the grid serves as a part of field plate, the electric field intensity of the boundary of the channel and the drift region is reduced, effective support is provided for reducing the length of the channel, and the limit frequency of the LDMOS can be further improved.
(3) When the ions are injected into the drift region, the influence of the side scattering of the ions on the channel region is weakened, and the control difficulty of process production is reduced.
(4) The side wall gate structure pulls open the space distance between the channel region and the drift region in the longitudinal direction, and under the condition that the electric field at the boundary of the channel region and the drift region is reduced, the concentration of the drift region close to the side wall of the gate can be increased, and the on-resistance is effectively reduced.
Drawings
FIG. 1 is a schematic structural view of a step formed on a silicon substrate by photolithography etching;
FIG. 2 is a schematic diagram of a gate oxide and deposited polysilicon structure;
FIG. 3 is a schematic structural diagram of a sidewall gate formed at a step corner by using polysilicon etch-back;
FIG. 4 is a schematic structural diagram of doping of a channel region, a drift region and a source-drain region;
FIG. 5 is a schematic structural diagram of a field plate formed on the surface of a step by selective etching;
in the figure, 1 is a silicon substrate, 2 is thermal oxidation SiO 2 3 is polysilicon, 4 is deposited SiO 2 And 5 is a metal.
Detailed Description
The technical scheme of the invention is further explained by combining the attached drawings
As shown in fig. 1, a step is formed on a substrate by a photolithography etching method;
as shown in fig. 2, growing gate oxide by thermal oxidation, and depositing polysilicon;
as shown in fig. 3, the polysilicon etch back is adopted, ending at SiO 2 Forming a side wall grid;
as shown in fig. 4, doping of the channel region, the drift region and the source and drain regions is performed by ion implantation;
as shown in FIG. 5, siO is deposited 2 And photoetching and etching the medium and the tungsten to form a metal field plate on the surface of the step.
Example 1
1) Forming a step with the height difference of 5000 angstroms on a P-silicon substrate by a photoetching method;
2) Growing 200 angstroms of gate oxide by thermal oxidation, and depositing 4000 angstroms of polycrystalline silicon;
3) By means of polysilicon back etching, the process is terminated at SiO 2 Forming a side wall grid;
4) Doping a channel region, a drift region and a source drain region by adopting an ion implantation mode;
5) Deposition of 1000 angstroms of SiO 2 And photoetching and etching the medium and 1000 angstrom tungsten to form a metal field plate on the surface of the step.
Example 2
1) Forming a step with 4500 angstrom height difference on the gallium arsenide substrate through photoetching;
2) Growing 250 angstrom gate oxide by thermal oxidation, and depositing 3500 angstrom polysilicon;
3) By means of polysilicon back etching, ending in SiO 2 Forming a side wall grid;
4) Doping a channel region, a drift region and a source drain region by adopting an ion implantation mode;
5) Deposition of 700 angstroms of SiO 2 Medium and 1500 angstrom metal, photoetching and etching to form a metal field plate on the step surface.
Claims (2)
1. A side wall gate structure of radio frequency LDMOS is characterized by comprising a semiconductor substrate and thermal oxidation SiO 2 Polysilicon, deposited SiO 2 And metal, wherein the surface of the semiconductor substrate is etched to form a step, and the surface of the step is provided with thermal oxide SiO 2 Thermal oxidation of SiO 2 The surface is deposited with polysilicon which forms a side wall gate at the corner of the step, and the upper surface of the step is provided with deposited SiO 2 The metal field plate is formed by selective etching, and the field plate is not overlapped with the side wall gate;
wherein: a source region and a channel region are arranged below the step, the side wall of the step is a drift region, and the side wall gate and the drift region are formed by thermal oxidation of SiO 2 Isolating; depositing SiO on the metal field plate and the side wall grid 2 Isolating, wherein the channel region and the drift region are intersected at the corner of the step;
forming a channel region on the surface of the semiconductor substrate through ion implantation and transverse diffusion, and forming a drift region through ion implantation and longitudinal diffusion;
the polysilicon gate at the corner of the step is formed by a self-alignment process or photoetching;
the semiconductor substrate material is one of silicon, germanium, silicon carbide, carbon, gallium arsenide and gallium nitride;
the metal material is one of tungsten and tungsten silicon.
2. The method for preparing the side-wall gate structure of the radio frequency LDMOS as claimed in claim 1, comprising the following steps:
1) Forming a step with a height difference of 3000-6000 angstroms on a semiconductor substrate through photoetching;
2) Growing 150-300 angstroms of thermal oxidation SiO2 by thermal oxidation, and depositing 3000-4000 angstroms of polysilicon;
3) By means of polysilicon back etching, ending in thermal oxidation of SiO 2 Forming a side wall grid;
4) Doping a channel region, a drift region and a source drain region by adopting an ion implantation mode;
5) Depositing 600-1500 angstrom thermal oxidation SiO 2 And photoetching the medium and 1000-2000 angstroms of metal to form a metal field plate on the surface of the step.
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| CN105097804A (en) * | 2014-05-23 | 2015-11-25 | 德克萨斯仪器股份有限公司 | Method for creation of the gate shield in analog/rf power ed-cmos in sige bicmos technologies |
| CN105374879A (en) * | 2015-11-16 | 2016-03-02 | 上海华虹宏力半导体制造有限公司 | Radio frequency laterally diffused metal oxide semiconductor (LDMOS) device |
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| US7087959B2 (en) * | 2004-08-18 | 2006-08-08 | Agere Systems Inc. | Metal-oxide-semiconductor device having an enhanced shielding structure |
| DE102006001922B3 (en) * | 2006-01-14 | 2007-05-03 | Infineon Technologies Austria Ag | Lateral power transistor used as a MOSFET or an insulated gate bipolar transistor comprises a source zone, a drain zone, a drift zone and a body zone arranged in a semiconductor layer and an electrode layer |
| US20130020632A1 (en) * | 2011-07-18 | 2013-01-24 | Disney Donald R | Lateral transistor with capacitively depleted drift region |
| CN102881722A (en) * | 2012-10-26 | 2013-01-16 | 西安电子科技大学 | Source-field-plate heterojunction field-effect transistor and manufacturing method thereof |
| US9698260B1 (en) * | 2015-12-31 | 2017-07-04 | Globalfoundries Singapore Pte. Ltd. | High voltage device with low Rdson |
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| CN105097804A (en) * | 2014-05-23 | 2015-11-25 | 德克萨斯仪器股份有限公司 | Method for creation of the gate shield in analog/rf power ed-cmos in sige bicmos technologies |
| CN105374879A (en) * | 2015-11-16 | 2016-03-02 | 上海华虹宏力半导体制造有限公司 | Radio frequency laterally diffused metal oxide semiconductor (LDMOS) device |
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| Title |
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| 2000W硅LDMOS微波脉冲大功率晶体管;应贤炜;《固体电子学研究与进展》;20171231;第37卷(第6期);第1-5页 * |
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