CN110112056A - A kind of preparation method of integrated morphology and thus obtained copper interconnecting line and dielectric material integrated morphology - Google Patents
A kind of preparation method of integrated morphology and thus obtained copper interconnecting line and dielectric material integrated morphology Download PDFInfo
- Publication number
- CN110112056A CN110112056A CN201910340421.1A CN201910340421A CN110112056A CN 110112056 A CN110112056 A CN 110112056A CN 201910340421 A CN201910340421 A CN 201910340421A CN 110112056 A CN110112056 A CN 110112056A
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- Prior art keywords
- metal
- copper
- preparation
- polymer
- dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
Abstract
The present invention provides a kind of preparation method of integrated morphology, comprising: S1 deposits one layer of high molecular polymer on a semiconductor substrate, forms one layer of photolithography plate on the surface of high molecular polymer；S2 forms polymer groove by plasma etching high molecular polymer, removes photolithography plate；S3 covers one layer of metal barrier in the wall surface of polymer groove；S4 fills deposited copper metal in polymer groove to form copper interconnecting line structure；High molecular polymer between copper metal is all removed by plasma etching, forms metal valley between copper metal by S5；S6 fills deposits dielectric materials in metal valley；S7, deposition of insulative material forms coating on dielectric material and copper interconnecting line structure.The present invention also provides the copper interconnecting lines obtained according to above-mentioned preparation method and dielectric material integrated morphology.The present invention avoids directly performing etching dielectric material caused flute surfaces defect by filling copper metal in polymer groove.
Description
Technical field
The present invention relates to integrated circuit structure, relates more specifically to a kind of preparation method of integrated morphology and thus obtain
Copper interconnecting line and dielectric material integrated morphology.
Background technique
In super large-scale integration manufacture, in order to solve resistance in circuit caused by device feature size constantly reduces
Capacitance delays effect, Damascus and dual damascene process use copper as interconnection line conducting wire, and low/ultralow dielectric is situated between
Electric matter is as intermetallic dielectric layer.This copper interconnecting line processing procedure is applied to 90nm and its smaller size of technique manufactures.Due to it is low/
Ultralow dielectric dielectric material is in traditional sucrose material (SiO2) in doping C etc. elements form porous structure, mechanics, machine
Tool performance will be substantially reduced.This makes in the technical process that plasma etching forms dielectric layer groove, the surface of trench wall
It is more coarse, and then cause copper interconnecting line edge roughness very high (Line Edge Roughness)；And the change in copper metal
During learning mechanical polishing process, since low/ultralow dielectric dielectric layer supportive is weaker, the vertex of copper conductor is easier
It is worn.Therefore copper-it is low/interface of ultralow dielectric dielectric layer belongs to weakness zone.When manufacturing process is developed to 22nm skill
Art and it is following when, the structural weakening phenomenon due to caused by the intermetallic dielectric layer performance of ultralow dielectric can be increasingly severe,
And continue the problem solved in technique.
Summary of the invention
In order to solve the problems, such as above-mentioned TDDB of the existing technology, the present invention is intended to provide a kind of preparation side of integrated morphology
Method and thus obtained copper interconnecting line and dielectric material integrated morphology.
The present invention provides a kind of preparation method of integrated morphology, comprising the following steps: S1, on a semiconductor substrate, deposition
One layer of high molecular polymer forms one layer of photolithography plate on the surface of high molecular polymer；S2 passes through plasma etching polyphosphazene polymer
It closes object and forms polymer groove, and remove photolithography plate；S3 covers one layer of metal barrier in the wall surface of polymer groove；S4,
Deposited copper metal is filled in polymer groove to form copper interconnecting line structure；S5, will be between copper metal by plasma etching
High molecular polymer is all removed, and metal valley is formed between copper metal；S6 fills deposition medium material in metal valley
Material；S7, the deposition of insulative material on dielectric material and copper interconnecting line structure form coating.Preferably, the high molecular polymer
It is the polymeric material of satisfactory mechanical property, is easy to be removed after forming groove and deposited copper metal.
Metal barrier is TaN layers.
The step S4 includes that the chemically mechanical polishing of the progress copper metal after deposited copper metal makes its surfacing.
The dielectric material is the SiCOH of low-k.
The step S6 includes that the chemically mechanical polishing of the progress dielectric material after deposits dielectric materials makes its surfacing.
The insulating materials is the SiN of high dielectric constant.
The present invention also provides the copper interconnecting lines obtained according to above-mentioned preparation method and dielectric material integrated morphology.
Relative to the prior art for filling copper metal in dielectric material groove, the present invention fills copper in polymer groove
Metal, the good mechanical properties being had by means of high molecular polymer itself, so that the smooth surface of groove, is forming groove
The damage that can reduce trench wall caused by etching in etching process avoids and directly performs etching (formation to dielectric material
Groove) caused by flute surfaces defect.Moreover, because high molecular polymer has stronger support performance, copper metal is formed
Copper interconnecting line structure at the top of preferably supported and be just not easy to be worn.In short, integrated morphology according to the present invention
Preparation method can effectively improve the interfacial structure of copper interconnecting line Yu dielectric material integrated morphology using Damascus technics
Performance, copper conductor abrasion caused by improving copper interconnecting line edge roughness and chemically-mechanicapolish polishing.
Detailed description of the invention
Fig. 1 is copper interconnecting line-low k dielectric materials integrated morphology preparation side according to a preferred embodiment of the present invention
The process flow chart of method.
Specific embodiment
With reference to the accompanying drawing, presently preferred embodiments of the present invention is provided, and is described in detail.
Fig. 1 is the integrated knot of copper interconnecting line-low-k (k) dielectric material according to a preferred embodiment of the present invention
The process flow chart of the preparation method of structure, specifically includes:
On semiconductor substrate 1, one layer of high molecular polymer (Polymer deposition) 2 is deposited, in polyphosphazene polymer
The surface for closing object 2 forms one layer of photolithography plate (Trench mask) 3, as shown in a)；
Polymer groove 21 is formed followed by plasma etching (Plasma etch) high molecular polymer 2, and is removed
Photolithography plate 3, as shown in b)；
Next one layer of metal barrier TaN (Metal barrier is covered in the wall surface of polymer groove 21
Deposition) 4, as shown in c)；
Next deposited copper metal (Metal deposition) 5 is filled in polymer groove 21, as shown in d)；
Chemically mechanical polishing (CMP) followed by copper metal 5 makes its surfacing, forms copper interconnecting line at this time
Structure, such as shown in (e)；
Followed by plasma etching (Plasma etch), by the high molecular polymer (Polymer between copper metal 5
Deposition) 2 (Polymer removed) all is removed, metal valley 51 is formed between copper metal, such as shown in (f).
Next the filling deposition ultralow dielectric dielectric material SiCOH (Ultra-low-k in metal valley 51
Deposition) 6, such as shown in (g)；
Next the chemically mechanical polishing for carrying out dielectric material 6 again, makes its surfacing (Ultra-low-k
Deposition), as shown in (h)；
Finally on dielectric material 6 and copper interconnecting line structure deposition of insulative material to form coating SiN (Capping
Layer deposition) 7, first copper interconnection layer line-low k dielectric materials structure is completed at this time, such as shown in (i).
Method according to this can then form second layer copper-connection in first copper interconnection layer line-low k dielectric materials structure
Line-low k dielectric materials structure etc. obtains copper interconnecting line and dielectric material integrated morphology until completing residual metallic layer.
Above-described, only presently preferred embodiments of the present invention, the range being not intended to limit the invention, of the invention is upper
Stating embodiment can also make a variety of changes.Made by i.e. all claims applied according to the present invention and description
Simply, equivalent changes and modifications fall within the claims of the invention patent.The not detailed description of the present invention is
Routine techniques content.
Claims (7)
1. a kind of preparation method of integrated morphology, which comprises the following steps:
S1 deposits one layer of high molecular polymer on a semiconductor substrate, forms one layer of photoetching on the surface of high molecular polymer
Plate；
S2 forms polymer groove by plasma etching high molecular polymer, and removes photolithography plate；
S3 covers one layer of metal barrier in the wall surface of polymer groove；
S4 fills deposited copper metal in polymer groove to form copper interconnecting line structure；
High molecular polymer between copper metal is all removed by plasma etching, forms metal between copper metal by S5
Groove；
S6 fills deposits dielectric materials in metal valley；
S7, the deposition of insulative material on dielectric material and copper interconnecting line structure form coating.
2. preparation method according to claim 1, which is characterized in that metal barrier is TaN layers.
3. preparation method according to claim 1, which is characterized in that the step S4 is carried out after being included in deposited copper metal
The chemically mechanical polishing of copper metal makes its surfacing.
4. preparation method according to claim 1, which is characterized in that the dielectric material is the SiCOH of low-k.
5. preparation method according to claim 1, which is characterized in that it is laggard that the step S6 is included in deposits dielectric materials
The chemically mechanical polishing of row dielectric material makes its surfacing.
6. preparation method according to claim 1, which is characterized in that the insulating materials is the SiN of high dielectric constant.
7. the copper interconnecting line that preparation method according to claim 1 to 6 obtains and dielectric material integrated morphology.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910340421.1A CN110112056A (en) | 2019-04-25 | 2019-04-25 | A kind of preparation method of integrated morphology and thus obtained copper interconnecting line and dielectric material integrated morphology |
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|---|---|---|---|
| CN201910340421.1A CN110112056A (en) | 2019-04-25 | 2019-04-25 | A kind of preparation method of integrated morphology and thus obtained copper interconnecting line and dielectric material integrated morphology |
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| CN110112056A true CN110112056A (en) | 2019-08-09 |
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| CN201910340421.1A Pending CN110112056A (en) | 2019-04-25 | 2019-04-25 | A kind of preparation method of integrated morphology and thus obtained copper interconnecting line and dielectric material integrated morphology |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050090100A1 (en) * | 2003-10-24 | 2005-04-28 | Been Jon Woo | Simplified dual damascene process |
| US20090162793A1 (en) * | 2007-12-22 | 2009-06-25 | Choi Kwang Seon | Method of Manufacturing Metal Interconnection of Semiconductor Device |
| CN102683274A (en) * | 2012-06-05 | 2012-09-19 | 上海集成电路研发中心有限公司 | Air-gap process applied to copper interconnection |
| CN103515304A (en) * | 2012-06-19 | 2014-01-15 | 台湾积体电路制造股份有限公司 | Etch damage and esl free dual damascene metal interconnect |
| CN104025294A (en) * | 2011-10-07 | 2014-09-03 | 英特尔公司 | Formation of DRAM capacitor among metal interconnect |
| CN105374740A (en) * | 2014-08-29 | 2016-03-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof, and electronic device |
| US20160358851A1 (en) * | 2015-06-03 | 2016-12-08 | GlobalFoundries, Inc. | Integrated circuits including organic interlayer dielectric layers and methods for fabricating the same |
| CN109560098A (en) * | 2018-11-27 | 2019-04-02 | 德淮半导体有限公司 | Imaging sensor and forming method thereof |
-
2019
- 2019-04-25 CN CN201910340421.1A patent/CN110112056A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050090100A1 (en) * | 2003-10-24 | 2005-04-28 | Been Jon Woo | Simplified dual damascene process |
| US20090162793A1 (en) * | 2007-12-22 | 2009-06-25 | Choi Kwang Seon | Method of Manufacturing Metal Interconnection of Semiconductor Device |
| CN104025294A (en) * | 2011-10-07 | 2014-09-03 | 英特尔公司 | Formation of DRAM capacitor among metal interconnect |
| CN102683274A (en) * | 2012-06-05 | 2012-09-19 | 上海集成电路研发中心有限公司 | Air-gap process applied to copper interconnection |
| CN103515304A (en) * | 2012-06-19 | 2014-01-15 | 台湾积体电路制造股份有限公司 | Etch damage and esl free dual damascene metal interconnect |
| CN105374740A (en) * | 2014-08-29 | 2016-03-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof, and electronic device |
| US20160358851A1 (en) * | 2015-06-03 | 2016-12-08 | GlobalFoundries, Inc. | Integrated circuits including organic interlayer dielectric layers and methods for fabricating the same |
| CN109560098A (en) * | 2018-11-27 | 2019-04-02 | 德淮半导体有限公司 | Imaging sensor and forming method thereof |
Non-Patent Citations (2)
| Title |
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| 张磊等: "0.13μm铜互连工艺鼓包状缺陷问题的解决 ", 《电子与封装》 * |
| 成立等: "VLSI芯片制备中的多层互连新技术 ", 《半导体技术》 * |
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