CN110109858A - Bus architecture, server, internal storage data reading/writing method and readable storage medium storing program for executing - Google Patents
Bus architecture, server, internal storage data reading/writing method and readable storage medium storing program for executing Download PDFInfo
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- CN110109858A CN110109858A CN201910375712.4A CN201910375712A CN110109858A CN 110109858 A CN110109858 A CN 110109858A CN 201910375712 A CN201910375712 A CN 201910375712A CN 110109858 A CN110109858 A CN 110109858A
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 230000015654 memory Effects 0.000 claims abstract description 75
- 230000005540 biological transmission Effects 0.000 claims description 9
- 238000004590 computer program Methods 0.000 claims description 5
- 238000011161 development Methods 0.000 claims description 5
- 238000012546 transfer Methods 0.000 claims description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
Abstract
This application discloses a kind of bus architecture, the bus architecture includes the target hardware equipment being connect by bus with bus control unit；The memory modules of the bus control unit are provided with, the corresponding internal storage data read-write operation of the reading and writing data instruction execution for sending according to the target hardware equipment to the bus control unit.The application can be improved the memory read-write ability of bus architecture.Disclosed herein as well is a kind of server, a kind of internal storage data reading/writing method and a kind of computer readable storage mediums, have the above beneficial effect.
Description
Technical field
The present invention relates to field of computer technology, in particular to a kind of bus architecture, a kind of server, a kind of internal storage data
Reading/writing method and a kind of computer readable storage medium.
Background technique
Bus (Bus) is that the common communication main line of information is transmitted between the various functional components of computer, and bus may include
Data/address bus, address bus and control bus.Bus is a kind of internal structure, it is cpu, memory, Input/Output Device transmitting
The all parts of the highway of information, host are connected by bus, external equipment by corresponding interface circuit again and always
Line is connected, so as to form computer hardware system.
In the related technology, the bus structures (i.e. bus architecture) of server be all realized centered on CPU, such as
QPI bus, PCIe bus.These are all the buses centered on CPU.Memory hangs over CPU in the following, other device (equipment) pass through
Various buses and CPU are interconnected.But in Computer Architecture, a large amount of data are calculated and storage is by memory, institute
To exist largely to the read-write operation of memory.And bus in the related technology is all to hang over CPU in the following, all pairs of memory read-writes
Operation will lead to limitation of the bus architecture to memory literacy by CPU by CPU.
Therefore, how to improve the memory read-write ability of bus architecture is the technology that those skilled in the art need to solve at present
Problem.
Summary of the invention
The purpose of the application is to provide a kind of bus architecture, a kind of server, a kind of internal storage data reading/writing method and one kind
Computer readable storage medium can be improved the memory read-write ability of bus architecture.
In order to solve the above technical problems, the application provides a kind of bus architecture, which includes:
The target hardware equipment being connect by bus with bus control unit；
Be provided with the memory modules of the bus control unit, for according to the target hardware equipment to the bus marco
The corresponding internal storage data read-write operation of reading and writing data instruction execution that device is sent.
Optionally, the hardware device include any one of CPU, GPU, FPGA and Switch component or appoint several groups
It closes.
Optionally, the Switch component is for connecting development hardware equipment；Wherein, the development hardware equipment includes
FPGA and/or GPU.
Present invention also provides a kind of servers, including any one of the above bus architecture.
Present invention also provides a kind of internal storage data reading/writing methods, are applied to any one of the above bus architecture, the memory
Data read-write method includes:
It receives target hardware device and is sent through the bus reading and writing data instruction；
The reading and writing data is executed in memory modules instructs corresponding internal storage data read-write operation.
Optionally, when reading and writing data instruction is internal storage data reading instruction, the data are executed in memory modules
The internal storage data read-write operation of read write command includes:
Inquire corresponding with internal storage data reading instruction target read-write data in the memory modules, and by the target
Read-write data pass through the bus transfer to the target hardware device.
Optionally, further includes:
Detect the transmission state of the target read-write data；
When the transmission state exception, warning message is generated.
Present invention also provides a kind of computer readable storage mediums, are stored thereon with computer program, the computer
Program realizes the step of above-mentioned internal storage data reading/writing method executes when executing.
This application provides a kind of bus architectures, including the target hardware equipment being connect by bus with bus control unit；
The memory modules of the bus control unit are provided with, for what is sent according to the target hardware equipment to the bus control unit
The corresponding internal storage data read-write operation of reading and writing data instruction execution.
The application by being arranged bus control unit in memory modules, all target hardware equipments pass through bus with it is interior
Bus control unit connection in storing module, saves as the bus architecture design at center within realization.Due to bus provided by the present application
Structure is centered on CPU, therefore the reading and writing data instruction of target device transmission needs not move through CPU and can directly reach memory mould
Block, so that memory modules execute corresponding internal storage data read-write operation.Total wire frame at center is saved as this application provides within,
Therefore it can be avoided limitation of the CPU to memory literacy, improve the memory read-write ability of bus architecture.The application also mentions simultaneously
A kind of server, a kind of internal storage data reading/writing method and a kind of computer readable storage medium have been supplied, there is above-mentioned beneficial effect,
Details are not described herein.
Detailed description of the invention
In ord to more clearly illustrate embodiments of the present application, attached drawing needed in the embodiment will be done simply below
It introduces, it should be apparent that, the drawings in the following description are only some examples of the present application, for ordinary skill people
For member, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of structural schematic diagram of bus architecture provided by the embodiment of the present application；
Fig. 2 is memory module structure schematic diagram；
Fig. 3 is a kind of flow chart of internal storage data reading/writing method provided by the embodiment of the present application.
Specific embodiment
To keep the purposes, technical schemes and advantages of the embodiment of the present application clearer, below in conjunction with the embodiment of the present application
In attached drawing, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described embodiment is
Some embodiments of the present application, instead of all the embodiments.Based on the embodiment in the application, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall in the protection scope of this application.
Below referring to Figure 1, Fig. 1 is a kind of structural schematic diagram of bus architecture provided by the embodiment of the present application, specifically
Structure may include:
The target hardware equipment 200 being connect by bus 300 with bus control unit 101；
Be provided with the memory modules 100 of the bus control unit 101, for according to the target hardware equipment 200 to institute
State the corresponding internal storage data read-write operation of reading and writing data instruction execution of the transmission of bus control unit 101.
Fig. 2 is referred to, Fig. 2 is memory module structure schematic diagram, and DDR is memory in Fig. 2, and DDR PHY is the port of memory
Physical layer, DDR Controller are memory control logic layer, and BUS is bus, and Arbiter is bus arbitration.The present embodiment phase
When can when the bus control unit that is set in CPU of original is moved to that target device is to memory read-write in memory modules 100
Directly to be communicated with bus control module.Because bus control module 101 is set on memory modules, it is equivalent to target
Equipment is directly communicated with memory modules, is no longer communicated indirectly by CPU.Connection relationship between memory modules and bus control unit
Directly bus control unit is hung over similar to common memory grain or memory bar in the following, interface is exactly common memory interface.
Memory modules 100 as shown in Figure 1 are directly connected with bus 300, and memory modules 100 are used as active device, other devices
Part (i.e. hardware device 200) is used as and is connected in bus from equipment.There is bus control unit on memory modules 100, is responsible for bus
Scheduling and the control of memory consistency.
As a kind of feasible embodiment, above-mentioned target hardware equipment 200 may include CPU, GPU, FPGA and
Any one of Switch component appoints several combinations.Wherein, Switch component can be used for connecting development hardware equipment；The expansion
Opening up hardware device includes FPGA and/or GPU, to realize that hardware device can connect the additional extension of quantity.The present embodiment does not limit
The type and quantity of target hardware equipment, those skilled in the art can be according to practical situations flexible choices.
The implementation of bus structures provided by procedure declaration the present embodiment below by FPGA read/write memory: when
FPGA needs internally to deposit when being written and read, and memory read-write instruction is directly sent to the bus marco of memory modules by bus
Device executes memory read-write in memory modules and instructs corresponding internal storage data read-write operation, and read-write operation result is passed through bus
Return directly to FPGA.And in the bus architecture centered on CPU, FPGA needs internally to deposit when be written and read, first
Read-write requests are sent to CPU, CPU is translated into CPU to the Read-write Catrol of memory according to the content of read-write requests, works as CPU
It is obtained from memory and relays to FPGA after data.It can be seen that in the present embodiment bus architecture no longer centered on CPU,
No longer pass through CPU when other hardware device read/write memories, it can be without being bound by the performance of CPU.
The present embodiment by being arranged bus control unit in memory modules, all target hardware equipments pass through bus with
Bus control unit connection in memory modules, saves as the bus architecture design at center within realization.Memory directly hangs over total line traffic control
Device processed is in the following, bus control unit becomes a part of memory modules.In with CPU being due to bus structures provided in this embodiment
The heart, therefore the reading and writing data instruction of target device transmission needs not move through CPU and can directly reach memory modules, so as to memory modules
Execute corresponding internal storage data read-write operation.Total wire frame at center is saved as within present embodiments providing, therefore can be avoided
Limitation of the CPU to memory literacy improves the memory read-write ability of bus architecture.
It may include any one bus architecture in above-described embodiment present invention also provides a kind of server.Certainly should
Server can also include various network interfaces, the components such as power supply.
Fig. 3 is referred to below, Fig. 3 is a kind of flow chart of internal storage data reading/writing method provided by the embodiment of the present application,
The present embodiment can be applied to as any one bus architecture, specific steps may include: in above-described embodiment
S1: it receives target hardware device and is sent through the bus reading and writing data instruction；
S2: the reading and writing data is executed in memory modules and instructs corresponding internal storage data read-write operation.
The present embodiment is realized based on bus architecture described in the corresponding embodiment of Fig. 1, the execution master of the present embodiment
Body is memory modules, target hardware device be sent through the bus reading and writing data instruction can for target hardware device directly with it is interior
Information transmitting between storing module, after memory modules receive reading and writing data instruction, memory modules are executed according to reading and writing data
Corresponding internal storage data read-write operation, so that reading and writing data is executed corresponding read-write operation result, to be back to corresponding target hard
Part equipment.The type and quantity of the hardware device that sets the goal unlimited in the present embodiment, target hardware equipment may include CPU,
GPU, FPGA and Switch component.
Specifically, when reading and writing data instruction is internal storage data reading instruction in above-described embodiment, in S2 in memory modules
The internal storage data read-write operation for executing reading and writing data instruction can be with specifically: inquire in the memory modules with the memory
The corresponding target of data reading instructions reads and writes data, and target read-write data are hard to the target by the bus transfer
Part device.Further, the transmission state of target read-write data can also be detected according to predetermined period；When detecting the transmission
When abnormal state, warning message is generated.
The present embodiment realizes that the bus architecture is total by being arranged in memory modules based on the corresponding bus architecture of Fig. 1
Lane controller, all target hardware equipments pass through bus and connect with the bus control unit in memory modules, realize with memory
Centered on bus architecture design.Since the bus structures are centered on CPU, the reading and writing data that target device is sent is instructed
Memory modules can directly be reached by needing not move through CPU, so that memory modules execute corresponding internal storage data read-write operation.This implementation
Example saves as the internal storage data read-write scheme of total wire frame at center within providing, therefore can be avoided CPU to memory read-write energy
The limitation of power improves the memory read-write ability of bus architecture.
Present invention also provides a kind of computer readable storage mediums, have computer program thereon, the computer program
It is performed and step provided by above-described embodiment may be implemented.The storage medium may include: USB flash disk, mobile hard disk, read-only deposit
Reservoir (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or
The various media that can store program code such as CD.
Each embodiment is described in a progressive manner in specification, the highlights of each of the examples are with other realities
The difference of example is applied, the same or similar parts in each embodiment may refer to each other.For system disclosed in embodiment
Speech, since it is corresponded to the methods disclosed in the examples, so being described relatively simple, related place is referring to method part illustration
?.It should be pointed out that for those skilled in the art, under the premise of not departing from the application principle, also
Can to the application, some improvement and modification can also be carried out, these improvement and modification also fall into the protection scope of the claim of this application
It is interior.
It should also be noted that, in the present specification, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that the process, method, article or equipment for including a series of elements not only includes that
A little elements, but also including other elements that are not explicitly listed, or further include for this process, method, article or
The intrinsic element of equipment.Under the situation not limited more, the element limited by sentence "including a ..." is not arranged
Except there is also other identical elements in the process, method, article or apparatus that includes the element.
Claims (8)
1. a kind of bus architecture characterized by comprising
The target hardware equipment being connect by bus with bus control unit；
The memory modules of the bus control unit are provided with, for sending out according to the target hardware equipment to the bus control unit
The corresponding internal storage data read-write operation of the reading and writing data instruction execution sent.
2. bus architecture according to claim 1, which is characterized in that the hardware device include CPU, GPU, FPGA and
Any one of Switch component appoints several combinations.
3. bus architecture according to claim 2, which is characterized in that the Switch component is set for connecting development hardware
It is standby；Wherein, the development hardware equipment includes FPGA and/or GPU.
4. a kind of server, which is characterized in that including any one bus architecture as described in claims 1 to 3.
5. a kind of internal storage data reading/writing method, which is characterized in that be applied to total coil holder as described in any one of claims 1 to 3
Structure, the internal storage data reading/writing method include:
It receives target hardware device and is sent through the bus reading and writing data instruction；
The reading and writing data is executed in memory modules instructs corresponding internal storage data read-write operation.
6. internal storage data reading/writing method according to claim 5, which is characterized in that when reading and writing data instruction is memory number
When according to reading instruction, the internal storage data read-write operation that the reading and writing data instruction is executed in memory modules includes:
Target read-write data corresponding with the internal storage data reading instruction in the memory modules are inquired, and the target is read and write
Data pass through the bus transfer to the target hardware device.
7. internal storage data reading/writing method according to claim 6, which is characterized in that further include:
Detect the transmission state of the target read-write data；
When the transmission state exception, warning message is generated.
8. a kind of computer readable storage medium, which is characterized in that be stored with computer on the computer readable storage medium
Program realizes the internal storage data reading/writing method as described in any one of claim 5 to 7 when the computer program is executed by processor
The step of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201910375712.4A CN110109858A (en) | 2019-05-07 | 2019-05-07 | Bus architecture, server, internal storage data reading/writing method and readable storage medium storing program for executing |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910375712.4A CN110109858A (en) | 2019-05-07 | 2019-05-07 | Bus architecture, server, internal storage data reading/writing method and readable storage medium storing program for executing |
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Citations (6)
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|---|---|---|---|---|
| CN1696917A (en) * | 2004-07-07 | 2005-11-16 | 威盛电子股份有限公司 | Direct internal storage access controller in master-slave system and bus structure |
| CN101078991A (en) * | 2006-05-23 | 2007-11-28 | 环达电脑(上海)有限公司 | BIOS read-write memory SPD based computer system information conservation and read method |
| CN101142562A (en) * | 2005-03-14 | 2008-03-12 | 松下电器产业株式会社 | Bus controller |
| US20160328340A1 (en) * | 2012-07-19 | 2016-11-10 | International Business Machines Corporation | Memory subsystem and computer system |
| CN106557442A (en) * | 2015-09-28 | 2017-04-05 | 北京兆易创新科技股份有限公司 | A kind of chip system |
| CN108733594A (en) * | 2017-04-13 | 2018-11-02 | 慧荣科技股份有限公司 | Memory controller and data storage device |
-
2019
- 2019-05-07 CN CN201910375712.4A patent/CN110109858A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1696917A (en) * | 2004-07-07 | 2005-11-16 | 威盛电子股份有限公司 | Direct internal storage access controller in master-slave system and bus structure |
| CN101142562A (en) * | 2005-03-14 | 2008-03-12 | 松下电器产业株式会社 | Bus controller |
| CN101078991A (en) * | 2006-05-23 | 2007-11-28 | 环达电脑(上海)有限公司 | BIOS read-write memory SPD based computer system information conservation and read method |
| US20160328340A1 (en) * | 2012-07-19 | 2016-11-10 | International Business Machines Corporation | Memory subsystem and computer system |
| CN106557442A (en) * | 2015-09-28 | 2017-04-05 | 北京兆易创新科技股份有限公司 | A kind of chip system |
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Application publication date: 20190809 |