CN110100303A - A kind of preparation method of grapheme transistor - Google Patents
A kind of preparation method of grapheme transistor Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 39
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 85
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- 238000000034 method Methods 0.000 claims abstract description 63
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- 229910052751 metal Inorganic materials 0.000 claims description 50
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- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 10
- 239000007772 electrode material Substances 0.000 claims description 8
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- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
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- 239000010703 silicon Substances 0.000 claims description 6
- 229910052763 palladium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The embodiment of the present application discloses a kind of preparation method of grapheme transistor, to simplify the technical process of preparation grapheme transistor.Method includes: to cover graphene layer on substrate to form the first sample；Source electrode and drain electrode are prepared on the graphene layer in the first sample, form the second sample；The first gate medium is deposited on the second sample, forms third sample, first grid dielectric overlay source electrode, drain electrode and graphene layer；Self-aligned etching is carried out to third sample, form the 4th sample, 4th sample includes substrate, source electrode, drain electrode, channel region and the second gate medium, channel region is the conductive region for being used to connect source electrode and drain electrode that graphene layer is formed after Self-aligned etching, and the second gate medium is the gate medium for covering source electrode, drain electrode and channel region that the first gate medium is formed after Self-aligned etching；Gate electrode is prepared on the second gate medium in the 4th sample, forms grapheme transistor.
Description
This application involves technical field of semiconductors more particularly to a kind of preparation methods of grapheme transistor.
Graphene (Graphene) is a kind of two dimensional crystal that the carbon atom by monolayer honeycomb crystal lattice forms.The electronic structures different from common three-dimensional graphite that graphene has bring superior electrology characteristic, such as higher electron mobility and high saturated velocity for it.In addition, the radiofrequency characteristics of graphene are also always research hotspot.At present in document report, the maximum cut-off of graphene is more than 300GHz, and maximum frequency of oscillation has also reached 200GHz.
Since graphene has superior electrology characteristic and radiofrequency characteristics, grapheme transistor has obtained the extensive concern of industry.
In traditional handicraft, grapheme transistor is prepared in the following way: etching the graphene of non-channel region on graphene layer using photolithographicallpatterned, then prepares source electrode and drain electrode at the both ends of channel region；Then gate medium is deposited between source electrode and drain electrode, and removes the extra gate medium of non-channel region by photolithographicallpatterned, finally prepares grid on the gate medium between source electrode and drain electrode.Two step lithography operations are at least needed using this grapheme transistor preparation method, technical process is cumbersome, high process cost.
To sum up, the preparation method of existing grapheme transistor has that technical process is cumbersome.
Summary of the invention
The embodiment of the present application provides a kind of preparation method of grapheme transistor, to simplify the technical process of preparation grapheme transistor.
In a first aspect, the embodiment of the present application provides a kind of preparation method of grapheme transistor, this method comprises the following steps: covering graphene layer on substrate, forms the first sample；Source electrode and drain electrode are prepared on the graphene layer in the first sample, form the second sample；The first gate medium is deposited on the second sample, forms third sample, first grid dielectric overlay source electrode, drain electrode and graphene layer；Self-aligned etching is carried out to third sample, form the 4th sample, 4th sample includes substrate, source electrode, drain electrode, channel region and the second gate medium, channel region is the conductive region for being used to connect source electrode and drain electrode that graphene layer is formed after Self-aligned etching, and the second gate medium is the gate medium for covering source electrode, drain electrode and channel region that the first gate medium is formed after Self-aligned etching；Gate electrode is prepared on the second gate medium in the 4th sample, forms grapheme transistor.
Using the above scheme, graphene layer and the first gate medium have been prepared before performing etching operation, therefore the gate medium in non-channel region and the first gate medium in graphene layer in addition to the second gate medium can be etched away when performing etching operation simultaneously.Compared with the scheme for needing respectively to perform etching graphene layer and gate medium by two step lithography operations in the preparation method for the grapheme transistor that the prior art provides, the technical process of the preparation method of above-mentioned grapheme transistor is simplified, and preparation efficiency is improved.
In a kind of possible design, Self-aligned etching is carried out to third sample, can specifically be accomplished in that and Self-aligned etching is carried out to third sample using plasma cleaner, etching gas is oxygen and argon gas.
By experiment test discovery, as oxygen (O2) flow be 10sccm, the flow of argon gas (Ar) is 40sccm and the power of plasma cleaner is 10W, when etch period is 2min, etching effect is preferable.Certainly, in the identical situation of the parameters such as the flow of etching gas, the power of plasma cleaner and etch period, etching effect also can be with experiment
The difference of environment and change.Therefore, in the embodiment of the present application to the occurrence of these parameters without limitation, as long as etching effect can be reached.
In a kind of possible design, the first gate medium is deposited on the second sample, can specifically be realized by the following two kinds mode:
Mode one
One layer of positive photoresist of spin coating on the second sample, it will be in the pattern transfer of the first gate medium to the second sample using photolithographicallpatterned, seed layer using electron-beam evaporation mode growth aluminum metal thin layer as the first gate medium, and aluminum oxide is grown using atomic layer deposition ALD mode, as the first gate medium.
Mode two
One layer of positive photoresist of spin coating on the second sample grows yttrium thin metal layer using electron-beam evaporation mode, yttrium thin metal layer is oxidized to yttrium oxide using hot baking mode, as the first gate medium using photolithographicallpatterned by the pattern transfer of the first gate medium to the second sample.
It should be noted that the mode for depositing the first gate medium on the second sample includes but is not limited to both the above.The implementation (such as non-lithographic mode) of other deposition gate mediums is equally applicable in the embodiment of the present application.
In a kind of possible design, gate electrode is prepared on the second gate medium in the 4th sample, can specifically be realized by the following two kinds mode:
Mode one
Gate electrode is prepared on the second gate medium in the 4th sample using electron beam evaporation metal and by the way of removing.
Mode two
Gate electrode is prepared on the second gate medium in the 4th sample using metal sputtering and by the way of removing.
It should be noted that the mode for preparing gate electrode includes but is not limited to both the above.The mode that other prepare gate electrode is equally applicable in the embodiment of the present application.
In a kind of possible design, source electrode and drain electrode are prepared on the graphene layer in the first sample, can specifically be realized by the following two kinds mode:
Mode one
Source electrode and drain electrode are prepared on graphene layer using electron beam evaporation metal and by the way of removing.
Mode two
Source electrode and drain electrode are prepared on graphene layer using metal sputtering and by the way of removing.
Similarly, the mode for preparing source electrode and drain electrode includes but is not limited to both the above.The mode that other prepare gate electrode is equally applicable in the embodiment of the present application.
In a kind of possible design, the electrode material of source electrode and drain electrode is by titanium and Jin Zucheng；Alternatively, the electrode material of source electrode and drain electrode is by titanium, palladium and Jin Zucheng.
In a kind of possible design, graphene layer is covered on substrate, can be specifically accomplished in that by the way of micromechanics removing or chemical vapor deposition CVD and be covered graphene layer on substrate.
In a kind of possible design, substrate is that Sapphire Substrate or substrate are made of high resistant silicon layer and the hafnium oxide insulating layer formed on high resistant silicon layer by ALD mode.
Fig. 1 is a kind of structural schematic diagram of grapheme transistor provided by the embodiments of the present application；
Fig. 2 is the structural schematic diagram of another grapheme transistor provided by the embodiments of the present application；
Fig. 3 is a kind of flow diagram of the preparation method for grapheme transistor that the prior art provides；
Fig. 4 is the flow diagram of the preparation method of the first grapheme transistor provided by the embodiments of the present application；
Fig. 5 is the flow diagram of the preparation method of second of grapheme transistor provided by the embodiments of the present application；
Fig. 6 is the structural schematic diagram for the grapheme transistor being prepared using the embodiment of the present application；
Fig. 7 is the DC test result schematic diagram for the grapheme transistor being prepared using the embodiment of the present application；
Fig. 8 is the alternating-current measurement result schematic diagram for the grapheme transistor being prepared using the embodiment of the present application；
Fig. 9 is the flow diagram of the preparation method of the third grapheme transistor provided by the embodiments of the present application；
Figure 10 is the flow diagram of the preparation method of the 4th kind of grapheme transistor provided by the embodiments of the present application.
Since graphene has superior electrology characteristic and radiofrequency characteristics, grapheme transistor has obtained the extensive concern of industry.Grapheme transistor can be divided into multiple types, such as can be divided into top gate type grapheme transistor and non-top gate type grapheme transistor according to the position difference of gate electrode.
The structure of non-top gate type grapheme transistor can be as shown in Figure 1.Grapheme transistor shown in FIG. 1 includes substrate, gate medium, gate electrode G, graphene channel layers, source electrode S and drain electrode D.Wherein, gate medium is formed in substrate；Gate electrode G is formed in gate medium, achievees the effect that insulate with graphene channel layers, source electrode S, drain electrode D；Graphene channel layers are formed on gate medium；Source electrode S and drain electrode D is located at the both ends of graphene channel layers, and the two is electrically connected by graphene channel layers.
The structure of top gate type grapheme transistor can be as shown in Figure 2.Grapheme transistor shown in Fig. 2 includes substrate, graphene channel layers, gate medium, gate electrode G, source electrode S and drain electrode D.Wherein, graphene channel layers are formed in substrate；Source electrode S and drain electrode D is located at the both ends of graphene channel layers, and the two is electrically connected by graphene channel layers；Gate medium is covered on source electrode S, graphene channel layers and drain electrode D；Gate electrode G is formed on gate medium.
Top gate type grapheme transistor is compared with non-top gate type grapheme transistor, and the thickness of grid is smaller, grid-control ability is stronger.The grapheme transistor prepared in the embodiment of the present application is top gate type grapheme transistor.
In the prior art, when preparing top gate type grapheme transistor (hereinafter referred to as " grapheme transistor "), the method generallyd use can be as shown in Figure 3.
1, graphene layer is covered on substrate；
Wherein, substrate is completely covered in graphene layer.
2, the graphene layer positioned at substrate two sides is etched away using photolithographicallpatterned, forms graphene channel layers.
3, source electrode S and drain electrode D are prepared at the both ends of graphene channel layers.
4, gate medium is grown on the sample that step 3 is formed.
Wherein, the sample of step 3 formation is completely covered in gate medium.
5, the gate medium that the sample two sides of step 4 formation are etched away using photolithographicallpatterned, forms the gate dielectric layer of grapheme transistor.
6, gate electrode G is prepared on the gate dielectric layer formed in steps of 5, to prepare grapheme transistor.
It is not difficult to find out that at least needing two step photoetching that grapheme transistor can just be prepared using method shown in Fig. 3.And the technical process of photoetching process is complex, such as each photoetching requires preparation mask substrate, mask pattern.In addition, also needed using photoresist in photoetching process, and the residual of photoresist will increase the contact resistance of grapheme transistor.Therefore, grapheme transistor is prepared using preparation method shown in Fig. 3, technical process is cumbersome, high process cost.
The embodiment of the present application provides a kind of preparation method of grapheme transistor, to simplify the technical process of preparation grapheme transistor.
It should be noted that in the embodiment of the present application, it is multiple to refer to two or more.In addition, it is necessary to understand, in the description of the embodiment of the present application, the vocabulary such as " first ", " second " are only used for distinguishing the purpose of description, are not understood to indicate or imply relative importance, can not be interpreted as indication or suggestion sequence.
The embodiment of the present application is described in further detail below in conjunction with attached drawing.
It referring to fig. 4, is a kind of preparation method of grapheme transistor provided by the embodiments of the present application.This method comprises the following steps:
S401: covering graphene layer on substrate, forms the first sample.
In the embodiment of the present application, without limitation to the concrete type of substrate.For example, substrate can be Sapphire Substrate, it is also possible to by high resistant silicon layer and the hafnium oxide (HfO formed on high resistant silicon layer by atomic layer deposition (atomic layer deposition, ALD) mode2) insulating layer composition.
Specifically, the mode that micromechanics removing or chemical vapor deposition (chemical vapor deposition, CVD) can be used in S401 covers graphene layer on substrate.
S402: preparing source electrode and drain electrode on the graphene layer in the first sample, forms the second sample.
Specifically, when preparing source electrode and drain electrode, there are many modes that can be respectively adopted.For example, using electron beam evaporation metal and removing by the way of (Lift-off) or splash-proofing sputtering metal and removing the mode of (Lift-off).
Illustratively, source electrode or drain electrode can be prepared on the graphene layer in the first sample by the way of electron beam evaporation metal+removing (Lift-off).Wherein, it can be using the metal that electron beam evaporation metal mode is evaporated with a thickness of titanium (Ti) metal of 1nm, palladium (Pd) metal with a thickness of 50nm and gold (Au) metal these three metals with a thickness of 100nm.That is, the electrode material of source electrode or drain electrode can be made of titanium (Ti), palladium (Pd) and golden (Au).
Illustratively, source electrode or drain electrode can be prepared on the graphene layer in the first sample by the way of splash-proofing sputtering metal+removing (Lift-off).Wherein, titanium (Ti) metal with a thickness of 15nm and gold (Au) metal both metals with a thickness of 100nm can be using the metal that splash-proofing sputtering metal mode sputters.That is, the electrode material of source electrode or drain electrode can be made of titanium (Ti) and golden (Au).
It should be noted that the preparation method of source electrode and drain electrode can be the same or different in the embodiment of the present application.It should be understood, of course, that technical process is more simplified when the preparation method of source electrode and drain electrode is identical.
S403: depositing the first gate medium on the second sample, forms third sample.
Wherein, first grid dielectric overlay source electrode, drain electrode and graphene layer.
When specific implementation, deposited on the second sample the first gate medium implementation can there are many.Two of them implementation is only enumerated below.
Mode one
One layer of positive photoresist of spin coating on the second sample, it will be in the pattern transfer of the first gate medium to the second sample using photolithographicallpatterned, seed layer using electron-beam evaporation mode growth aluminum metal (Al) thin layer as the first gate medium, then grows aluminum oxide (Al using ALD mode2O3), as the first gate medium.
Illustratively, the thickness of aluminum metal (Al) thin layer for using electron-beam evaporation mode to grow can be 2nm, the aluminum oxide (Al grown using ALD mode2O3) thickness can be 15nm, the operation temperature of ALD can be 90 DEG C.
Mode two
One layer of positive photoresist of spin coating on the second sample, it will be in the pattern transfer of the first gate medium to the second sample using photolithographicallpatterned, yttrium (Y) thin metal layer is grown using electron-beam evaporation mode, yttrium (Y) thin metal layer is then oxidized to by yttrium oxide (Y using hot baking mode2O3), as the first gate medium.
Illustratively, the thickness of yttrium (Y) thin metal layer for using electron-beam evaporation mode to grow can be 3nm, the yttrium oxide (Y aoxidized using hot baking mode2O3) with a thickness of 5nm, heat dries that the operation temperature of operation is 180 DEG C, to dry the time be 10min to heat.
It should be noted that the mode for depositing the first gate medium on the second sample includes but is not limited to both the above.The implementation (such as non-lithographic mode) of other deposition gate mediums is equally applicable in the embodiment of the present application.
S404: Self-aligned etching is carried out to third sample, forms the 4th sample.
Wherein, 4th sample includes substrate, source electrode, drain electrode, channel region and the second gate medium, channel region is the conductive region for being used to connect source electrode and drain electrode that graphene layer is formed after Self-aligned etching, and the second gate medium is the gate medium for covering source electrode, drain electrode and channel region that the first gate medium is formed after Self-aligned etching.
Specifically, in S404, Self-aligned etching is carried out to third sample, can specifically be accomplished in that and Self-aligned etching is carried out to third sample using plasma cleaner, etching gas is oxygen (O2) and argon gas (Ar).
By experiment test discovery, as oxygen (O2) flow be 10sccm, the flow of argon gas (Ar) is 40sccm and the power of plasma cleaner is 10W, when etch period is 2min, etching effect is preferable.Certainly, in the identical situation of the parameters such as the flow of etching gas, the power of plasma cleaner and etch period, etching effect can also change with the difference of experimental situation.Therefore, in the embodiment of the present application to the occurrence of these parameters without limitation, as long as etching effect can be reached.
It should be noted that Self-aligned etching described in S404 can be understood as a kind of photolithographicallpatterned.Photoetching is the technology that a kind of mask pattern by mask substrate is optically transferred on plate.In S404, the graphene layer of non-channel region can be etched away by photolithographicallpatterned, while the gate medium in addition to the second gate medium is etched away from the first gate medium.Wherein, source electrode and drain electrode are not completely covered on source electrode, channel region and drain electrode in the second gate dielectric overlay obtained after etching.This is because: the second gate medium is the thin layer for being used to isolated gate electrode and channel region in grapheme transistor, therefore the second gate medium needs to cover channel region；Simultaneously in order to avoid the current leakage of channel region, the second gate medium need to be completely covered channel region, i.e. the second gate medium needs to cover source electrode, channel region and drain electrode.In addition, source electrode and drain electrode are the external connecting interfaces of the grapheme transistor, therefore source electrode and drain electrode can not be completely covered in the second gate medium for the grapheme transistor being prepared using method shown in Fig. 4.
In S404, the mask pattern utilized to the etching of the first gate medium is the mask pattern utilized in existing photolithographicallpatterned；It and is actually to be utilized to be covered on the second gate medium on graphene layer, being obtained by the first grid medium etching as autoregistration exposure mask to the etching of graphene layer.That is, in a step lithography operations in S404, mask pattern and second gate media implementation can be utilized respectively to the etching operation of the first gate medium and graphene layer, with need to realize by two step lithography operations in the prior art to the scheme of the etching of gate medium and graphene layer (such as in method shown in Fig. 3, the etching to graphene layer is realized by the lithography operations of step 2, then source electrode is being prepared, after drain electrode and gate medium, the etching to gate medium is realized by the lithography operations of step 5) it compares, using method shown in Fig. 4 technical process is simplified.
Explanation is also needed, using oxygen (O2) and argon gas (Ar) carry out Self-aligned etching and can be understood as one kind of dry etching mode.When executing S404, above-mentioned dry etching mode can be not only used, wet etching mode can also be used, do not limited this in the embodiment of the present application.As long as realizing the etching to graphene layer and the first gate medium simultaneously in a step etching operation.
S405: preparing gate electrode on the second gate medium in the 4th sample, forms grapheme transistor.
Specifically, when preparing gate electrode, can be by the way of there are many, for example, using electron beam evaporation metal and by the way of removing (Lift-off), or using splash-proofing sputtering metal and by the way of removing (Lift-off).
Illustratively, gate electrode can be prepared on the second gate medium in the 4th sample by the way of electron beam evaporation metal+removing (Lift-off).Wherein, titanium (Ti) metal with a thickness of 1nm and gold (Au) metal with a thickness of 20nm can be using the metal that electron beam evaporation metal mode is evaporated.
Illustratively, gate electrode can be prepared on the second gate medium in the 4th sample by the way of splash-proofing sputtering metal+removing (Lift-off).Wherein, titanium (Ti) metal with a thickness of 15nm and gold (Au) metal with a thickness of 100nm can be using the metal that splash-proofing sputtering metal mode sputters.
In order to make the technical process of the preparation method of grapheme transistor shown in Fig. 4 be more convenient for understanding, the embodiment of the present application also provides the preparation methods of another grapheme transistor, as shown in Figure 5.Method shown in Fig. 5 can be considered another form of method shown in Fig. 4.The structure of the sample (or finished product) formed after each step operation (S401~S405) shown in Fig. 4 can be more clearly visible that by method shown in Fig. 5.
Wherein, graphene layer, the first sample shown in available Fig. 5 are covered on substrate by executing S401.From figure 5 it can be seen that the first sample includes substrate and graphene layer.
The second sample shown in source electrode S and drain electrode D, available Fig. 5 is prepared on graphene layer by executing S402.Second sample includes substrate, graphene layer, source electrode S and drain electrode D.
The first gate medium is deposited on the second sample by executing S403, third sample shown in available Fig. 5.Third sample includes substrate, graphene layer, source electrode S, drain electrode D and the first gate medium.
Self-aligned etching, the 4th sample shown in available Fig. 5 are carried out to third sample by executing S404.4th sample includes the second gate medium that the channel region that substrate, source electrode S, drain electrode D, graphene layer are formed after Self-aligned etching and the first gate medium are formed after Self-aligned etching.
Gate electrode G is prepared on the second gate medium in the 4th sample by executing S405, grapheme transistor (finished product) can be formed.The second gate medium and gate electrode G that grapheme transistor (finished product) is formed after Self-aligned etching comprising channel region, the first gate medium that substrate, source electrode S, drain electrode D, graphene layer are formed after Self-aligned etching.
It should be noted that gate medium shown in third sample is the first gate medium in Fig. 5, gate medium shown in the 4th sample and grapheme transistor (finished product) is the second gate medium.Second gate medium is obtained by the first grid medium etching.Since the material composition of the first gate medium and the second gate medium is identical, identified in Fig. 5 with the legend of same color.
Also need explanation be, in Fig. 5, graphene shown in first sample, the second sample and third sample is " graphene layer " described in method shown in Fig. 4, and graphene shown in the 4th sample and grapheme transistor (finished product) is " channel region " described in method shown in Fig. 4.Since " graphene layer " is identical with the material composition of " channel region ", identified in Fig. 5 with the legend of same color.In addition, the graphene that the 4th sample compared with third sample, etches away is " non-channel region ".
Using the preparation method of grapheme transistor provided by the embodiments of the present application, graphene layer and the first gate medium have been prepared before performing etching operation, therefore the gate medium in non-channel region and the first gate medium in graphene layer in addition to the second gate medium can be etched away when performing etching operation simultaneously.Compared with the scheme for needing respectively to perform etching graphene layer and gate medium by two step lithography operations in the preparation method for the grapheme transistor that the prior art provides, the technical process of the preparation method of grapheme transistor provided by the embodiments of the present application is simplified, and preparation efficiency is improved.
In addition, lithography operations can have photoresist residual phenomena, increase so as to cause the contact resistance of grapheme transistor, shadow
Ring the performance of grapheme transistor.Reduce the number of lithography operations compared with the scheme that the prior art provides using the preparation method of grapheme transistor provided by the embodiments of the present application, thus photoetching glue residua is less, so that the performance for the grapheme transistor being prepared is more preferable.
Referring to Fig. 6, the grapheme transistor prepared for the preparation method using grapheme transistor provided by the embodiments of the present application.As seen from Figure 6; the graphene layer of non-channel region is etched more clean; using the preparation method of grapheme transistor provided by the embodiments of the present application while preferably completing the etching technics of grapheme transistor, effectively adequately protection also has been carried out to the graphene of channel region.
DC test and alternating-current measurement carried out to grapheme transistor shown in fig. 6, available DC test result schematic diagram shown in Fig. 7 and alternating-current measurement result schematic diagram shown in Fig. 8 (grid length in Fig. 7 and Fig. 8 for the grapheme transistor of test is 160nm).
In DC test, the main normallized current for testing grapheme transistor and mutual conductance.Wherein, mutual conductance, that is, drain current variable quantity and gate source voltage variable quantity ratio, for indicating gate source voltage to the control ability of drain current；Normallized current is the ratio of the current value for flowing through grapheme transistor and the channel width of grapheme transistor, for measuring the performance of various sizes of grapheme transistor.In Fig. 7, IdIndicate the current between the source and the drain, VtgIndicate grid voltage, VdIndicate the voltage between source electrode and drain electrode, gmRepresent mutual conductance, LgIndicate grid length.The maximum normallized current that DC test result as shown in Figure 7 can be seen that grapheme transistor shown in fig. 6 can achieve 1200mA/mm, and maximum transconductance reaches 250mS/mm, illustrate that grapheme transistor shown in fig. 6 possesses higher grid efficiency.
In alternating-current measurement, the main cutoff frequency and maximum oscillation frequency for testing grapheme transistor.Cutoff frequency and maximum oscillation frequency represent the high frequency performance of grapheme transistor.In Fig. 8, H21Indicate forward current gain, U1/2Indicate the unilateral power gain of Mason, fTIndicate cutoff frequency, fmaxIndicate maximum oscillation frequency, LgIndicate that grid length, the curve of mark " before De- embedding " represent the test result before De- embedding, the curve of mark " after De- embedding " represents the test result after De- embedding.Alternating-current measurement result as shown in Figure 8 can be seen that, cutoff frequency and maximum oscillation frequency of the grapheme transistor shown in fig. 6 before De- embedding are 22GHz, and cutoff frequency and maximum oscillation frequency of the grapheme transistor shown in fig. 6 after De- embedding are respectively 204GHz and 61GHz.
Based on above embodiments, the embodiment of the present application also provides the preparation method of other two kinds of grapheme transistors.The preparation method of both grapheme transistors can be considered a specific example of method shown in Fig. 4 or Fig. 5.Both methods is introduced separately below.
Method one
It is the flow diagram of method one referring to Fig. 9.Method shown in Fig. 9 includes the following steps:
1, the HfO of 50nm thickness is formed by ALD method on HR-Si substrate2Insulating layer, as substrate.
2, it is transferred graphene on substrate using CVD mode, forms the first sample.
3, on the first sample, source-drain electrode is prepared using the method for electron beam evaporation metal+Lift-off, forms the second sample, electrode material Ti, Pd and Au, thickness is respectively 1nm, 50nm and 100nm.
4, then one layer of positive photoresist of spin coating on the second sample in the first gate medium pattern transfer to substrate, will use seed layer of the Al of electron beam evaporation growth 2nm as the first gate medium using photolithographicallpatterned, then using the Al of 90 DEG C of atomic layer deposition growth 15nm thickness2O3As the first gate medium, third sample is formed.
5, on third sample, Self-aligned etching is carried out using graphene of the plasma cleaner to non-channel region, forms the 4th sample, etching gas is respectively the O of 10sccm2And the Ar of 40sccm, the power of plasma cleaner are about 10W, etch period 2min.
6, on the 4th sample, top-gate electrode is prepared using the method for electron beam evaporation Ti metal and Au metal (thickness is respectively 1nm and 20nm)+Lift-off, forms top gate type grapheme transistor.
It should be noted that method shown in Fig. 9 can be considered a specific example of method shown in Fig. 4 or Fig. 5.The implementation of not detailed description can be found in the associated description in method shown in Fig. 4 or Fig. 5 in method shown in Fig. 9.
Method two
It is the flow diagram of method two referring to Figure 10.Method shown in Figure 10 includes the following steps:
1, the method removed using micromechanics, is transferred graphene in Sapphire Substrate, and the first sample is formed.
2, on the first sample, source-drain electrode is prepared using the method for metal sputtering+Lift-off, forms the second sample, electrode material is Ti and Au, and thickness is respectively 15 and 100nm.
3, one layer of positive photoresist of spin coating on the second sample, then using the Y thin metal layer of electron beam evaporation growth 3nm, is then dried 10 minutes using 180 DEG C of heat using photolithographicallpatterned by the first gate medium pattern transfer to substrate, Y thin metal layer is oxidized to the Y of 5nm2O3As the first gate medium, third sample is formed.
4, on third sample, Self-aligned etching is carried out using graphene of the plasma cleaner to non-channel region, forms the 4th sample, etching gas is respectively the O of 10sccm2And the Ar of 40sccm, the power of plasma cleaner are about 10W, etch period 2min.
5, on the 4th sample, top-gate electrode is prepared using the method for sputtering Ti metal and Au metal (thickness is respectively 15nm and 100nm)+Lift-off, forms top gate type grapheme transistor.
It should be noted that method shown in Figure 10 can be considered a specific example of method shown in Fig. 4 or Fig. 5.The implementation of not detailed description can be found in the associated description in method shown in Fig. 4 or Fig. 5 in method shown in Figure 10.
To sum up, using the preparation method of grapheme transistor provided by the embodiments of the present application, it can simplify the technical process of preparation grapheme transistor.
It should be understood by those skilled in the art that, embodiments herein can provide as method, system or computer program product.Therefore, the form of complete hardware embodiment, complete software embodiment or embodiment combining software and hardware aspects can be used in the application.Moreover, the form for the computer program product implemented in the computer-usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) that one or more wherein includes computer usable program code can be used in the application.
The application is that reference is described according to the flowchart and/or the block diagram of the method for the embodiment of the present application, equipment (system) and computer program product.It should be understood that the combination of process and/or box in each flow and/or block and flowchart and/or the block diagram that can be realized by computer program instructions in flowchart and/or the block diagram.These computer program instructions be can provide to the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to generate a machine, so that generating by the instruction that computer or the processor of other programmable data processing devices execute for realizing the device for the function of specifying in one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, to be able to guide in computer or other programmable data processing devices computer-readable memory operate in a specific manner, so that instruction stored in the computer readable memory generates the manufacture including command device, which realizes the function of specifying in one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that executing series of operation steps on a computer or other programmable device to generate computer implemented processing, so that instruction executed on a computer or other programmable device is provided for realizing in one or more flows of the flowchart and/or block diagram
The step of function of being specified in one box or multiple boxes.
Obviously, those skilled in the art can carry out various modification and variations without departing from the spirit and scope of the embodiment of the present application to the embodiment of the present application.If then the application is also intended to include these modifications and variations in this way, these modifications and variations of the embodiment of the present application belong within the scope of the claim of this application and its equivalent technologies.
Claims (8)
- A kind of preparation method of grapheme transistor characterized by comprisingGraphene layer is covered on substrate, forms the first sample；Source electrode and drain electrode are prepared on the graphene layer in first sample, form the second sample；The first gate medium is deposited on second sample, forms third sample, source electrode, the drain electrode and the graphene layer described in the first grid dielectric overlay；Self-aligned etching is carried out to the third sample, form the 4th sample, 4th sample includes the substrate, the source electrode, the drain electrode, channel region and the second gate medium, the channel region is the conductive region for being used to connect the source electrode and the drain electrode that the graphene layer is formed after Self-aligned etching, and second gate medium is the gate medium for covering the source electrode, the drain electrode and the channel region that first gate medium is formed after Self-aligned etching；Gate electrode is prepared on second gate medium in the 4th sample, forms grapheme transistor.
- The method as described in claim 1, which is characterized in that Self-aligned etching is carried out to the third sample, comprising:Self-aligned etching is carried out to the third sample using plasma cleaner, etching gas is oxygen and argon gas.
- It is method according to claim 1 or 2, which is characterized in that deposit the first gate medium on second sample, comprising:One layer of positive photoresist of spin coating on second sample, it will be in the pattern transfer of first gate medium to second sample using photolithographicallpatterned, seed layer using electron-beam evaporation mode growth aluminum metal thin layer as first gate medium, and aluminum oxide is grown using atomic layer deposition ALD mode, as first gate medium；OrOne layer of positive photoresist of spin coating on second sample, it will be in the pattern transfer of first gate medium to second sample using photolithographicallpatterned, yttrium thin metal layer is grown using electron-beam evaporation mode, the yttrium thin metal layer is oxidized to by yttrium oxide using hot baking mode, as first gate medium.
- Method as claimed in any one of claims 1 to 3, which is characterized in that prepare gate electrode on second gate medium in the 4th sample, comprising:The gate electrode is prepared on second gate medium in the 4th sample using electron beam evaporation metal and by the way of removing；OrThe gate electrode is prepared on second gate medium in the 4th sample using metal sputtering and by the way of removing.
- Such as the described in any item methods of Claims 1 to 4, which is characterized in that prepare source electrode and drain electrode on the graphene layer in first sample, comprising:The source electrode and the drain electrode are prepared on the graphene layer using electron beam evaporation metal and by the way of removing；OrThe source electrode and the drain electrode are prepared on the graphene layer using metal sputtering and by the way of removing.
- Method as claimed in any one of claims 1 to 5, which is characterized in that the electrode material of the source electrode and the drain electrode is by titanium and Jin Zucheng；Alternatively,The electrode material of the source electrode and the drain electrode is by titanium, palladium and Jin Zucheng.
- Method as described in any one of claims 1 to 6, which is characterized in that cover graphene layer on substrate, comprising:Graphene layer is covered over the substrate by the way of micromechanics removing or chemical vapor deposition CVD.
- Method as described in any one of claims 1 to 7, which is characterized in that the substrate is Sapphire Substrate, or The substrate is formed by high resistant silicon layer and by the hafnium oxide insulating layer that ALD mode is formed on the high resistant silicon layer.
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