CN114203822A - Gate surrounding transistor based on transition metal sulfide and preparation method - Google Patents
Gate surrounding transistor based on transition metal sulfide and preparation method Download PDFInfo
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- 229910052723 transition metal Inorganic materials 0.000 title claims abstract description 21
- -1 transition metal sulfide Chemical class 0.000 title claims abstract description 21
- 238000002360 preparation method Methods 0.000 title abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims description 21
- 239000010409 thin film Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000010894 electron beam technology Methods 0.000 claims description 3
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 claims description 2
- 238000005566 electron beam evaporation Methods 0.000 claims description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- 238000005240 physical vapour deposition Methods 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims description 2
- 238000002207 thermal evaporation Methods 0.000 claims description 2
- 238000000407 epitaxy Methods 0.000 claims 2
- 238000001451 molecular beam epitaxy Methods 0.000 claims 1
- 238000000926 separation method Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 54
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 4
- 229910016021 MoTe2 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 229910052961 molybdenite Inorganic materials 0.000 description 2
- 229910052982 molybdenum disulfide Inorganic materials 0.000 description 2
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910003090 WSe2 Inorganic materials 0.000 description 1
- 239000002041 carbon nanotube Substances 0.000 description 1
- 229910021393 carbon nanotube Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- CWQXQMHSOZUFJS-UHFFFAOYSA-N molybdenum disulfide Chemical compound S=[Mo]=S CWQXQMHSOZUFJS-UHFFFAOYSA-N 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
Abstract
The invention belongs to the technical field of semiconductor processes, and particularly relates to a gate surrounding transistor based on transition metal sulfide and a preparation method thereof. In order to break the limitation of the existing GAAFET material system, the transistor comprises a substrate, a plurality of laminated structures, a source electrode, a drain electrode, a dielectric layer and a grid electrode; the stacked structure is formed by stacking channel layers surrounded by a grid, dielectric layers are arranged between the channel layers and the grid for separation, and the drain, the source and the grid are also arranged between the dielectric layers for separation.
Description
Technical Field
The invention belongs to the technical field of semiconductor processes, and particularly relates to a gate surrounding transistor based on transition metal sulfide and a preparation method thereof.
Background
Since the introduction of moore's law in the seventies of the last century, it has always affected the development of the integrated circuit industry. The emphasis of moore's law is on increasing the number of transistors on a chip per unit area by times, increasing the performance of the chip while continuously reducing the manufacturing cost, and thus semiconductor process technology is continuously advancing and the size of the transistors is moving from the micrometer scale to the nanometer scale today. However, after the nano-scale is developed, moore's law is in a dilemma, on one hand, the transistor size faces physical limits, and the continuous upgrading of the semiconductor process technology faces difficulty, and on the other hand, the power consumption is increased due to the fact that the transistor is multiplied, and the cost cannot be reduced. At 28 nm node, the stereo fin Field Effect transistor (FinFET) replaces the planar transistor which has moved to the limit, and continues the refulgence of moore's law, but now 3 nm node, FinFET has moved to the limit, and the whole ring Gate transistor (GAAFET-) (Gate all around Field Effect Transistors) becomes a new possibility to continue moore's law.
The current GAAFET mostly uses silicon as a channel material, and chinese patents CN21395861U, CN1165361A, CN110875430A and CN113035941A all describe a channel structure of a GAAFET device and a preparation method thereof, which may be different, but the channel material is silicon-based material, which not only has low carrier mobility, but also has high production cost. Developers are looking for new materials that can replace silicon based, such as transition metal sulfides, carbon nanotubes, etc.
Disclosure of Invention
The invention aims to break through the limitation of the existing GAAFET material system and provide a preparation method of a gate surrounding type transistor based on transition metal sulfide.
In order to achieve the purpose, the invention adopts the following technical scheme:
a transition metal sulfide-based gate-around transistor, the transistor comprising a substrate, a stacked structure in the form of an array, a channel layer, a source, a drain, a dielectric layer, and a gate;
the stacked structure is composed of a channel layer stack surrounded by a grid, the channel layer and the grid are separated by a dielectric layer, and the drain, the source and the grid are also separated by the dielectric layer.
Further, the channel layer is a single-layer or few-layer semiconductor two-dimensional transition metal sulfide thin film,such as MoTe2、MoS2、WSe2、MoSe2、WS2Etc.;
the dielectric layer is made of high dielectric material, such as Al2O3、SiO2、HfO2、Ta2O5、TiO2、La2O3、 HfZrO4Etc.;
the gate is a metal or metallic two-dimensional transition metal sulfide film, such as 1T phase MoTe21T phase MoS2Graphene, and the like;
the substrate is a simple substance element insulator or a compound insulator, such as silicon oxide, silicon nitride and sapphire;
the source electrode and the drain electrode are made of metal materials.
A preparation method of a gate-surrounding transistor based on transition metal sulfide comprises the following steps:
step 1, depositing an insulating layer on a substrate, depositing a channel layer, and then repeatedly depositing to obtain a laminated structure formed by the insulating layer and the channel layer alternately;
step 2, vertically etching the laminated structure in the step 1 by adopting a dry etching process to obtain an array-type laminated structure;
step 3, defining a source electrode area and a drain electrode area of each laminated structure, and depositing the source electrode area and the drain electrode area;
step 4, removing the insulating layer in the laminated structure by using a wet etching process to expose the channel layer;
step 5, depositing a dielectric layer on the surface of the channel layer, the surface of the substrate and the surfaces of the source electrode and the drain electrode which are possibly contacted with the grid electrode in the step 4;
and 6, depositing a grid electrode on the dielectric layer in the step 5 to form the transistor.
Further, the insulating layer is a high dielectric constant material, such as Al2O3、SiO2、HfO2、Ta2O5、 TiO2、La2O3、HfZrO4。
Further, any one of magnetron sputtering, a chemical vapor deposition method, an atomic layer deposition method, a physical vapor deposition method, a thermal evaporation method, electron beam evaporation, a low-pressure chemical vapor deposition method, a seed epitaxial growth method, a gas epitaxial growth method, a molecular beam epitaxial growth method, and the like may be used for the deposition.
Further, the specific method for defining the source and drain regions in step 3 is as follows: and performing exposure development on the front side and the rear side of the stacked structure in an array form by using an electron beam exposure technology or a photoetching technology, defining a source electrode region and a drain electrode region, removing the original stacked structure of the source electrode region and the drain electrode region by adopting reactive ion etching, and finally depositing the source electrode region and the drain electrode region in the source electrode region and the drain electrode region.
Furthermore, in the step 4, the insulating layer is etched by using a wet etching process, the insulating layer can be completely etched, or the insulating layer can be selectively etched, and only part of the insulating layer is etched.
Further, in the step 5 and the step 6, photoresist can be used for protecting the source electrode and the drain electrode, and then a dielectric layer and a grid electrode are deposited; the dielectric layer and the grid can also be directly deposited, and the dielectric layer is used as an insulating layer to prevent the source electrode, the drain electrode and the grid from contacting.
Compared with the prior art, the invention has the following advantages:
the invention provides a gate surrounding transistor based on transition metal sulfide and a preparation method thereof. In the transistor, the channel layer is composed of two-dimensional transition metal sulfide, and the two-dimensional transition metal sulfide has high electron mobility, high carrier concentration, atomic-level thickness and better uniformity, so that the GAAFET prepared by taking the two-dimensional transition metal sulfide as the channel layer not only enables the transistor to have better electrical performance, but also can realize superposition of more layers, and improves the integration level. Secondly, the GAAFET realizes the four-side surrounding of the channel by the grid, the contact area between the GAAFET and the channel is greatly improved, the regulation and control capability of the grid is remarkably improved, and the Moore's law can be continued.
Drawings
Fig. 1 is a structure prepared in step 1 of the gate-surrounding transistor preparation method of the present invention;
FIG. 2 shows a structure obtained in step 2 of the method for manufacturing a gate-around transistor according to the present invention;
FIG. 3 is a structure obtained by step 3 of the method for manufacturing a gate-around transistor according to the present invention;
FIG. 4 shows the structure of the gate-around transistor of the present invention obtained in step 4;
fig. 5 is a structure obtained by step 5 of the method for manufacturing a gate-around transistor according to the present invention, wherein fig. 5a is a schematic structural view, fig. 5b is a cross-sectional view, and fig. 5c is a longitudinal-sectional view;
fig. 6 is a structure obtained by step 6 of the method for manufacturing a gate-around transistor according to the present invention, wherein fig. 6a is a schematic structural view, fig. 6b is a cross-sectional view, and fig. 6c is a longitudinal-sectional view;
101-substrate, 102-insulating layer, 103-channel layer, 104-drain, 105-source, 106-dielectric layer, 107-gate.
Detailed Description
Example 1
As shown in fig. 6, a transition metal sulfide-based gate-around type transistor includes a substrate 101, a stacked structure, a channel layer 103, a source 105, a drain 104, a dielectric layer 106, and a gate 107;
depositing a plurality of laminated structures in an array form on the substrate 101, wherein the drain electrode 104 and the source electrode 105 are respectively deposited on the front side and the rear side of the laminated structures, the laminated structures are formed by stacking channel layers 103 surrounded by a grid electrode 107, the channel layers 103 are separated from the grid electrode by a dielectric layer 106, and the drain electrode 104, the source electrode 105 and the grid electrode 107 are also separated by the dielectric layer 106;
in this embodiment, the substrate 101 is silicon oxide, and the channel layer 103 is a semiconductor phase MoTe2The thin film, the source electrode 105 is gold, the drain electrode 104 is gold, the dielectric layer 106 is hafnium oxide, and the gate electrode 107 is metal Mo;
a preparation method of a gate-surrounding transistor based on transition metal sulfide comprises the following steps:
step 1, preparing a substrate 101, depositing an insulating layer 102 (hafnium oxide) on the substrate 101, and performing magnetron sputtering on the insulating layer 102Sputtering of Mo metal, first producing MoTe of 1T metal phase by tellurium2And then 1T phase MoTe is grown by using a seed epitaxial growth method2MoTe telluride as a 2H semiconductor phase2The thin film is then repeatedly grown in this order to obtain the insulating layer 101 and the channel layer 103 (semiconductor phase MoTe)2Thin film) alternating layers, resulting in the structure shown in fig. 1;
step 2, etching the obtained laminated structure by adopting dry etching along the vertical direction of the substrate 101 to obtain an array-type laminated structure, and obtaining the structure shown in fig. 2;
step 3, defining the source electrode 105 and the drain electrode 104 area of each laminated structure by using an electron beam exposure process or a photoetching process, exposing the source electrode area and the drain electrode area by etching, and finally depositing metal electrodes as the source electrode 105, the drain electrode 104 and the channel layer 103 (semiconductor phase MoTe)2Thin film) to achieve one-dimensional contact, resulting in the structure shown in fig. 3;
step 4, removing the insulating layer 102 (which may be a whole insulating layer or a selected region etching, and only a part of the insulating layer) in the laminated structure by using a wet etching process to expose the channel layer 103 (semiconductor phase MoTe)2Thin film) to obtain the structure shown in fig. 4;
step 5, based on the step 4, adopting an atomic layer deposition method to deposit the channel layer 103 (semiconductor phase MoTe)2Film) and depositing a dielectric layer 106 on the surface of the substrate 101 and on the exposed drain surface inside the source electrode 105 and the drain electrode 104, resulting in the structure shown in fig. 5, wherein fig. 5a is a schematic structural view, fig. 5b is a cross-sectional view, and fig. 5c is a longitudinal-sectional view;
step 6, on the basis of step 5, masking the source 105 and the drain 104 with photoresist, and depositing Mo metal on the dielectric layer 106 as a gate 107 by using an atomic layer deposition method to form the transistor, as shown in fig. 6, wherein fig. 6a is a schematic structural diagram, fig. 6b is a cross-sectional view, and fig. 6c is a longitudinal-sectional view.
Claims (6)
1. A transition metal sulfide-based gate-around transistor, comprising a substrate, a stacked structure, a channel layer, a source, a drain, a dielectric layer, and a gate;
the stacked structure is composed of a channel layer stack surrounded by a grid, the channel layer and the grid are separated by a dielectric layer, and the drain, the source and the grid are also separated by the dielectric layer.
2. The transition metal sulfide-based gate-around transistor of claim 1, wherein the channel layer is a single or few semiconductor two-dimensional transition metal sulfide thin film, the dielectric layer is a high dielectric material, the gate is a metal or metallic two-dimensional transition metal sulfide thin film, and the substrate is an elemental insulator or a compound insulator; the source electrode and the drain electrode are made of metal materials.
3. A method for manufacturing a gate-all-around transistor based on a transition metal sulfide according to claim 2, comprising the steps of:
step 1, depositing an insulating layer on a substrate, depositing a channel layer, and then repeatedly depositing to obtain a laminated structure formed by the insulating layer and the channel layer alternately;
step 2, vertically etching the laminated structure in the step 1 by adopting a dry etching process to obtain an array-type laminated structure;
step 3, defining a source electrode area and a drain electrode area of each laminated structure, and then depositing the source electrode area and the drain electrode area;
step 4, removing the insulating layer in the laminated structure by using a wet etching process to expose the channel layer;
step 5, depositing a dielectric layer on the surface of the channel layer, the surface of the substrate and the surfaces of the source electrode, the drain electrode and the grid electrode in contact in the step 4;
and 6, depositing a grid electrode on the dielectric layer in the step 5 to form the transistor.
4. The method of claim 3, wherein the insulating layer is a high-k material.
5. The method according to claim 3, wherein the deposition is performed by any one of magnetron sputtering, chemical vapor deposition, atomic layer deposition, physical vapor deposition, thermal evaporation, electron beam evaporation, low pressure chemical vapor deposition, seed epitaxy, gas epitaxy, and molecular beam epitaxy.
6. The method according to claim 3, wherein the source and drain regions are defined in step 3 by: and performing exposure development on the front side and the rear side of the stacked structure in an array form by using an electron beam exposure technology or a photoetching technology, defining a source electrode region and a drain electrode region, removing the original stacked structure of the source electrode region and the drain electrode region by adopting reactive ion etching, and finally depositing the source electrode region and the drain electrode region in the source electrode region and the drain electrode region.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111486390.4A CN114203822A (en) | 2021-12-07 | 2021-12-07 | Gate surrounding transistor based on transition metal sulfide and preparation method |
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| CN202111486390.4A CN114203822A (en) | 2021-12-07 | 2021-12-07 | Gate surrounding transistor based on transition metal sulfide and preparation method |
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