CN110100303B - Preparation method of graphene transistor - Google Patents
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- CN110100303B CN110100303B CN201780072495.0A CN201780072495A CN110100303B CN 110100303 B CN110100303 B CN 110100303B CN 201780072495 A CN201780072495 A CN 201780072495A CN 110100303 B CN110100303 B CN 110100303B
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The embodiment of the application discloses a preparation method of a graphene transistor, which is used for simplifying the technical process of preparing the graphene transistor. The method comprises the following steps: covering a graphene layer on a substrate to form a first sample; preparing a source electrode and a drain electrode on the graphene layer in the first sample to form a second sample; depositing a first gate dielectric on the second sample to form a third sample, wherein the first gate dielectric covers the source electrode, the drain electrode and the graphene layer; performing self-aligned etching on the third sample to form a fourth sample, wherein the fourth sample comprises a substrate, a source electrode, a drain electrode, a channel region and a second gate dielectric, the channel region is a conductive region which is formed after the graphene layer is subjected to the self-aligned etching and is used for connecting the source electrode and the drain electrode, and the second gate dielectric is a gate dielectric which is formed after the first gate dielectric is subjected to the self-aligned etching and covers the source electrode, the drain electrode and the channel region; and preparing a gate electrode on the second gate dielectric in the fourth sample to form the graphene transistor.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a preparation method of a graphene transistor.
Background
Graphene (Graphene) is a two-dimensional crystal composed of carbon atoms on a single-layered honeycomb crystal lattice. Graphene has an electronic structure different from that of common three-dimensional graphite, and brings excellent electrical properties such as high electron mobility and high saturation velocity to the graphene. In addition, the radio frequency characteristics of graphene have been the research focus. In the current literature report, the maximum cut-off frequency of graphene exceeds 300GHz, and the highest oscillation frequency also reaches 200 GHz.
Due to the excellent electrical and radio frequency characteristics of graphene, graphene transistors have received much attention in the industry.
In the traditional process, a graphene transistor is prepared in the following way: etching graphene in a non-channel region on the graphene layer by adopting a photoetching mode, and then preparing a source electrode and a drain electrode at two ends of the channel region; and then depositing a gate dielectric between the source electrode and the drain electrode, stripping redundant gate dielectric in a non-channel region in a photoetching mode, and finally preparing a gate electrode on the gate dielectric between the source electrode and the drain electrode. The graphene transistor preparation method at least needs two steps of photoetching operation, and is complex in process and high in process cost.
In conclusion, the existing preparation method of the graphene transistor has the problem of complicated process.
Disclosure of Invention
The embodiment of the application provides a preparation method of a graphene transistor, which is used for simplifying the technical process of preparing the graphene transistor.
In a first aspect, an embodiment of the present application provides a method for manufacturing a graphene transistor, where the method includes the following steps: covering a graphene layer on a substrate to form a first sample; preparing a source electrode and a drain electrode on the graphene layer in the first sample to form a second sample; depositing a first gate dielectric on the second sample to form a third sample, wherein the first gate dielectric covers the source electrode, the drain electrode and the graphene layer; performing self-aligned etching on the third sample to form a fourth sample, wherein the fourth sample comprises a substrate, a source electrode, a drain electrode, a channel region and a second gate dielectric, the channel region is a conductive region which is formed after the graphene layer is subjected to the self-aligned etching and is used for connecting the source electrode and the drain electrode, and the second gate dielectric is a gate dielectric which is formed after the first gate dielectric is subjected to the self-aligned etching and covers the source electrode, the drain electrode and the channel region; and preparing a gate electrode on the second gate dielectric in the fourth sample to form the graphene transistor.
By adopting the scheme, the graphene layer and the first gate dielectric are prepared before the etching operation is carried out, so that the non-channel region in the graphene layer and the gate dielectric except the second gate dielectric in the first gate dielectric can be etched away simultaneously during the etching operation. Compared with the scheme that the graphene layer and the gate medium are required to be etched through two steps of photoetching operation in the preparation method of the graphene transistor provided by the prior art, the technical process of the preparation method of the graphene transistor is simplified, and the preparation efficiency is improved.
In one possible design, the self-aligned etching is performed on the third sample, which may be specifically implemented as follows: and carrying out self-aligned etching on the third sample by using a plasma cleaning machine, wherein etching gases are oxygen and argon.
Through experimental tests, the oxygen (O) is found2) The flow rate of the gas (Ar) is 10sccm, the flow rate of the argon (Ar) is 40sccm, the power of the plasma cleaning machine is 10W, and the etching effect is better when the etching time is 2 min. Of course, under the condition that parameters such as the flow rate of the etching gas, the power of the plasma cleaner, the etching time and the like are the same, the etching effect can also change along with different experimental environments. Therefore, specific values of these parameters are not limited in the embodiment of the present application as long as the etching effect can be achieved.
In one possible design, depositing the first gate dielectric on the second sample can be specifically achieved by:
in a first mode
And spin-coating a layer of positive photoresist on the second sample, transferring the pattern of the first gate dielectric to the second sample by adopting a photoetching mode, growing an aluminum metal thin layer by adopting an electron beam evaporation mode to serve as a seed layer of the first gate dielectric, and growing aluminum oxide by adopting an Atomic Layer Deposition (ALD) mode to serve as the first gate dielectric.
Mode two
Spin-coating a layer of positive photoresist on a second sample, transferring the pattern of the first gate dielectric to the second sample by adopting a photoetching mode, growing a yttrium metal thin layer by adopting an electron beam evaporation mode, and oxidizing the yttrium metal thin layer into yttrium oxide by adopting a hot baking mode to serve as the first gate dielectric.
It should be noted that the manner of depositing the first gate dielectric on the second sample includes, but is not limited to, the above two. Other implementations of depositing the gate dielectric (e.g., non-photolithographic implementations) are equally applicable in the embodiments of the present application.
In one possible design, the gate electrode is prepared on the second gate dielectric in the fourth sample, which can be specifically realized by the following two ways:
in a first mode
A gate electrode was prepared on the second gate dielectric in the fourth sample by electron beam evaporation of the metal and lift-off.
Mode two
A gate electrode was prepared on the second gate dielectric in the fourth sample by metal sputtering and lift-off.
Note that, the manner of preparing the gate electrode includes, but is not limited to, the above two. Other ways of preparing the gate electrode are equally applicable in the embodiments of the present application.
In one possible design, the source electrode and the drain electrode are prepared on the graphene layer in the first sample, which can be specifically realized by the following two ways:
in a first mode
And preparing a source electrode and a drain electrode on the graphene layer by adopting an electron beam evaporation metal and stripping mode.
Mode two
And preparing a source electrode and a drain electrode on the graphene layer by adopting a metal sputtering and stripping mode.
Likewise, the manner of preparing the source electrode and the drain electrode includes, but is not limited to, the above two. Other ways of preparing the gate electrode are equally applicable in the embodiments of the present application.
In one possible design, the electrode material of the source and drain electrodes consists of titanium and gold; alternatively, the electrode material of the source electrode and the drain electrode is composed of titanium, palladium, and gold.
In one possible design, a graphene layer is covered on a substrate, which can be specifically realized by the following steps: and covering the substrate with the graphene layer by adopting a micro-mechanical stripping or Chemical Vapor Deposition (CVD) mode.
In one possible design, the substrate is a sapphire substrate, or the substrate is composed of a high-resistance silicon layer and a hafnium oxide insulating layer formed on the high-resistance silicon layer by ALD.
Drawings
Fig. 1 is a schematic structural diagram of a graphene transistor according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of another graphene transistor provided in an embodiment of the present application;
fig. 3 is a schematic flow chart of a method for manufacturing a graphene transistor according to the prior art;
fig. 4 is a schematic flow chart of a method for manufacturing a first graphene transistor according to an embodiment of the present disclosure;
fig. 5 is a schematic flow chart of a method for manufacturing a second graphene transistor according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a graphene transistor manufactured according to an embodiment of the present application;
fig. 7 is a schematic diagram of a dc test result of a graphene transistor prepared according to an embodiment of the present application;
fig. 8 is a schematic diagram of an ac test result of a graphene transistor manufactured according to an embodiment of the present application;
fig. 9 is a schematic flow chart of a method for manufacturing a third graphene transistor according to an embodiment of the present disclosure;
fig. 10 is a schematic flow chart of a method for manufacturing a fourth graphene transistor according to an embodiment of the present application.
Detailed Description
Due to the excellent electrical and radio frequency characteristics of graphene, graphene transistors have received much attention in the industry. The graphene transistor may be classified into a plurality of types, for example, a top gate type graphene transistor and a non-top gate type graphene transistor according to a position of a gate electrode.
The structure of the non-top gate type graphene transistor may be as shown in fig. 1. The graphene transistor shown in fig. 1 includes a substrate, a gate dielectric, a gate electrode G, a graphene channel layer, a source electrode S, and a drain electrode D. Wherein, the gate dielectric is formed on the substrate; the grid electrode G is formed in the grid medium, so that the effect of insulation with the graphene channel layer, the source electrode S and the drain electrode D is achieved; the graphene channel layer is formed on the gate dielectric; the source electrode S and the drain electrode D are respectively located at two ends of the graphene channel layer and are electrically connected through the graphene channel layer.
The structure of the top gate type graphene transistor may be as shown in fig. 2. The graphene transistor shown in fig. 2 includes a substrate, a graphene channel layer, a gate dielectric, a gate electrode G, a source electrode S, and a drain electrode D. The graphene channel layer is formed on the substrate; the source electrode S and the drain electrode D are respectively positioned at two ends of the graphene channel layer and are electrically connected through the graphene channel layer; the grid medium covers the source electrode S, the graphene channel layer and the drain electrode D; the gate electrode G is formed over the gate dielectric.
Compared with a non-top gate type graphene transistor, the top gate type graphene transistor is smaller in thickness of a gate and stronger in gate control capability. The graphene transistor prepared in the embodiment of the application is a top gate type graphene transistor.
In the prior art, a method generally adopted when a top gate type graphene transistor (hereinafter referred to as "graphene transistor") is manufactured may be as shown in fig. 3.
1. Covering a graphene layer on a substrate;
wherein the graphene layer completely covers the substrate.
2. And etching the graphene layers on the two sides of the substrate by adopting a photoetching mode to form the graphene channel layer.
3. And preparing a source electrode S and a drain electrode D at two ends of the graphene channel layer.
4. And growing a gate dielectric on the sample formed in the step 3.
Wherein the gate dielectric completely covers the sample formed in step 3.
5. And (4) etching off the gate dielectrics on two sides of the sample formed in the step (4) by adopting a photoetching mode to form gate dielectric layers of the graphene transistor.
6. And (5) preparing a gate electrode G on the gate dielectric layer formed in the step (5), thereby preparing the graphene transistor.
It can be seen that, with the method shown in fig. 3, at least two steps of photolithography are required to prepare the graphene transistor. The process of the photolithography process is complicated, and for example, a mask substrate and a mask pattern need to be prepared for each photolithography. In addition, a photoresist is required in the photolithography process, and the residue of the photoresist increases the contact resistance of the graphene transistor. Therefore, the graphene transistor prepared by the preparation method shown in fig. 3 is complex in process and high in process cost.
The embodiment of the application provides a preparation method of a graphene transistor, which is used for simplifying the process of preparing the graphene transistor.
In the embodiments of the present application, a plurality means two or more. In addition, it should be understood that the terms first, second, etc. in the description of the embodiments of the present application are used for distinguishing between the descriptions and not for indicating or implying relative importance or order.
Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
Referring to fig. 4, a method for manufacturing a graphene transistor according to an embodiment of the present application is provided. The method comprises the following steps:
s401: a graphene layer is overlaid on a substrate to form a first sample.
In the embodiments of the present application, the specific type of the substrate is not limited. For example, the substrate may be a sapphire substrate, or may be a high-resistance silicon layer and hafnium oxide (HfO) formed on the high-resistance silicon layer by Atomic Layer Deposition (ALD)2) And an insulating layer.
Specifically, in S401, a graphene layer may be covered on the substrate by using a micro mechanical lift-off or Chemical Vapor Deposition (CVD).
S402: a source electrode and a drain electrode were prepared on the graphene layer in the first sample to form a second sample.
Specifically, in preparing the source electrode and the drain electrode, there are various ways that can be respectively employed. For example, a method of evaporating metal by electron beam and peeling off (Lift-off), or a method of sputtering metal and peeling off (Lift-off) is used.
Illustratively, a source electrode or a drain electrode may be prepared on the graphene layer in the first sample in a manner of electron beam evaporation metal + Lift-off (Lift-off). The metal evaporated by electron beam evaporation can be titanium (Ti) metal with a thickness of 1nm, palladium (Pd) metal with a thickness of 50nm, and gold (Au) metal with a thickness of 100 nm. That is, the electrode material of the source electrode or the drain electrode may be composed of titanium (Ti), palladium (Pd), and gold (Au).
Illustratively, a source electrode or a drain electrode may be prepared on the graphene layer in the first sample in a manner of sputtering metal + Lift-off (Lift-off). The metal sputtered by the sputtering metal method can be two metals, namely titanium (Ti) metal with the thickness of 15nm and gold (Au) metal with the thickness of 100 nm. That is, the electrode material of the source electrode or the drain electrode may be composed of titanium (Ti) and gold (Au).
In the embodiments of the present application, the source electrode and the drain electrode may be prepared in the same manner or in different manners. Of course, it is understood that the process is simplified when the source and drain electrodes are fabricated in the same manner.
S403: and depositing a first gate dielectric on the second sample to form a third sample.
Wherein the first gate dielectric covers the source electrode, the drain electrode and the graphene layer.
In particular implementations, there may be various ways to deposit the first gate dielectric on the second sample. Only two of these implementations are listed below.
In a first mode
Spin-coating a layer of positive photoresist on a second sample, transferring the pattern of the first gate dielectric to the second sample by adopting a photoetching mode, and growing an aluminum metal (Al) thin layer as the seed of the first gate dielectric by adopting an electron beam evaporation modeSub-layer, and growing aluminum oxide (Al) by ALD method2O3) As the first gate dielectric.
Illustratively, the thickness of the aluminum metal (Al) thin layer grown by electron beam evaporation may be 2nm, and the aluminum oxide (Al) grown by ALD2O3) May be 15nm and the operating temperature of ALD may be 90 ℃.
Mode two
Spin-coating a layer of positive photoresist on a second sample, transferring the pattern of the first gate dielectric to the second sample by photolithography, growing a yttrium (Y) metal thin layer by electron beam evaporation, and oxidizing the yttrium (Y) metal thin layer into yttrium oxide (Y) by baking2O3) As the first gate dielectric.
Illustratively, the thickness of the yttrium (Y) metal thin layer grown by electron beam evaporation can be 3nm, and the yttrium oxide (Y) obtained by thermal baking oxidation2O3) The thickness of (A) is 5nm, the operation temperature of the hot drying operation is 180 ℃, and the hot drying time is 10 min.
It should be noted that the manner of depositing the first gate dielectric on the second sample includes, but is not limited to, the above two. Other implementations of depositing the gate dielectric (e.g., non-photolithographic implementations) are equally applicable in the embodiments of the present application.
S404: and carrying out self-aligned etching on the third sample to form a fourth sample.
The fourth sample comprises a substrate, a source electrode, a drain electrode, a channel region and a second gate medium, wherein the channel region is a conductive region which is formed after the graphene layer is subjected to self-aligned etching and is used for connecting the source electrode and the drain electrode, and the second gate medium is a gate medium which is formed after the first gate medium is subjected to self-aligned etching and covers the source electrode, the drain electrode and the channel region.
Specifically, in S404, the self-aligned etching is performed on the third sample, which can be specifically implemented as follows: performing self-aligned etching on the third sample by using a plasma cleaner, wherein the etching gas is oxygen (O)2) And argon (Ar).
Through experimental tests, the oxygen is found to be(O2) The flow rate of the gas (Ar) is 10sccm, the flow rate of the argon (Ar) is 40sccm, the power of the plasma cleaning machine is 10W, and the etching effect is better when the etching time is 2 min. Of course, under the condition that parameters such as the flow rate of the etching gas, the power of the plasma cleaner, the etching time and the like are the same, the etching effect can also change along with different experimental environments. Therefore, specific values of these parameters are not limited in the embodiment of the present application as long as the etching effect can be achieved.
It should be noted that the self-aligned etching described in S404 may be understood as a photolithography method. Photolithography is a technique of optically transferring a mask pattern on a mask substrate onto a flat panel. In S404, the graphene layer in the non-channel region may be etched away by photolithography, and the gate dielectrics except for the second gate dielectric may be etched away from the first gate dielectric. And the second gate dielectric obtained after etching covers the source electrode, the channel region and the drain electrode, but does not completely cover the source electrode and the drain electrode. This is because: the second gate dielectric is a thin layer used for isolating the gate electrode from the channel region in the graphene transistor, so that the second gate dielectric needs to cover the channel region; at the same time, in order to avoid current leakage in the channel region, the second gate dielectric needs to completely cover the channel region, i.e., the second gate dielectric needs to cover the source electrode, the channel region and the drain electrode. In addition, for the graphene transistor prepared by the method shown in fig. 4, the source electrode and the drain electrode are external connection interfaces of the graphene transistor, and therefore the second gate dielectric may not completely cover the source electrode and the drain electrode.
In S404, the mask pattern used for etching the first gate dielectric is the mask pattern used in the existing photoetching mode; the etching of the graphene layer actually utilizes the second gate dielectric which is formed by etching the first gate dielectric and covers the graphene layer as a self-aligned mask. That is to say, in the one-step photolithography operation in S404, the mask pattern and the second gate dielectric may be respectively used to implement the etching operation on the first gate dielectric and the graphene layer, and compared with a scheme in the prior art that the etching operation on the gate dielectric and the graphene layer needs to be implemented through two-step photolithography operations (for example, in the method shown in fig. 3, the etching operation on the graphene layer is implemented through the photolithography operation in step 2, and then after the source electrode, the drain electrode and the gate dielectric are prepared, the etching operation on the gate dielectric is implemented through the photolithography operation in step 5), the process is simplified by using the method shown in fig. 4.
It is also to be noted that oxygen (O) is used2) Self-aligned etching with argon (Ar) may be understood as one of the dry etching methods. When S404 is executed, not only the dry etching manner described above but also a wet etching manner may be adopted, which is not limited in this embodiment. The graphene layer and the first gate dielectric can be etched simultaneously in one etching operation.
S405: and preparing a gate electrode on the second gate dielectric in the fourth sample to form the graphene transistor.
Specifically, in the preparation of the gate electrode, there may be employed various means, for example, a means of evaporating a metal by an electron beam and peeling off (Lift-off), or a means of sputtering a metal and peeling off (Lift-off).
Illustratively, a gate electrode may be prepared on the second gate dielectric in the fourth sample by electron beam evaporation metal + Lift-off (Lift-off). Wherein, the metal evaporated by the electron beam evaporation metal method can be titanium (Ti) metal with the thickness of 1nm and gold (Au) metal with the thickness of 20 nm.
Illustratively, a sputtered metal + Lift-off (Lift-off) pattern may be used to prepare the gate electrode on the second gate dielectric in the fourth sample. The metal sputtered by the sputtering metal method can be titanium (Ti) metal with the thickness of 15nm and gold (Au) metal with the thickness of 100 nm.
In order to facilitate understanding of the process of the method for manufacturing a graphene transistor shown in fig. 4, an embodiment of the present application further provides another method for manufacturing a graphene transistor, as shown in fig. 5. The method of fig. 5 may be considered as another form of the method of fig. 4. The structure of the sample (or finished product) formed after the respective step operations (S401 to S405) illustrated in fig. 4 can be more clearly seen by the method illustrated in fig. 5.
Here, by performing S401 of covering a graphene layer on a substrate, a first sample illustrated in fig. 5 may be obtained. As can be seen in fig. 5, the first sample comprised a substrate and a graphene layer.
By preparing the source electrode S and the drain electrode D on the graphene layer by performing S402, a second sample shown in fig. 5 may be obtained. The second sample comprises a substrate, a graphene layer, a source electrode S and a drain electrode D.
A third sample shown in fig. 5 may be obtained by performing S403 to deposit a first gate dielectric on the second sample. The third sample contained a substrate, a graphene layer, a source electrode S, a drain electrode D, and a first gate dielectric.
By performing self-aligned etching on the third sample by performing S404, a fourth sample shown in fig. 5 can be obtained. The fourth sample comprises a substrate, a source electrode S, a drain electrode D, a channel region formed by the graphene layer after self-aligned etching and a second gate dielectric formed by the first gate dielectric after self-aligned etching.
By performing S405 to prepare the gate electrode G on the second gate dielectric in the fourth sample, a graphene transistor (finished product) may be formed. The graphene transistor (finished product) comprises a substrate, a source electrode S, a drain electrode D, a channel region formed by self-aligned etching of a graphene layer, a second gate dielectric formed by self-aligned etching of a first gate dielectric, and a gate electrode G.
In fig. 5, the gate dielectric shown in the third sample is the first gate dielectric, and the gate dielectric shown in the fourth sample and the graphene transistor (finished product) is the second gate dielectric. The second gate dielectric is obtained by etching the first gate dielectric. Since the material composition of the first gate dielectric and the second gate dielectric are the same, they are identified by legends of the same color in fig. 5.
It should be noted that, in fig. 5, the graphene shown in the first sample, the second sample, and the third sample is referred to as a "graphene layer" in the method shown in fig. 4, and the graphene shown in the fourth sample and the graphene transistor (finished product) is referred to as a "channel region" in the method shown in fig. 4. Since the material composition of the "graphene layer" and the "channel region" are the same, they are identified in fig. 5 by a legend of the same color. In addition, in the fourth sample, the graphene etched away is a "non-channel region" compared to the third sample.
By adopting the preparation method of the graphene transistor provided by the embodiment of the application, the graphene layer and the first gate dielectric are prepared before the etching operation is carried out, so that the non-channel region in the graphene layer and the gate dielectric except the second gate dielectric in the first gate dielectric can be etched away simultaneously during the etching operation. Compared with the scheme that the graphene layer and the gate dielectric are required to be etched through two steps of photoetching operation in the preparation method of the graphene transistor provided by the prior art, the technical process of the preparation method of the graphene transistor provided by the embodiment of the application is simplified, and the preparation efficiency is improved.
In addition, the photoresist residue phenomenon may occur in the photolithography operation, thereby increasing the contact resistance of the graphene transistor and affecting the performance of the graphene transistor. Compared with the scheme provided by the prior art, the preparation method of the graphene transistor provided by the embodiment of the application reduces the times of photoetching operation, so that less photoresist remains, and the prepared graphene transistor has better performance.
Referring to fig. 6, a graphene transistor manufactured by the method for manufacturing a graphene transistor according to the embodiment of the present application is shown. As can be seen from fig. 6, the graphene layer in the non-channel region is etched cleanly, and the graphene in the channel region is effectively and sufficiently protected while the etching process of the graphene transistor is well completed by the method for preparing the graphene transistor provided by the embodiment of the present application.
The direct current test and the alternating current test of the graphene transistor shown in fig. 6 can obtain a schematic diagram of a direct current test result shown in fig. 7 and a schematic diagram of an alternating current test result shown in fig. 8 (both the gate lengths of the graphene transistors used for the test in fig. 7 and 8 are 160 nm).
In the direct current test, the normalized current and transconductance of the graphene transistor are mainly tested. Wherein, transconductance is the variation of drain current and gateThe ratio of the source voltage variation is used for expressing the control capability of the grid source voltage to the drain current; the normalized current is a ratio of a current value flowing through the graphene transistor to a channel width of the graphene transistor, and is used for measuring performances of graphene transistors with different sizes. In FIG. 7, IdDenotes the current between source and drain, VtgDenotes the gate voltage, VdDenotes the voltage between source and drain, gmRepresents transconductance, LgIndicating the gate length. From the dc test results shown in fig. 7, it can be seen that the maximum normalized current of the graphene transistor shown in fig. 6 can reach 1200mA/mm, and the maximum transconductance reaches 250mS/mm, which indicates that the graphene transistor shown in fig. 6 has higher gate efficiency.
In the ac test, the cutoff frequency and the maximum oscillation frequency of the graphene transistor are mainly tested. The cutoff frequency and the maximum oscillation frequency represent the high frequency performance of the graphene transistor. In FIG. 8, H21Representing the forward current gain, U1/2Representing the Mason single-sided power gain, fTDenotes the cut-off frequency, fmaxRepresenting the maximum oscillation frequency, LgThe gate length is indicated, the test result labeled "Before _ demombedding" represents the test result Before de-embedding, and the test result labeled "After _ demombedding" represents the test result After de-embedding. As can be seen from the ac test result shown in fig. 8, the cut-off frequency and the maximum oscillation frequency of the graphene transistor shown in fig. 6 before de-embedding are both 22GHz, and the cut-off frequency and the maximum oscillation frequency of the graphene transistor shown in fig. 6 after de-embedding are 204GHz and 61GHz, respectively.
Based on the above embodiments, the embodiments of the present application further provide two other methods for manufacturing a graphene transistor. The two methods for manufacturing the graphene transistor can be regarded as a specific example of the method shown in fig. 4 or fig. 5. These two methods are described separately below.
Fig. 9 is a schematic flow chart of the first method. The method shown in fig. 9 comprises the following steps:
1. HfO with thickness of 50nm formed on high-resistance silicon substrate by ALD method2And the insulating layer is used as a substrate.
2. The first sample was formed by transferring graphene onto a substrate using a CVD process.
3. Preparing a source electrode and a drain electrode on the first sample by using an electron beam evaporation metal + Lift-off method to form a second sample, wherein the electrode materials are Ti, Pd and Au, and the thicknesses of the electrode materials are 1nm, 50nm and 100nm respectively.
4. And spin-coating a positive photoresist layer on the second sample, transferring the first gate dielectric pattern onto the substrate by using a photoetching mode, then growing Al with the thickness of 2nm by using electron beam evaporation as a seed layer of the first gate dielectric, and then growing Al2O3 with the thickness of 15nm as the first gate dielectric by using atomic layer deposition at the temperature of 90 ℃ to form a third sample.
5. On the third sample, self-aligned etching is carried out on the graphene in the non-channel region by using a plasma cleaning machine to form a fourth sample, and the etching gases are respectively O of 10sccm2And 40sccm of Ar, the power of the plasma cleaner is about 10W, and the etching time is 2 min.
6. On the fourth sample, a top gate electrode was prepared using a method of electron beam evaporation of Ti metal and Au metal (thickness of 1nm and 20nm, respectively) + Lift-off, forming a top gate type graphene transistor.
It should be noted that the method shown in fig. 9 can be regarded as a specific example of the method shown in fig. 4 or fig. 5. The implementation manner not described in detail in the method shown in fig. 9 can be referred to the related description in the method shown in fig. 4 or fig. 5.
Method two
Fig. 10 is a schematic flow chart of the second method. The method shown in fig. 10 comprises the following steps:
1. the graphene is transferred to a sapphire substrate using a micromechanical lift-off method to form a first sample.
2. Preparing a source electrode and a drain electrode on the first sample by using a metal sputtering + Lift-off method to form a second sample, wherein the electrode materials are Ti and Au, and the thicknesses of the electrode materials are 15nm and 100nm respectively.
3. Spin coating a positive photoresist on the second sample, transferring the first gate dielectric pattern to the substrate by photolithography, and electrically etchingGrowing a 3nm Y metal thin layer by using electron beam evaporation, and then heating and baking at 180 ℃ for 10 minutes to oxidize the Y metal thin layer into 5nm Y2O3As the first gate dielectric, a third sample was formed.
4. On the third sample, self-aligned etching is carried out on the graphene in the non-channel region by using a plasma cleaning machine to form a fourth sample, and the etching gases are respectively O of 10sccm2And 40sccm of Ar, the power of the plasma cleaner is about 10W, and the etching time is 2 min.
5. On the fourth sample, a top gate electrode was prepared using a method of sputtering Ti metal and Au metal (thickness of 15nm and 100nm, respectively) + Lift-off, forming a top gate type graphene transistor.
It should be noted that the method shown in fig. 10 can be regarded as a specific example of the method shown in fig. 4 or fig. 5. The implementation manner not described in detail in the method shown in fig. 10 can be referred to the related description in the method shown in fig. 4 or fig. 5.
In summary, the preparation method of the graphene transistor provided by the embodiment of the application can simplify the process of preparing the graphene transistor.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to encompass such modifications and variations.
Claims (8)
1. A preparation method of a graphene transistor is characterized by comprising the following steps:
covering a graphene layer on a substrate to form a first sample;
preparing a source electrode and a drain electrode on the graphene layer in the first sample to form a second sample;
depositing a first gate dielectric on the second sample to form a third sample, wherein the first gate dielectric covers the source electrode, the drain electrode and the graphene layer;
performing self-aligned etching on the third sample to form a fourth sample, wherein the fourth sample comprises the substrate, the source electrode, the drain electrode, a channel region and a second gate dielectric, the channel region is a conductive region formed by the graphene layer after the self-aligned etching and used for connecting the source electrode and the drain electrode, and the second gate dielectric is a gate dielectric formed by the first gate dielectric after the self-aligned etching and covering the source electrode, the drain electrode and the channel region;
and preparing a gate electrode on the second gate dielectric in the fourth sample to form the graphene transistor.
2. The method of claim 1, wherein self-aligned etching the third sample comprises:
and carrying out self-aligned etching on the third sample by using a plasma cleaning machine, wherein etching gases are oxygen and argon.
3. The method of claim 1, wherein depositing a first gate dielectric on the second sample comprises:
spin-coating a layer of positive photoresist on the second sample, transferring the pattern of the first gate dielectric onto the second sample by adopting a photoetching mode, growing an aluminum metal thin layer by adopting an electron beam evaporation mode to serve as a seed layer of the first gate dielectric, and growing aluminum oxide by adopting an Atomic Layer Deposition (ALD) mode to serve as the first gate dielectric; or
Spin-coating a layer of positive photoresist on the second sample, transferring the pattern of the first gate dielectric onto the second sample by adopting a photoetching mode, growing a yttrium metal thin layer by adopting an electron beam evaporation mode, and oxidizing the yttrium metal thin layer into yttrium oxide serving as the first gate dielectric by adopting a hot baking mode.
4. The method of any of claims 1 to 3, wherein preparing a gate electrode on the second gate dielectric in the fourth sample comprises:
preparing the grid electrode on the second grid medium in the fourth sample by adopting an electron beam metal evaporation and stripping mode; or
And preparing the gate electrode on the second gate dielectric in the fourth sample by adopting a metal sputtering and stripping mode.
5. The method of any one of claims 1 to 3, wherein preparing a source electrode and a drain electrode on the graphene layer in the first sample comprises:
preparing the source electrode and the drain electrode on the graphene layer by adopting an electron beam metal evaporation and stripping mode; or
And preparing the source electrode and the drain electrode on the graphene layer by adopting a metal sputtering and stripping mode.
6. The method according to any one of claims 1 to 3, wherein an electrode material of the source electrode and the drain electrode is composed of titanium and gold; alternatively, the first and second electrodes may be,
the electrode material of the source electrode and the drain electrode is composed of titanium, palladium and gold.
7. A method according to any one of claims 1 to 3, wherein overlaying a graphene layer on a substrate comprises:
and covering the substrate with a graphene layer by adopting a micro-mechanical stripping or Chemical Vapor Deposition (CVD) mode.
8. The method according to any one of claims 1 to 3, wherein the substrate is a sapphire substrate, or the substrate is composed of a high-resistance silicon layer and a hafnium oxide insulating layer formed on the high-resistance silicon layer by ALD.
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| JP5135825B2 (en) * | 2007-02-21 | 2013-02-06 | 富士通株式会社 | Graphene transistor and manufacturing method thereof |
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| US8895352B2 (en) * | 2009-06-02 | 2014-11-25 | International Business Machines Corporation | Method to improve nucleation of materials on graphene and carbon nanotubes |
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| JP5135825B2 (en) * | 2007-02-21 | 2013-02-06 | 富士通株式会社 | Graphene transistor and manufacturing method thereof |
| CN103227103A (en) * | 2012-01-26 | 2013-07-31 | 三星电子株式会社 | Graphene device and method of manufacturing the same |
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