CN110085711A - Light emitting diode and forming method thereof - Google Patents
Light emitting diode and forming method thereof Download PDFInfo
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- CN110085711A CN110085711A CN201910359917.3A CN201910359917A CN110085711A CN 110085711 A CN110085711 A CN 110085711A CN 201910359917 A CN201910359917 A CN 201910359917A CN 110085711 A CN110085711 A CN 110085711A
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- indium gallium
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- 238000000034 method Methods 0.000 title claims abstract description 61
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 89
- 239000004065 semiconductor Substances 0.000 claims abstract description 87
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 86
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 claims abstract description 60
- 229910052749 magnesium Inorganic materials 0.000 claims abstract description 54
- 239000011777 magnesium Substances 0.000 claims abstract description 54
- -1 magnesium nitride Chemical class 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 29
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 133
- 229910052757 nitrogen Inorganic materials 0.000 claims description 66
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 49
- 229910052733 gallium Inorganic materials 0.000 claims description 49
- 229910052738 indium Inorganic materials 0.000 claims description 42
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 42
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 28
- 238000005229 chemical vapour deposition Methods 0.000 claims description 23
- 239000001257 hydrogen Substances 0.000 claims description 18
- 229910052739 hydrogen Inorganic materials 0.000 claims description 18
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 15
- 239000007789 gas Substances 0.000 claims description 15
- 229910021529 ammonia Inorganic materials 0.000 claims description 13
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 9
- 238000002360 preparation method Methods 0.000 claims description 6
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 claims description 5
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 claims description 5
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 claims description 5
- AUCDRFABNLOFRE-UHFFFAOYSA-N alumane;indium Chemical compound [AlH3].[In] AUCDRFABNLOFRE-UHFFFAOYSA-N 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 150000002431 hydrogen Chemical class 0.000 claims description 3
- 229910017083 AlN Inorganic materials 0.000 claims 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims 1
- 239000007792 gaseous phase Substances 0.000 claims 1
- 238000004062 sedimentation Methods 0.000 claims 1
- 230000006798 recombination Effects 0.000 abstract description 5
- 238000005215 recombination Methods 0.000 abstract description 5
- 238000006243 chemical reaction Methods 0.000 description 22
- 239000012495 reaction gas Substances 0.000 description 10
- 150000001875 compounds Chemical class 0.000 description 9
- 238000005286 illumination Methods 0.000 description 9
- 230000009471 action Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 230000005684 electric field Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 239000000203 mixture Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 238000000197 pyrolysis Methods 0.000 description 5
- 239000007787 solid Substances 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- MHYQBXJRURFKIN-UHFFFAOYSA-N C1(C=CC=C1)[Mg] Chemical compound C1(C=CC=C1)[Mg] MHYQBXJRURFKIN-UHFFFAOYSA-N 0.000 description 1
- 229910019080 Mg-H Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The present invention relates to a kind of light emitting diodes and forming method thereof.A kind of forming method of light emitting diode, comprising: provide substrate, the substrate has the first surface and second surface being oppositely arranged；N type semiconductor layer is prepared, the first surface is covered；Multi-quantum pit structure layer is prepared, the n type semiconductor layer is covered；Hole deriving structure layer is prepared, the multi-quantum pit structure layer is covered, the hole deriving structure layer includes p-type aluminum indium gallium nitride layer and magnesium nitride layer, and the magnesium nitride layer covers the p-type aluminum indium gallium nitride layer；P type semiconductor layer is prepared, the hole deriving structure layer is covered.The forming method is formed by light emitting diode, effectively improves number of cavities and hole concentration, to promote the recombination probability in electronics and hole, promotes the luminous efficiency of light emitting diode.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of light emitting diode and forming method thereof.
Background technique
Light emitting diode (LED, Light Emitting Diode) is a kind of solid-state semiconductor device that can be luminous, wide
It is general to be applied to the illumination light-emittings fields such as indicator light and display screen.
In traditional technology, the core of light emitting diode is generally PN junction.Under electric field action, constitute in the P-type layer of PN junction
Hole and constitute PN junction N-type layer in electronics be compounded to form visible light.
Applicant has found during realizing traditional technology: traditional light emitting diode, the injection of P-type layer side hole
Efficiency is lower, poor so as to cause luminous efficiency.
Summary of the invention
Based on this, it is necessary to it is low for light emitting diode hole injection efficiency present in traditional technology, so as to cause hair
The problem of light efficiency difference provides a kind of light emitting diode and forming method thereof.
A kind of forming method of light emitting diode, comprising: provide substrate, the substrate has the first surface being oppositely arranged
And second surface；N type semiconductor layer is prepared, the first surface is covered；Multi-quantum pit structure layer is prepared, the N-type half is covered
Conductor layer；Hole deriving structure layer is prepared, covers the multi-quantum pit structure layer, the hole deriving structure layer includes p-type nitrogen
Change aluminium indium gallium layer and magnesium nitride layer, the magnesium nitride layer covers the p-type aluminum indium gallium nitride layer；P type semiconductor layer is prepared, is covered
The hole deriving structure layer.
The forming method of above-mentioned light emitting diode is formed by light emitting diode, and hole deriving structure layer includes that stacking is set
The p-type aluminum indium gallium nitride layer and magnesium nitride layer set, can effectively improve number of cavities and hole concentration, to promote electronics and sky
The recombination probability in cave promotes the luminous efficiency of light emitting diode.
A kind of light emitting diode is based on any one above-mentioned forming method as described in the examples, which is characterized in that packet
It includes: substrate；N type semiconductor layer covers the substrate；Multi-quantum pit structure layer covers the n type semiconductor layer；It draws in hole
Structure sheaf, covers the multi-quantum pit structure layer, and the hole deriving structure layer includes p-type aluminum indium gallium nitride layer and magnesium nitride
Layer, the magnesium nitride layer cover the p-type aluminum indium gallium nitride layer；P type semiconductor layer covers the hole deriving structure layer.
Detailed description of the invention
Fig. 1 is the flow diagram of light emitting diode forming method in the application one embodiment.
Fig. 2 is the hierarchical structure schematic diagram of light emitting diode in the application one embodiment.
Fig. 3 is the flow diagram of light emitting diode forming method in another embodiment of the application.
The hierarchical structure schematic diagram of light emitting diode in another embodiment of Fig. 4 the application.
Fig. 5 is the hierarchical structure schematic diagram of stress release layer in the application one embodiment.
Fig. 6 is the hierarchical structure schematic diagram of multi-quantum pit structure layer in the application one embodiment.
Fig. 7 is the hierarchical structure schematic diagram of hole deriving structure layer in the application one embodiment.
Wherein, meaning representated by each drawing reference numeral is respectively as follows:
10, light emitting diode；
100, substrate；
102, first surface；
104, second surface；
200, n type semiconductor layer；
300, multi-quantum pit structure layer；
310, multiple quantum well layer；
312, indium gallium nitrogen layer；
314, gallium nitride layer；
400, hole deriving structure layer；
410, layer is drawn in hole；
412, p-type aluminum indium gallium nitride layer；
414, magnesium nitride layer；
500, p type semiconductor layer；
600, strain relief layer；
610, stress release layer；
612, indium gallium nitrogen layer；
614, low-doped gallium nitride layer.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.Many details are explained in the following description in order to fully understand this hair
It is bright.But the invention can be embodied in many other ways as described herein, those skilled in the art can be not
Similar improvement is done in the case where violating intension of the present invention, therefore the present invention is not limited by the specific embodiments disclosed below.
The application is low for the side the P hole injection efficiency of light emitting diode present in traditional technology, to influence to shine
The problem of LED lighting efficiency, provides the light emitting diode and its shape of a kind of quantity that can promote the hole compound with electronics
At method.
As depicted in figs. 1 and 2, a kind of forming method of light emitting diode, includes the following steps:
S100, provides substrate 100, and the substrate 100 has the first surface 102 and second surface 104 being oppositely arranged.
Specifically, providing a substrate 100 for being used to form the light emitting diode 10, the substrate 100 can be blue treasured
Stone lining bottom or other kinds of substrate.The substrate 100 has opposite first surface 102 and second surface 104.
S200 prepares n type semiconductor layer 200, covers the first surface 102.
Specifically, preparation covers the n type semiconductor layer 200 on the surface on a surface of the substrate 100.The N
Type semiconductor layer 200 can be prepared in any one of the first surface 102 and the second surface 104.In this implementation
In example, the n type semiconductor layer 200 is prepared on the first surface 102 of the substrate 100, and covers first table
Face 102.The n type semiconductor layer 200 covers the first surface 102 of the substrate 100, to generate electronics under electric field action.
S300 prepares multi-quantum pit structure layer 300, covers the n type semiconductor layer 200.
Specifically, preparing multi-quantum pit structure layer on surface of the n type semiconductor layer 200 far from the substrate 100
300.The multi-quantum pit structure layer 300 covers the n type semiconductor layer 200, for improving the recombination rate of electrons and holes.Institute
Stating multi-quantum pit structure layer 300 generally may include that staggered Quantum Well and quantum base is laminated.
S400 prepares hole deriving structure layer 400, covers the multi-quantum pit structure layer 300.The hole deriving structure
Layer 400 includes the p-type aluminum indium gallium nitride layer 412 and magnesium nitride layer 414 being stacked.The magnesium nitride layer 414 covers the p-type
Aluminum indium gallium nitride layer 412.
Specifically, preparing hole on surface of the multi-quantum pit structure layer 300 far from the n type semiconductor layer 200
Deriving structure layer 400.The hole deriving structure layer 400 covers the multi-quantum pit structure layer 300, for drawing hole, with
Increase number of cavities.The hole deriving structure layer 400 may include the p-type aluminum indium gallium nitride layer 412 and magnesium nitride layer of stacking
414.Wherein, the p-type aluminum indium gallium nitride layer 412 is close to the multi-quantum pit structure layer 300；The magnesium nitride layer 414 is separate
The multi-quantum pit structure layer 300, and cover the p-type aluminum indium gallium nitride layer 412.
S500 prepares p type semiconductor layer 500, covers the hole deriving structure layer 400.
Specifically, preparing P on the surface of the hole deriving structure layer 400 far from the multi-quantum pit structure layer 300
Type semiconductor layer 500.The p type semiconductor layer 500 covers the hole deriving structure layer 400, to generate under electric field action
Hole.
When being formed by the energization of light emitting diode 10 using this method, the n type semiconductor layer 200 generates electronics and in electricity
It is mobile to 300 direction of multi-quantum pit structure layer under field action；The p type semiconductor layer 500 generates hole and makees in electric field
With lower to 300 direction of multi-quantum pit structure layer movement.Meanwhile the hole deriving structure layer can produce a large amount of holes simultaneously
It is mobile to 300 direction of multi-quantum pit structure layer, to increase the quantity with the compound hole of electronics.This method is formed by
The light emitting diode 10 generates hole by the p-type aluminum indium gallium nitride layer 412 and the magnesium nitride layer 414, can be promoted
The quantity and density in compound hole with electronics, and then the recombination probability in hole and electronics is promoted, promote the light emitting diode
10 illumination effect.
In one embodiment, the forming method of the light emitting diode, the n type semiconductor layer 200 can be N-type
Gallium nitride (GaN) layer, i.e., the material of the described n type semiconductor layer 200 are the gallium nitride doped with N-type impurity.
Further, the thickness range of the n type semiconductor layer 200 can be 2 μm to 3 μm.Specifically, this is described
The thickness of n type semiconductor layer 200 can be 2 μm, be also possible to 3 μm, can also be 2.5 μm.
In one embodiment, as shown in figure 3, the forming method of the light emitting diode, is preparing multi-quantum pit structure
Layer 300, further includes following steps before covering the n type semiconductor layer 200:
S600 prepares strain relief layer 600, covers the n type semiconductor layer 200, the strain relief layer
600 are set between the multi-quantum pit structure layer 300 and the n type semiconductor layer 200.
Specifically, after preparing n type semiconductor layer 200, it, can also be in N-type before preparing multi-quantum pit structure layer 300
A strain relief layer 600 is prepared between semiconductor layer 200 and multi-quantum pit structure layer 300.The strain relief layer
The 600 covering n type semiconductor layers 200.The strain relief layer 600 is used for the n type semiconductor layer 200 and described
Lattice mismatch between multi-quantum pit structure layer 300 is buffered, while making the n type semiconductor layer 200 and the Multiple-quantum
The mismatch stress that well structure layer 300 generates is released.
The forming method of the light emitting diode is formed by light emitting diode 10, is also equipped with strain relief layer
600, the stress release ability and lattice mismatch buffer capacity of light emitting diode 10 can be improved, and then promote light emitting diode 10
Illumination effect.
Further, the step S600, can specifically include:
S610 prepares indium gallium nitrogen layer 612 using chemical vapour deposition technique in 850 DEG C to 950 DEG C of growth temperature range,
Cover the n type semiconductor layer 200.
Specifically, preparation covers the indium gallium nitrogen (In of n type semiconductor layer 200 on n type semiconductor layer 200xGa1-xN) layer
612.The indium gallium nitrogen layer 612 can be prepared in 850 DEG C to 950 DEG C of growth temperature range using chemical vapour deposition technique,
It, which specifically may is that, makes the reaction gas comprising indium, gallium and nitrogen to the n type semiconductor layer 200 far from the substrate 100
Diffusion into the surface；The reaction gas is set to be adsorbed in the surface of the n type semiconductor layer 200；Use pyrolysis or/and change
It learns synthetic reaction and forms solid indium gallium nitrogen layer 612 on the surface of the n type semiconductor layer 200.Wherein, the chemical vapor deposition
The temperature range of the reaction chamber of area method is 850 DEG C to 950 DEG C.The growth temperature of the i.e. described indium gallium nitrogen layer 612 can be 850 DEG C,
It is also possible to 950 DEG C, can also be 900 DEG C.
S620 reuses chemical vapour deposition technique and prepares low-doped gallium nitride layer 614, covers the indium gallium nitrogen layer 612,
To form a stress release layer 610.
Specifically, preparing low-doped nitrogen on the surface of the indium gallium nitrogen layer 612 far from the n type semiconductor layer 200
Change gallium (GaN) layer 614.The low-doped gallium nitride layer 614 can be the gallium nitride layer of low-mix silicon (Si).It is described low-doped
Gallium nitride layer 614 can be prepared in 850 DEG C to 950 DEG C of growth temperature range using chemical vapour deposition technique, specifically may be used
To be: making the reaction gas comprising silicon, gallium and nitrogen to the table of the indium gallium nitrogen layer 612 far from the n type semiconductor layer 200
Face diffusion；The reaction gas is set to be adsorbed in the surface of the indium gallium nitrogen layer 612；Use pyrolysis or/and chemical synthesis
Reaction forms solid low-doped gallium nitride layer 614 on the surface of the indium gallium nitrogen layer 612.Wherein, the chemical vapor deposition
The temperature range of the reaction chamber of area method is 850 DEG C to 950 DEG C.The growth temperature of the i.e. described low-doped gallium nitride layer 614 can be with
It is 850 DEG C, is also possible to 950 DEG C, can also be 900 DEG C.
S630 repeats the above steps 3 to 9 times, to prepare the stress release layer 610 of 3 to 9 stackings, answers described in composition
Power discharges structure sheaf 600.
Specifically, an indium gallium nitrogen layer 612 and a low-doped gallium nitride layer 614 constitute a stress release layer 610.
In general, the stress release layer 610 for constituting the strain relief layer 600 can be 3 to 9 layers.The i.e. described stress
Release structure sheaf 600 can be to be formed by 3 610 stacking cycles of stress release layer, is also possible to be released by 9 stress
It puts 610 stacking cycles of layer to be formed, can also be and formed by 6 610 stacking cycles of stress release layer.Therefore, it repeats above-mentioned
Step S610 and S620 tri- to nine times, three to nine stress release layers 610 are formed, that is, may make up strain relief layer 600.Packet
The light emitting diode 10 for including strain relief layer 600 can be as shown in Figure 4.In embodiment shown in Fig. 4, the stress release
Structure sheaf 600 includes the stress release layer 610 of three stackings.Fig. 5 shows the step S610 and step S620 is formed
A stress release layer 610 structure chart.
The forming method of above-mentioned light emitting diode is formed by the light emitting diode 10, by releasing the composition stress
The stress release layer 610 for putting structure sheaf 600 carries out quantity restriction, and the stress that the light emitting diode 10 both can be improved is released
Exoergic power, but can to avoid the blocked up normal work for influencing the light emitting diode 10 of the strain relief layer 600, thus
Promote the illumination effect of the light emitting diode 10.
In one embodiment, in the forming method of the light emitting diode, the step S300 be can specifically include:
S310 prepares indium gallium nitrogen layer 312 using chemical vapour deposition technique in 780 DEG C to 830 DEG C of growth temperature range,
Cover the n type semiconductor layer 200.
Specifically, when the light emitting diode 10 does not include strain relief layer 600, it can be in n type semiconductor layer
Multi-quantum pit structure layer 300 is prepared on 200.At this point, preparing indium gallium nitrogen (In on n type semiconductor layer 200xGa1-xN,0.22≥x
>=0.20) layer 312, indium gallium nitrogen layer 312 cover the n type semiconductor layer 200.The indium gallium nitrogen layer 312 can be arrived at 780 DEG C
It is prepared in 830 DEG C of growth temperature range using chemical vapour deposition technique, specifically may is that makes comprising indium, gallium and nitrogen
Diffusion into the surface of the reaction gas to the n type semiconductor layer 200 far from the substrate 100；It is adsorbed in the reaction gas
The surface of the n type semiconductor layer 200；Using pyrolysis or/and chemosynthesis reaction in the n type semiconductor layer 200
Surface form solid indium gallium nitrogen layer 312.Wherein, the temperature range of the reaction chamber of the chemical vapour deposition technique is 780 DEG C
To 830 DEG C.The growth temperature of the i.e. described indium gallium nitrogen layer 312 can be 780 DEG C, is also possible to 830 DEG C, can also be 805 DEG C.
When the light emitting diode 10 includes strain relief layer 600, can be made on strain relief layer 600
Standby multi-quantum pit structure layer 300.At this point, preparing indium gallium nitrogen layer 312 on strain relief layer 600, indium gallium nitrogen layer 312 is covered
The strain relief layer 600.The indium gallium nitrogen layer 312 can use change in 780 DEG C to 830 DEG C of growth temperature range
Vapour deposition process preparation is learned, specifically may is that makes the reaction gas comprising indium, gallium and nitrogen to the strain relief
600 diffusion into the surface far from the substrate 100 of layer；The reaction gas is set to be adsorbed in the table of the strain relief layer 600
Face；Solid indium gallium is formed on the surface of the strain relief layer 600 using pyrolysis or/and chemosynthesis reaction
Nitrogen layer 312.Wherein, the temperature range of the reaction chamber of the chemical vapour deposition technique is 780 DEG C to 830 DEG C.The i.e. described indium gallium nitrogen
The growth temperature of layer 312 can be 780 DEG C, is also possible to 830 DEG C, can also be 805 DEG C.
S320 adjusts growth temperature range to 850 DEG C to 950 DEG C, prepares gallium nitride layer using chemical vapour deposition technique
314, the indium gallium nitrogen layer 312 is covered, to form a multiple quantum well layer 310.
Specifically, preparing gallium nitride (GaN) on the surface of the indium gallium nitrogen layer 312 far from the n type semiconductor layer 200
Layer 314.The gallium nitride layer 314 can use chemical vapour deposition technique system in 850 DEG C to 950 DEG C of growth temperature range
Standby, specifically may is that makes the reaction gas comprising gallium and nitrogen to the indium gallium nitrogen layer 312 far from the N-type semiconductor
The diffusion into the surface of layer 200；The reaction gas is set to be adsorbed in the surface of the indium gallium nitrogen layer 312；Using pyrolysis or/and
Chemosynthesis reaction forms solid gallium nitride layer 314 on the surface of the indium gallium nitrogen layer 312.Wherein, the chemical vapor deposition
The temperature range of the reaction chamber of area method is 850 DEG C to 950 DEG C.The growth temperature of the i.e. described low-doped gallium nitride layer 314 can be with
It is 850 DEG C, is also possible to 950 DEG C, can also be 900 DEG C.
S330 repeats the above steps 7 to 13 times, to prepare the multiple quantum well layers 310 of 7 to 13 stackings, described in composition
Multi-quantum pit structure layer 300.
Specifically, an indium gallium nitrogen layer 312 and a gallium nitride layer 314 constitute a multiple quantum well layer 310.It is general next
It says, the multiple quantum well layer 310 for constituting the multi-quantum pit structure layer 300 can be 7 to 13 layers.The i.e. described multiple quantum wells knot
Structure layer 300 can be to be formed by 7 310 stacking cycles of multiple quantum well layer, is also possible to by 13 multiple quantum well layers
310 stacking cycles are formed, and be can also be and are formed by 10 310 stacking cycles of multiple quantum well layer.Therefore, it repeats the above steps
S310 and S320 seven to ten three times, form seven to ten three multiple quantum well layers 310, that is, may make up multi-quantum pit structure layer 300.Figure
6 show the embodiment for the multi-quantum pit structure layer 300 being made of two multiple quantum well layers 310.
The light emitting diode 10 that the forming method of above-mentioned light emitting diode is formed, by the composition multiple quantum wells
The multiple quantum well layer 310 of structure carries out quantity restriction, both can be improved compound with electronics in the light emitting diode 10
Number of cavities, and the compound of electronics and hole can be influenced to avoid the multi-quantum pit structure layer 300 is blocked up, thus described in being promoted
The illumination effect of light emitting diode 10.
Further, inventors have found that in the multiple quantum well layer 310, the indium gallium nitrogen layer 312 and the gallium nitride layer
314 thickness difference will affect the illumination effect of the light emitting diode 10.Wherein, when the thickness model of the indium gallium nitrogen layer 312
Enclosing the thickness range for 2nm to 3nm, the gallium nitride layer 314 is 10nm to 12nm, and the multi-quantum pit structure layer 300
When total thickness is 145nm to 165nm, the illumination effect of the light emitting diode 10 is best.I.e. in a Multiple-quantum
In well layer 310, the thickness of the indium gallium nitrogen layer 312 can be 2nm, is also possible to 3nm, can also be 2.5nm.Described in one
In multiple quantum well layer 310, the thickness of the gallium nitride layer 314 can be 10nm, is also possible to 12nm, can also be 11nm.Together
When, the overall thickness of the multi-quantum pit structure layer 300 can be 145nm, is also possible to 165nm, can also be 155nm.
In one embodiment, in the forming method of the light emitting diode, the step S400 be can specifically include:
S410 makes in 740 DEG C to 800 DEG C of growth temperature range and within the scope of the growth pressure of 200 supports to 250 supports
P-type aluminum indium gallium nitride layer 412 is prepared with chemical vapour deposition technique, covers the multi-quantum pit structure layer 300.
Specifically, preparing p-type aluminum indium gallium nitride (Al on multi-quantum pit structure layer 300xInyGa(1-x-y)N) layer 412.Institute
It states p-type aluminum indium gallium nitride layer 412 and covers the multi-quantum pit structure layer 300.The p-type aluminum indium gallium nitride layer 412 can be 740
DEG C in 800 DEG C of growth temperature range, within the scope of the growth pressure of 200 supports to 250 supports and nitrogen (N2), hydrogen (H2) and ammonia
Gas (NH3) mixed gas in prepared using chemical vapour deposition technique.
Further, the step S410 may include: in 740 DEG C to 800 DEG C of growth temperature range and 200 supports
Magnesium-doped aluminum indium gallium nitride layer is prepared using chemical vapour deposition technique within the scope of to the growth pressure of 250 supports, is covered described more
Quantum well structure layer 300.In the i.e. described step S410, p-type aluminum indium gallium nitride layer 412 can be magnesium-doped aluminum indium gallium nitride
Layer.At this point, the step S410 includes:
S411, the growth temperature that reaction chamber is arranged is 740 DEG C to 800 DEG C, and growth pressure is 200 supports to 250 supports, grows gas
Body is the mixed gas of nitrogen, hydrogen and ammonia.In the reaction chamber, multi-quantum pit structure layer 300 is formed by step S300
Surface be passed through range of flow be 25cc/sec to 45cc/sec trimethyl aluminium (TMAl).
S412 keeps the temperature, pressure and gaseous environment of reaction chamber constant, in the reaction chamber, is formed to step S300
Multi-quantum pit structure layer 300 surface synchronization be passed through range of flow be 60cc/sec to 120cc/sec trimethyl gallium
(TMGa)。
S413 keeps the temperature, pressure and gaseous environment of reaction chamber constant, in the reaction chamber, is formed to step S300
Multi-quantum pit structure layer 300 surface synchronization be passed through range of flow be 50cc/sec to 100cc/sec trimethyl indium
(TMIn)。
S414 keeps the temperature, pressure and gaseous environment of reaction chamber constant, in the reaction chamber, is formed to step S300
Multi-quantum pit structure layer 300 surface synchronization be passed through range of flow be 800cc/sec to 1100cc/sec two cyclopentadienyl magnesium
(CP2Mg)。
S415 prepares the trimethyl aluminium, trimethyl gallium, trimethyl indium, nitrogen and two luxuriant magnesium chemical combination described magnesium-doped
Aluminum indium gallium nitride layer.
Wherein, magnesium-doped aluminum indium gallium nitride layer is p-type aluminum indium gallium nitride layer 412.The life of p-type aluminum indium gallium nitride layer 412
Long temperature range is 740 DEG C to 800 DEG C.That is the growth temperature of p-type aluminum indium gallium nitride layer 412 can be 740 DEG C, be also possible to
800 DEG C, it can also be 770 DEG C.The growth pressure range of p-type aluminum indium gallium nitride layer 412 is 200 supports to 250 supports.I.e. p-type nitrogenizes
The growth pressure of aluminium indium gallium layer 412 can be 200 supports, is also possible to 250 supports, can also be 225 supports.P-type aluminum indium gallium nitride layer
412 growth gasses are the mixed gas of nitrogen, hydrogen and ammonia, and the proportion of nitrogen, hydrogen and ammonia are as follows: nitrogen/hydrogen/
Ammonia is 64/120/50L.
S420 continues to prepare magnesium nitride (GaN) layer 414, covers the p-type aluminum indium gallium nitride layer 412.
Specifically, preparing magnesium nitride layer 414 on the p-type aluminum indium gallium nitride layer 412 that step S410 is obtained.The magnesium nitride
The 414 covering p-type aluminum indium gallium nitride layer 412 of layer.The magnesium nitride layer 414 can be in 740 DEG C to 800 DEG C of growth temperature model
It encloses within the scope of interior, 200 supports to 250 supports growth pressures and uses chemical vapor deposition in the mixed gas of nitrogen, hydrogen and ammonia
Area method preparation.
Further, the step S420 includes:
S421 keeps the temperature, pressure and gaseous environment of reaction chamber constant, in the reaction chamber, is formed to step S415
P-type aluminum indium gallium nitride layer 412 the surface two luxuriant magnesium that are passed through that range of flow is 800cc/sec to 1100cc/sec.
The growth temperature for still maintaining reaction chamber is 740 DEG C to 800 DEG C, and growth pressure is 200 supports to 250 supports, growth
Gas is the mixed gas of nitrogen, hydrogen and ammonia, is passed through flow to the surface for reacting indoor p-type aluminum indium gallium nitride layer 412
The two luxuriant magnesium that range is 800cc/sec to 1100cc/sec.
S422 makes described two luxuriant magnesium and nitrogen that combination reaction occur, to obtain magnesium nitride layer 414.The combination reaction
Time is 2 seconds to 4 seconds.
Wherein, the growth temperature range of the magnesium nitride layer 414 is 740 DEG C to 800 DEG C.The i.e. described magnesium nitride layer 414
Growth temperature can be 740 DEG C, be also possible to 800 DEG C, can also be 770 DEG C.The growth pressure range of the magnesium nitride layer 414
For 200 supports to 250 supports.The growth pressure of the i.e. described magnesium nitride layer 414 can be 200 supports, is also possible to 250 supports, can also be
225 supports.The growth gasses of the magnesium nitride layer 414 are the mixed gas of nitrogen, hydrogen and ammonia, and nitrogen, hydrogen and ammonia
Proportion are as follows: nitrogen/hydrogen/ammonia be 64/120/50L.
S430 destroys the bond structures of the p-type aluminum indium gallium nitride layer 412 and the magnesium nitride layer 414, to form one
Draw layer 410 in hole.
Specifically, obtaining the p-type aluminum indium gallium nitride layer 412 in step S420 and covering the p-type aluminum indium gallium nitride layer
After 412 magnesium nitride layer 414, bond structures are carried out to the p-type aluminum indium gallium nitride layer 412 and the magnesium nitride layer 414 and are broken
It is bad.Wherein the bond structures in p-type aluminum indium gallium nitride layer 412 and the magnesium nitride layer 414 include Mg-H key.Therefore, Ke Yitong
It crosses and destroys the bond structures and achieve the purpose that effectively increase number of cavities.
Further, the step S430, specifically:
Growth temperature range is 740 DEG C to 800 DEG C, growth pressure range is that 200 supports are to 250 supports and growth gasses
In the growing environment of the mixed gas of nitrogen and hydrogen, the p-type aluminum indium gallium nitride layer 412 and the magnesium nitride layer 414 are tieed up
Constant temperature is held, to destroy the bond structures of the p-type aluminum indium gallium nitride layer 412 and the magnesium nitride layer 414.
In other words, it after step S420, maintains to react indoor growth temperature and growth pressure is constant, stop mixing
The supply of ammonia in gas gas, is only passed through hydrogen and nitrogen.At this point, i.e. using constant temperature and not supplying ammonia nitrogenizes the p-type
The interatomic bond of aluminium indium gallium layer 412 and the magnesium nitride layer 414 is destroyed.
Wherein, the growth temperature range of step S430 is 740 DEG C to 800 DEG C, and the growth temperature and step of step S430
S420 is identical.The growth pressure range of step S430 is 200 supports to 250 supports, and the growth pressure of step S430 and step S420
It is identical.The growth gasses of step S430 are the mixed gas of hydrogen and nitrogen, and the proportion of hydrogen and nitrogen is that nitrogen/hydrogen is
64/120L。
S440 repeats the above steps 3 to 24 times, draws layer 410 to prepare the hole of 3 to 24 stackings, constitutes the sky
Cave deriving structure layer 400.
Specifically, a p-type aluminum indium gallium nitride layer 412 and a magnesium nitride layer after bond structures destruction
414, which constitute a hole, draws layer 410.In general, layer is drawn in the hole for constituting the hole deriving structure layer 400
410 can be 3 to 24 layers.The i.e. described hole deriving structure layer 400, which can be, draws 410 stacking cycles of layer by 3 holes
It is formed, is also possible to be formed by 24 holes extraction 410 stacking cycles of layer, can also be and draw layers by 14 holes
410 stacking cycles are formed.Therefore, repeat the above steps S410 and S42 tri- to two 14 times, and 14 holes of formation three to two are drawn
Layer 410 out may make up hole deriving structure layer 400.In embodiment shown in Fig. 7, the hole deriving structure layer 400 is only wrapped
It includes the hole that two stackings are formed and draws layer 410.
The forming method of above-mentioned light emitting diode is formed by light emitting diode 10, in 740 DEG C to 800 DEG C of low temperature environment
The middle growth p-type aluminum indium gallium nitride layer 412, can improve the crystal quality of the p-type aluminum indium gallium nitride layer 412, reduce quilt
The number of cavities that the p-type aluminum indium gallium nitride layer 412 captures, to be promoted and the compound number of cavities of electronics.Meanwhile in the ring
The bond structures that the p-type aluminum indium gallium nitride layer 412 is grown in border can be destroyed, to increase number of cavities grade, be promoted empty
The combined efficiency in cave and electronics, and then promote the illumination effect of light emitting diode 10.
In one embodiment, the forming method of the light emitting diode, the p type semiconductor layer 500 can be p-type
Gallium nitride (GaN) layer, i.e., the material of the described p type semiconductor layer 500 are the gallium nitride doped with p type impurity, specifically can be and mix
The gallium nitride of miscellaneous magnesium.
Further, the thickness range of the p type semiconductor layer 500 can be 80nm to 120nm, growth temperature range
It can be 900 DEG C to 1100 DEG C.Specifically, the thickness of the p type semiconductor layer 500 can be 80nm, be also possible to
120nm can also be 100nm.The growth temperature range of the p type semiconductor layer 500 can be 900 DEG C, or 1100
DEG C, it can also be 1000 DEG C.Chemical vapour deposition technique preparation also can be used in the p type semiconductor layer 500, repeats no more.
The application also provides a kind of light emitting diode 10, is prepared based on the above embodiment, including substrate 100, N-type
Semiconductor layer 200, multi-quantum pit structure layer 300, hole deriving structure layer 400 and p type semiconductor layer 500.
Specifically, the substrate 100 is located at the bottom of the light emitting diode 10, generally can be Sapphire Substrate or
Other kinds of substrate.
The n type semiconductor layer 200 is located at 100 top of substrate, to generate electronics under electric field action.The N-type
Semiconductor layer 200 generally can be the semiconductor layer doped with N-type impurity.
The multi-quantum pit structure layer 300 is located among the n type semiconductor layer 200 and the p type semiconductor layer 500,
For improving the combined efficiency of electrons and holes.The multi-quantum pit structure layer 300 may include generally that staggered quantum is laminated
Trap and quantum are built.
The hole deriving structure layer 400 is located in the multi-quantum pit structure layer 300 and the p type semiconductor layer 500
Between, for promoting number of cavities, to increase and the compound number of cavities of electronics.The hole deriving structure layer 400 can wrap
Include the p-type aluminum indium gallium nitride layer 412 and the magnesium nitride layer 414 being stacked.Magnesium nitride (GaN) layer 414 covers
P-type aluminum indium gallium nitride (the AlxInyGa(1-x-y)N) layer 412.
The p type semiconductor layer 500 generally can be for generating hole under electric field action doped with p type impurity
Semiconductor layer.The p type semiconductor layer 500 is located at 400 top of hole deriving structure layer, that is, is located at the hole and draws
Side of the structure sheaf 400 far from the multi-quantum pit structure layer 300.
When the light emitting diode 10 is powered, the n type semiconductor layer 200 generates electronics and under electric field action to described
300 direction of multi-quantum pit structure layer is mobile.The p type semiconductor layer 500 generates hole and under electric field action to the volume
Sub- 300 direction of well structure layer is mobile.Meanwhile the hole deriving structure layer can produce a large amount of holes and to the multiple quantum wells
300 direction of structure sheaf is mobile, to increase the quantity with the compound hole of electronics.This method is formed by the light emitting diode
10, hole is generated by the p-type aluminum indium gallium nitride layer 412 and the magnesium nitride layer 414, the sky compound with electronics can be promoted
The quantity and density in cave, and then the recombination probability in hole and electronics is promoted, promote the illumination effect of the light emitting diode 10.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (11)
1. a kind of forming method of light emitting diode characterized by comprising
It provides substrate (100), the substrate (100) has the first surface (102) and second surface (104) being oppositely arranged；
N type semiconductor layer (200) are prepared, the first surface (102) are covered；
Multi-quantum pit structure layer (300) are prepared, the n type semiconductor layer (200) are covered；
It prepares hole deriving structure layer (400), covers the multi-quantum pit structure layer (300), the hole deriving structure layer
It (400) include p-type aluminum indium gallium nitride layer (412) and magnesium nitride layer (414), the p-type aluminum indium gallium nitride layer (412) is set to institute
It states between magnesium nitride layer (414) and the multi-quantum pit structure layer (300)；And
P type semiconductor layer (500) are prepared, the hole deriving structure layer (400) is covered.
2. the forming method of light emitting diode according to claim 1, which is characterized in that preparation hole deriving structure
Layer (400), covers the multi-quantum pit structure layer (300), comprising:
Chemical gaseous phase is used in 740 DEG C to 800 DEG C of growth temperature range and within the scope of the growth pressure of 200 supports to 250 supports
Sedimentation prepares the p-type aluminum indium gallium nitride layer (412), covers the multi-quantum pit structure layer (300)；
Continue to prepare magnesium nitride layer (414), covers the p-type aluminum indium gallium nitride layer (412)；
The bond structures of the p-type aluminum indium gallium nitride layer (412) and the magnesium nitride layer (414) are destroyed, to form a hole
It draws layer (410)；
It repeats the above steps 3 to 24 times, draws layer (410) to prepare the hole of 3 to 24 stackings, constitute the hole and draw knot
Structure layer (400).
3. the forming method of light emitting diode according to claim 2, which is characterized in that the p-type aluminum indium gallium nitride layer
It (412) is magnesium-doped aluminum indium gallium nitride layer.
4. the forming method of light emitting diode according to claim 3, which is characterized in that described at 740 DEG C to 800 DEG C
P-type aluminium nitride is prepared in growth temperature range and using chemical vapour deposition technique within the scope of the growth pressure of 200 supports to 250 supports
Indium gallium layer (412) covers the multi-quantum pit structure layer (300), comprising: is 740 DEG C to 800 DEG C, gives birth in growth temperature range
Long pressure limit is 200 supports to 250 supports and growth gasses are in the growing environment of mixed gas of nitrogen, hydrogen and ammonia,
It is passed through the trimethyl aluminium that range of flow is 25cc/sec to 45cc/sec；
It is passed through the trimethyl gallium that range of flow is 60cc/sec to 120cc/sec；
It is passed through the trimethyl indium that range of flow is 50cc/sec to 100cc/sec；
It is passed through the two luxuriant magnesium that range of flow is 800cc/sec to 1100cc/sec；
The trimethyl aluminium, trimethyl gallium, trimethyl indium, nitrogen and two luxuriant magnesium chemical combination are made to prepare the magnesium-doped aluminum indium gallium nitride
Layer.
5. the forming method of light emitting diode according to claim 2, which is characterized in that described to continue to prepare magnesium nitride layer
(414), the p-type aluminum indium gallium nitride layer (412) is covered, comprising: in growth temperature range be 740 DEG C to 800 DEG C, growth pressure
Range is 200 supports to 250 supports and growth gasses are in the growing environment of mixed gas of nitrogen, hydrogen and ammonia,
The two luxuriant magnesium that range of flow is 800cc/sec to 1100cc/sec are passed through, carry out described two luxuriant magnesium and nitrogen 2 to 4 seconds
Chemical combination prepares the magnesium nitride layer (414).
6. the forming method of light emitting diode according to claim 2, which is characterized in that described to destroy the p-type nitridation
The bond structures of aluminium indium gallium layer (412) and the magnesium nitride layer (414) draw layer (410) to form a hole, comprising:
Growth temperature range is 740 DEG C to 800 DEG C, growth pressure range is that 200 supports to 250 supports and growth gasses are nitrogen
In the growing environment of the mixed gas of hydrogen, the p-type aluminum indium gallium nitride layer (412) and the magnesium nitride layer (414) are tieed up
Constant temperature is held, to destroy the bond structures of the p-type aluminum indium gallium nitride layer (412) and the magnesium nitride layer (414).
7. the forming method of light emitting diode according to claim 1, which is characterized in that preparing multi-quantum pit structure layer
(300), before covering the n type semiconductor layer (200), further includes:
Strain relief layer (600) are prepared, are covered the n type semiconductor layer (200), the strain relief layer (600)
It is set between the multi-quantum pit structure layer (300) and the n type semiconductor layer (200).
8. the forming method of light emitting diode according to claim 7, which is characterized in that described to prepare strain relief
Layer (600), covers the n type semiconductor layer (200), specifically includes: in 850 DEG C to 950 DEG C of growth temperature range,
Indium gallium nitrogen layer (612) is prepared using chemical vapour deposition technique, covers the n type semiconductor layer (200)；
Low-doped gallium nitride layer (614) are prepared using chemical vapour deposition technique, cover the indium gallium nitrogen layer (612), to be formed
One stress release layer (610)；
It repeats the above steps 3 to 9 times, to prepare the stress release layer (610) of 3 to 9 stackings, constitutes the stress release knot
Structure layer (600).
9. the forming method of light emitting diode according to claim 1, which is characterized in that described to prepare multi-quantum pit structure
Layer (300), covers the n type semiconductor layer (200), comprising:
Indium gallium nitrogen layer (312) is prepared using chemical vapour deposition technique in 780 DEG C to 830 DEG C of growth temperature range, covers institute
State n type semiconductor layer (200)；
Growth temperature range is adjusted to 850 DEG C to 930 DEG C, is prepared gallium nitride layer (314) using chemical vapour deposition technique, institute is covered
Indium gallium nitrogen layer (312) is stated, to form a multiple quantum well layer (310)；
It repeats the above steps 7 to 13 times, to prepare the multiple quantum well layer (310) of 7 to 13 stackings, constitutes the multiple quantum wells knot
Structure layer (300).
10. the forming method of light emitting diode according to claim 9, which is characterized in that the indium gallium nitrogen layer (312)
Thickness range is 2nm to 3nm, and the thickness range of the gallium nitride layer (314) is 10nm to 12nm；
The thickness range of the multi-quantum pit structure layer (300) is 145nm to 165nm.
11. a kind of light emitting diode, based on forming method described in claims 1 to 10 any one, which is characterized in that packet
It includes:
Substrate (100)；
N type semiconductor layer (200) covers the substrate (100)；
Multi-quantum pit structure layer (300) covers the n type semiconductor layer (200)；
Hole deriving structure layer (400) covers the multi-quantum pit structure layer (300), hole deriving structure layer (400) packet
P-type aluminum indium gallium nitride layer (412) and magnesium nitride layer (414) are included, the magnesium nitride layer (414) covers the p-type aluminum indium gallium nitride
Layer (412)；
P type semiconductor layer (500) covers the hole deriving structure layer (400).
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